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1 /*
2 * Copyright (c) 2007-2018 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /* CMU_ENDHIST */
32 /*
33 * Mach Operating System
34 * Copyright (c) 1991,1990 Carnegie Mellon University
35 * All Rights Reserved.
36 *
37 * Permission to use, copy, modify and distribute this software and its
38 * documentation is hereby granted, provided that both the copyright
39 * notice and this permission notice appear in all copies of the
40 * software, derivative works or modified versions, and any portions
41 * thereof, and that both notices appear in supporting documentation.
42 *
43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
46 *
47 * Carnegie Mellon requests users of this software to return to
48 *
49 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
50 * School of Computer Science
51 * Carnegie Mellon University
52 * Pittsburgh PA 15213-3890
53 *
54 * any improvements or extensions that they make and grant Carnegie Mellon
55 * the rights to redistribute these changes.
56 */
57
58 /*
59 */
60
61 /*
62 * Processor registers for ARM
63 */
64 #ifndef _ARM_PROC_REG_H_
65 #define _ARM_PROC_REG_H_
66
67 #if defined (__arm64__)
68 #include <pexpert/arm64/board_config.h>
69 #elif defined (__arm__)
70 #include <pexpert/arm/board_config.h>
71 #endif
72
73 #if defined (ARMA7)
74 #define __ARM_ARCH__ 7
75 #define __ARM_SUB_ARCH__ CPU_ARCH_ARMv7k
76 #define __ARM_VMSA__ 7
77 #define __ARM_VFP__ 3
78
79 /* Force physical aperture to be mapped at PTE level so that its mappings
80 * can be updated to reflect cache attribute changes on alias mappings. This prevents
81 * prefetched physical aperture cachelines from becoming dirty in L1 due to a write to
82 * an uncached alias mapping on the same core. Subsequent uncached writes from another
83 * core may not snoop this line, and the dirty line may end up being evicted later to
84 * effectively overwrite the uncached writes from other cores. */
85 #define __ARM_PTE_PHYSMAP__ 1
86 /* __ARMA7_SMP__ controls whether we are consistent with the A7 MP_CORE spec; needed because entities other than
87 * the xnu-managed processors may need to snoop our cache operations.
88 */
89 #define __ARMA7_SMP__ 1
90 #define __ARM_COHERENT_CACHE__ 1
91 #define __ARM_DEBUG__ 7
92 #define __ARM_USER_PROTECT__ 1
93 #define __ARM_TIME_TIMEBASE_ONLY__ 1
94
95 #endif
96
97 #if __ARM_42BIT_PA_SPACE__
98 /* For now, force the issue! */
99 /* We need more VA space for the identity map to bootstrap the MMU */
100 #undef __ARM64_PMAP_SUBPAGE_L1__
101 #endif /* __ARM_42BIT_PA_SPACE__ */
102
103 #if __ARM_KERNEL_PROTECT__
104 /*
105 * This feature is not currently implemented for 32-bit ARM CPU architectures.
106 * A discussion of this feature for 64-bit ARM CPU architectures can be found
107 * in the ARM64 version of this file.
108 */
109 #if __arm__
110 #error __ARM_KERNEL_PROTECT__ is not supported on ARM32
111 #endif /* __arm__ */
112 #endif /* __ARM_KERNEL_PROTECT__ */
113
114 #if defined(ARM_BOARD_WFE_TIMEOUT_NS)
115 #define __ARM_ENABLE_WFE_ 1
116 #else /* defined(ARM_BOARD_WFE_TIMEOUT_NS) */
117 #define __ARM_ENABLE_WFE_ 0
118 #endif /* defined(ARM_BOARD_WFE_TIMEOUT_NS) */
119
120 /*
121 * MAX_PSETS allows the scheduler to create statically sized
122 * scheduling data structures (such as an array of processor sets, clutch
123 * buckets in Edge scheduler etc.). All current AMP platforms are dual
124 * pset and all non-AMP platforms are single pset architectures. This
125 * define might need to be conditionalized better (or moved to a better
126 * header) in the future.
127 *
128 * <Edge Multi-cluster Support Needed>
129 */
130 #if __ARM_AMP__
131 #define MAX_PSETS 2
132 #else /*__ARM_AMP__ */
133 #define MAX_PSETS 1
134 #endif /* __ARM_AMP__ */
135
136 /*
137 * The clutch scheduler is enabled only on non-AMP platforms for now.
138 */
139 #if CONFIG_CLUTCH
140
141 #if __ARM_AMP__
142
143 /* Enable the Edge scheduler for all J129 platforms */
144 #if XNU_TARGET_OS_OSX
145 #define CONFIG_SCHED_CLUTCH 1
146 #define CONFIG_SCHED_EDGE 1
147 #endif /* XNU_TARGET_OS_OSX */
148
149 #else /* __ARM_AMP__ */
150 #define CONFIG_SCHED_CLUTCH 1
151 #endif /* __ARM_AMP__ */
152
153 #endif /* CONFIG_CLUTCH */
154
155 /* Thread groups are enabled on all ARM platforms (irrespective of scheduler) */
156 #define CONFIG_THREAD_GROUPS 1
157
158 #ifdef XNU_KERNEL_PRIVATE
159
160 #if __ARM_VFP__
161 #define ARM_VFP_DEBUG 0
162 #endif /* __ARM_VFP__ */
163
164 #endif /* XNU_KERNEL_PRIVATE */
165
166
167
168 /*
169 * FSR registers
170 *
171 * CPSR: Current Program Status Register
172 * SPSR: Saved Program Status Registers
173 *
174 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0
175 * +-----------------------------------------------------------+
176 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE |
177 * +-----------------------------------------------------------+
178 */
179
180 /*
181 * Flags
182 */
183 #define PSR_NF 0x80000000 /* Negative/Less than */
184 #define PSR_ZF 0x40000000 /* Zero */
185 #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */
186 #define PSR_VF 0x10000000 /* Overflow */
187 #define PSR_QF 0x08000000 /* saturation flag (QADD ARMv5) */
188
189 /*
190 * Modified execution mode flags
191 */
192 #define PSR_JF 0x01000000 /* Jazelle flag (BXJ ARMv5) */
193 #define PSR_EF 0x00000200 /* mixed-endian flag (SETEND ARMv6) */
194 #define PSR_AF 0x00000100 /* precise abort flag (ARMv6) */
195 #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */
196 #define PSR_TFb 5 /* thumb flag (BX ARMv4T) */
197
198 /*
199 * Interrupts
200 */
201 #define PSR_IRQFb 7 /* IRQ : 0 = IRQ enable */
202 #define PSR_IRQF 0x00000080 /* IRQ : 0 = IRQ enable */
203 #define PSR_FIQF 0x00000040 /* FIQ : 0 = FIQ enable */
204
205 /*
206 * CPU mode
207 */
208 #define PSR_USER_MODE 0x00000010 /* User mode */
209 #define PSR_FIQ_MODE 0x00000011 /* FIQ mode */
210 #define PSR_IRQ_MODE 0x00000012 /* IRQ mode */
211 #define PSR_SVC_MODE 0x00000013 /* Supervisor mode */
212 #define PSR_ABT_MODE 0x00000017 /* Abort mode */
213 #define PSR_UND_MODE 0x0000001B /* Undefined mode */
214
215 #define PSR_MODE_MASK 0x0000001F
216 #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE)
217 #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE)
218
219 #define PSR_USERDFLT PSR_USER_MODE
220 #define PSR_USER_MASK (PSR_AF | PSR_IRQF | PSR_FIQF | PSR_MODE_MASK)
221 #define PSR_USER_SET PSR_USER_MODE
222
223 #define PSR_INTMASK PSR_IRQF /* Interrupt disable */
224
225 /*
226 * FPEXC: Floating-Point Exception Register
227 */
228
229 #define FPEXC_EX 0x80000000 /* Exception status */
230 #define FPEXC_EX_BIT 31
231 #define FPEXC_EN 0x40000000 /* VFP : 1 = EN enable */
232 #define FPEXC_EN_BIT 30
233
234
235 /*
236 * FPSCR: Floating-point Status and Control Register
237 */
238
239 #define FPSCR_DN 0x02000000 /* Default NaN */
240 #define FPSCR_FZ 0x01000000 /* Flush to zero */
241
242 #define FPSCR_DEFAULT FPSCR_DN | FPSCR_FZ
243
244
245 /*
246 * FSR registers
247 *
248 * IFSR: Instruction Fault Status Register
249 * DFSR: Data Fault Status Register
250 */
251 #define FSR_ALIGN 0x00000001 /* Alignment */
252 #define FSR_DEBUG 0x00000002 /* Debug (watch/break) */
253 #define FSR_ICFAULT 0x00000004 /* Fault on instruction cache maintenance */
254 #define FSR_SFAULT 0x00000005 /* Translation Section */
255 #define FSR_PFAULT 0x00000007 /* Translation Page */
256 #define FSR_SACCESS 0x00000003 /* Section access */
257 #define FSR_PACCESS 0x00000006 /* Page Access */
258 #define FSR_SDOM 0x00000009 /* Domain Section */
259 #define FSR_PDOM 0x0000000B /* Domain Page */
260 #define FSR_SPERM 0x0000000D /* Permission Section */
261 #define FSR_PPERM 0x0000000F /* Permission Page */
262 #define FSR_EXT 0x00001000 /* External (Implementation Defined Classification) */
263
264 #define FSR_MASK 0x0000040F /* Valid bits */
265 #define FSR_ALIGN_MASK 0x0000040D /* Valid bits to check align */
266
267 #define DFSR_WRITE 0x00000800 /* write data abort fault */
268
269 #if defined (ARMA7) || defined (APPLE_ARM64_ARCH_FAMILY) || defined (BCM2837)
270
271 #define TEST_FSR_VMFAULT(status) \
272 (((status) == FSR_PFAULT) \
273 || ((status) == FSR_PPERM) \
274 || ((status) == FSR_SFAULT) \
275 || ((status) == FSR_SPERM) \
276 || ((status) == FSR_ICFAULT) \
277 || ((status) == FSR_SACCESS) \
278 || ((status) == FSR_PACCESS))
279
280 #define TEST_FSR_TRANSLATION_FAULT(status) \
281 (((status) == FSR_SFAULT) \
282 || ((status) == FSR_PFAULT))
283
284 #else
285
286 #error Incompatible CPU type configured
287
288 #endif
289
290 /*
291 * Cache configuration
292 */
293
294 #if defined (ARMA7)
295
296 /* I-Cache */
297 #define MMU_I_CLINE 5 /* cache line size as 1<<MMU_I_CLINE (32) */
298
299 /* D-Cache */
300 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
301
302 #elif defined (APPLETYPHOON)
303
304 /* I-Cache */
305 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
306
307 /* D-Cache */
308 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
309
310 #elif defined (APPLETWISTER)
311
312 /* I-Cache */
313 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
314
315 /* D-Cache */
316 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
317
318 #elif defined (APPLEHURRICANE)
319
320 /* I-Cache */
321 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
322
323 /* D-Cache */
324 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
325
326 #elif defined (APPLEMONSOON)
327
328 /* I-Cache, 96KB for Monsoon, 48KB for Mistral, 6-way. */
329 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
330
331 /* D-Cache, 64KB for Monsoon, 32KB for Mistral, 4-way. */
332 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
333
334 #elif defined (APPLEVORTEX)
335
336 /* I-Cache, 128KB 8-way for Vortex, 48KB 6-way for Tempest. */
337 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
338
339 /* D-Cache, 128KB 8-way for Vortex, 32KB 4-way for Tempest. */
340 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
341
342 #elif defined (APPLELIGHTNING)
343
344 /* I-Cache, 192KB for Lightning, 96KB for Thunder, 6-way. */
345 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
346
347 /* D-Cache, 128KB for Lightning, 8-way. 48KB for Thunder, 6-way. */
348 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
349
350 #elif defined (BCM2837) /* Raspberry Pi 3 */
351
352 /* I-Cache. We don't have detailed spec so we just follow the ARM technical reference. */
353 #define MMU_I_CLINE 6
354
355 /* D-Cache. */
356 #define MMU_CLINE 6
357
358 #else
359 #error processor not supported
360 #endif
361
362
363 #if (__ARM_VMSA__ <= 7)
364
365 /*
366 * SCTLR: System Control Register
367 */
368 /*
369 * System Control Register (SCTLR)
370 *
371 * 31 30 29 28 27 25 24 22 21 20 19 17 15 14 13 12 11 10 5 2 1 0
372 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
373 * |0|TE|AFE|TRE|NMFI|0|EE|VE|11|FI|UWXN|WXN|1|HA|1|0|RR| V| I| Z|SW|000|1|C15BEN|11|C|A|M|
374 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
375 *
376 * Where:
377 * TE: Thumb Exception enable
378 * AFE: Access flag enable
379 * TRE: TEX remap enable
380 * NMFI: Non-maskable FIQ (NMFI) support
381 * EE: Exception Endianness
382 * VE: Interrupt Vectors Enable
383 * FI: Fast interrupts configuration enable
384 * ITD: IT Disable
385 * UWXN: Unprivileged write permission implies PL1 XN
386 * WXN: Write permission implies XN
387 * HA: Hardware Access flag enable
388 * RR: Round Robin select
389 * V: High exception vectors
390 * I: Instruction cache enable
391 * Z: Branch prediction enable
392 * SW: SWP/SWPB enable
393 * C15BEN: CP15 barrier enable
394 * C: Cache enable
395 * A: Alignment check enable
396 * M: MMU enable
397 */
398
399 #define SCTLR_RESERVED 0x82DD8394
400
401 #define SCTLR_ENABLE 0x00000001 /* MMU enable */
402 #define SCTLR_ALIGN 0x00000002 /* Alignment check enable */
403 #define SCTLR_DCACHE 0x00000004 /* Data or Unified Cache enable */
404 #define SCTLR_BEN 0x00000040 /* CP15 barrier enable */
405 #define SCTLR_SW 0x00000400 /* SWP/SWPB Enable */
406 #define SCTLR_PREDIC 0x00000800 /* Branch prediction enable */
407 #define SCTLR_ICACHE 0x00001000 /* Instruction cache enabled. */
408 #define SCTLR_HIGHVEC 0x00002000 /* Vector table at 0xffff0000 */
409 #define SCTLR_RROBIN 0x00004000 /* Round Robin replacement */
410 #define SCTLR_HA 0x00020000 /* Hardware Access flag enable */
411 #define SCTLR_NMFI 0x08000000 /* Non-maskable FIQ */
412 #define SCTLR_TRE 0x10000000 /* TEX remap enable */
413 #define SCTLR_AFE 0x20000000 /* Access flag enable */
414 #define SCTLR_TE 0x40000000 /* Thumb Exception enable */
415
416 #define SCTLR_DEFAULT \
417 (SCTLR_AFE|SCTLR_TRE|SCTLR_HIGHVEC|SCTLR_ICACHE|SCTLR_PREDIC|SCTLR_DCACHE|SCTLR_ENABLE)
418
419
420 /*
421 * PRRR: Primary Region Remap Register
422 *
423 * 31 24 20 19 18 17 16 0
424 * +---------------------------------------------------------------+
425 * | NOSn | Res |NS1|NS0|DS1|DS0| TRn |
426 * +---------------------------------------------------------------+
427 */
428
429 #define PRRR_NS1 0x00080000
430 #define PRRR_NS0 0x00040000
431 #define PRRR_DS1 0x00020000
432 #define PRRR_DS0 0x00010000
433
434 #define PRRR_NOSn_ISH(region) (0x1<<((region)+24))
435
436 #if defined (ARMA7)
437 #define PRRR_SETUP (0x1F08022A)
438 #else
439 #error processor not supported
440 #endif
441
442 /*
443 * NMRR, Normal Memory Remap Register
444 *
445 * 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
446 * +---------------------------------------------------------------+
447 * |OR7|OR6|OR5|OR4|OR3|OR2|OR1|OR0|IR7|IR6|IR5|IR4|IR3|IR2|IR1|IR0|
448 * +---------------------------------------------------------------+
449 */
450
451 #define NMRR_DISABLED 0x0 /* Non-cacheable */
452 #define NMRR_WRITEBACK 0x1 /* Write-Back, Write-Allocate */
453 #define NMRR_WRITETHRU 0x2 /* Write-Through, no Write-Allocate */
454 #define NMRR_WRITEBACKNO 0x3 /* Write-Back, no Write-Allocate */
455
456 #if defined (ARMA7)
457 #define NMRR_SETUP (0x01210121)
458 #else
459 #error processor not supported
460 #endif
461
462 /*
463 * TTBR: Translation Table Base Register
464 *
465 */
466
467 #define TTBR_IRGN_DISBALED 0x00000000 /* inner non-cacheable */
468 #define TTBR_IRGN_WRITEBACK 0x00000040 /* inner write back and allocate */
469 #define TTBR_IRGN_WRITETHRU 0x00000001 /* inner write thru */
470 #define TTBR_IRGN_WRITEBACKNO 0x00000041 /* inner write back no allocate */
471
472 #define TTBR_RGN_DISBALED 0x00000000 /* outer non-cacheable */
473 #define TTBR_RGN_WRITEBACK 0x00000008 /* outer write back and allocate */
474 #define TTBR_RGN_WRITETHRU 0x00000010 /* outer write thru outer cache */
475 #define TTBR_RGN_WRITEBACKNO 0x00000018 /* outer write back no allocate */
476
477 #define TTBR_SHARED 0x00000002 /* Shareable memory atribute */
478 #define TTBR_SHARED_NOTOUTER 0x00000020 /* Outer not shareable memory atribute */
479
480 #if defined (ARMA7)
481 #define TTBR_SETUP (TTBR_RGN_WRITEBACK|TTBR_IRGN_WRITEBACK|TTBR_SHARED)
482 #else
483 #error processor not supported
484 #endif
485
486 /*
487 * TTBCR: Translation Table Base Control register
488 *
489 * 31 3 2 0
490 * +----------+
491 * | zero | N |
492 * +----------+
493 *
494 * If N=0, always use translation table base register 0. Otherwise, if
495 * bits [31:32-N] of the address are all zero use base register 0. Otherwise,
496 * use base register 1.
497 *
498 * Reading from this register also returns the page table boundary for TTB0.
499 * Writing to it updates the boundary for TTB0. (0=16KB, 1=8KB, 2=4KB, etc...)
500 */
501
502 #define TTBCR_N_1GB_TTB0 0x2 /* 1 GB TTB0, 3GB TTB1 */
503 #define TTBCR_N_2GB_TTB0 0x1 /* 2 GB TTB0, 2GB TTB1 */
504 #define TTBCR_N_4GB_TTB0 0x0 /* 4 GB TTB0 */
505 #define TTBCR_N_MASK 0x3
506
507 #define TTBCR_N_SETUP (TTBCR_N_2GB_TTB0)
508
509
510
511 /*
512 * ARM Page Granule
513 */
514 #define ARM_PGSHIFT 12
515 #define ARM_PGBYTES (1 << ARM_PGSHIFT)
516 #define ARM_PGMASK (ARM_PGBYTES-1)
517
518 /*
519 * DACR: Domain Access Control register
520 */
521
522 #define DAC_FAULT 0x0 /* invalid domain - everyone loses */
523 #define DAC_CLIENT 0x1 /* client domain - use AP bits */
524 #define DAC_RESERVE 0x2 /* reserved domain - undefined */
525 #define DAC_MANAGER 0x3 /* manager domain - all access */
526
527 #define DACR_SET(dom, x) ((x)<<((dom)<<1))
528
529
530 #define ARM_DOM_DEFAULT 0 /* domain that forces AP use */
531 #define ARM_DAC_SETUP 0x1
532
533 /*
534 * ARM 2-level Page Table support
535 */
536
537 /*
538 * Memory Attribute Index
539 */
540 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled */
541 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes */
542 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled */
543 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer */
544 #define CACHE_ATTRINDX_INNERWRITEBACK 0x4 /* inner cache enabled, buffer enabled, write allocate */
545 #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE
546 #define CACHE_ATTRINDX_POSTED_REORDERED CACHE_ATTRINDX_DISABLE
547 #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED CACHE_ATTRINDX_DISABLE
548 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK
549
550
551 /*
552 * Access protection bit values
553 */
554 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */
555 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */
556 #define AP_RONA 0x2 /* priv=read-only , user=no-access */
557 #define AP_RORO 0x3 /* priv=read-only , user=read-only */
558
559 /*
560 * L1 Translation table
561 *
562 * Each translation table is up to 16KB
563 * 4096 32-bit entries of 1MB of address space.
564 */
565
566 #define ARM_TT_L1_SIZE 0x00100000 /* size of area covered by a tte */
567 #define ARM_TT_L1_OFFMASK 0x000FFFFF /* offset within an L1 entry */
568 #define ARM_TT_L1_TABLE_OFFMASK 0x000FFFFF /* offset within an L1 entry */
569 #define ARM_TT_L1_BLOCK_OFFMASK 0x000FFFFF /* offset within an L1 entry */
570 #define ARM_TT_L1_SUPER_OFFMASK 0x00FFFFFF /* offset within an L1 entry */
571 #define ARM_TT_L1_SHIFT 20 /* page descriptor shift */
572 #define ARM_TT_L1_INDEX_MASK 0xfff00000 /* mask for getting index in L1 table from virtual address */
573
574 #define ARM_TT_L1_PT_SIZE (4 * ARM_TT_L1_SIZE) /* 4 L1 table entries required to consume 1 L2 pagetable page */
575 #define ARM_TT_L1_PT_OFFMASK (ARM_TT_L1_PT_SIZE - 1)
576
577 /*
578 * L2 Translation table
579 *
580 * Each translation table is up to 1KB
581 * 4096 32-bit entries of 1MB (2^30) of address space.
582 */
583
584 #define ARM_TT_L2_SIZE 0x00001000 /* size of area covered by a tte */
585 #define ARM_TT_L2_OFFMASK 0x00000FFF /* offset within an L2 entry */
586 #define ARM_TT_L2_SHIFT 12 /* page descriptor shift */
587 #define ARM_TT_L2_INDEX_MASK 0x000ff000 /* mask for getting index in L2 table from virtual address */
588
589 /*
590 * Convenience definitions for:
591 * ARM_TT_LEAF: The last level of the configured page table format.
592 * ARM_TT_TWIG: The second to last level of the configured page table format.
593 * ARM_TT_ROOT: The first level of the configured page table format.
594 *
595 * My apologies to any botanists who may be reading this.
596 */
597 #define ARM_TT_LEAF_SIZE ARM_TT_L2_SIZE
598 #define ARM_TT_LEAF_OFFMASK ARM_TT_L2_OFFMASK
599 #define ARM_TT_LEAF_SHIFT ARM_TT_L2_SHIFT
600 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L2_INDEX_MASK
601
602 #define ARM_TT_TWIG_SIZE ARM_TT_L1_SIZE
603 #define ARM_TT_TWIG_OFFMASK ARM_TT_L1_OFFMASK
604 #define ARM_TT_TWIG_SHIFT ARM_TT_L1_SHIFT
605 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L1_INDEX_MASK
606
607 #define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE
608 #define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK
609 #define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT
610 #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK
611
612 /*
613 * Level 1 Translation Table Entry
614 *
615 * page table entry
616 *
617 * 31 10 9 8 5 4 2 0
618 * +----------------------+-+----+--+--+--+
619 * | page table base addr | |dom |XN|00|01|
620 * +----------------------+-+----+--+--+--+
621 *
622 * direct (1MB) section entry
623 *
624 * 31 20 18 15 12 10 9 8 5 4 2 0
625 * +------------+--+-+-+-+---+--+-+----+--+--+--+
626 * | base addr |00|G|S|A|TEX|AP| |dom |XN|CB|10|
627 * +------------+--+-+-+-+---+--+-+----+--+--+--+
628 *
629 * super (16MB) section entry
630 *
631 * 31 24 23 18 15 12 10 9 8 5 4 2 0
632 * +---------+------+-+-+-+---+--+-+----+--+--+--+
633 * |base addr|000001|G|S|A|TEX|AP| |dom |XN|CB|10|
634 * +---------+------+-+-+-+---+--+-+----+--+--+--+
635 *
636 * where:
637 * 'G' is the notGlobal bit
638 * 'S' is the shared bit
639 * 'A' in the access permission extension (APX) bit
640 * 'TEX' remap register control bits
641 * 'AP' is the access protection
642 * 'dom' is the domain for the translation
643 * 'XN' is the eXecute Never bit
644 * 'CB' is the cache/buffer attribute
645 */
646
647 #define ARM_TTE_EMPTY 0x00000000 /* unasigned entry */
648
649 #define ARM_TTE_TYPE_FAULT 0x00000000 /* fault entry type */
650 #define ARM_TTE_TYPE_TABLE 0x00000001 /* page table type */
651 #define ARM_TTE_TYPE_BLOCK 0x00000002 /* section entry type */
652 #define ARM_TTE_TYPE_MASK 0x00000003 /* mask for extracting the type */
653
654 #define ARM_TTE_BLOCK_NGSHIFT 17
655 #define ARM_TTE_BLOCK_NG_MASK 0x00020000 /* mask to determine notGlobal bit */
656 #define ARM_TTE_BLOCK_NG 0x00020000 /* value for a per-process mapping */
657
658 #define ARM_TTE_BLOCK_SHSHIFT 16
659 #define ARM_TTE_BLOCK_SH_MASK 0x00010000 /* shared (SMP) mapping mask */
660 #define ARM_TTE_BLOCK_SH 0x00010000 /* shared (SMP) mapping */
661
662 #define ARM_TTE_BLOCK_CBSHIFT 2
663 #define ARM_TTE_BLOCK_CB(x) ((x) << ARM_TTE_BLOCK_CBSHIFT)
664 #define ARM_TTE_BLOCK_CB_MASK (3<< ARM_TTE_BLOCK_CBSHIFT)
665
666 #define ARM_TTE_BLOCK_AP0SHIFT 10
667 #define ARM_TTE_BLOCK_AP0 (1<<ARM_TTE_BLOCK_AP0SHIFT)
668 #define ARM_TTE_BLOCK_AP0_MASK (1<<ARM_TTE_BLOCK_AP0SHIFT)
669
670 #define ARM_TTE_BLOCK_AP1SHIFT 11
671 #define ARM_TTE_BLOCK_AP1 (1<<ARM_TTE_BLOCK_AP1SHIFT)
672 #define ARM_TTE_BLOCK_AP1_MASK (1<<ARM_TTE_BLOCK_AP1SHIFT)
673
674 #define ARM_TTE_BLOCK_AP2SHIFT 15
675 #define ARM_TTE_BLOCK_AP2 (1<<ARM_TTE_BLOCK_AP2SHIFT)
676 #define ARM_TTE_BLOCK_AP2_MASK (1<<ARM_TTE_BLOCK_AP2SHIFT)
677
678 /* access protections */
679 #define ARM_TTE_BLOCK_AP(ap) \
680 ((((ap)&0x1)<<ARM_TTE_BLOCK_AP1SHIFT) | \
681 ((((ap)>>1)&0x1)<<ARM_TTE_BLOCK_AP2SHIFT))
682
683 /* mask access protections */
684 #define ARM_TTE_BLOCK_APMASK \
685 (ARM_TTE_BLOCK_AP1_MASK | ARM_TTE_BLOCK_AP2_MASK)
686
687 #define ARM_TTE_BLOCK_AF ARM_TTE_BLOCK_AP0 /* value for access */
688 #define ARM_TTE_BLOCK_AFMASK ARM_TTE_BLOCK_AP0_MASK /* access mask */
689
690 #define ARM_TTE_TABLE_MASK 0xFFFFFC00 /* mask for a L2 page table entry */
691 #define ARM_TTE_TABLE_SHIFT 10 /* shift for L2 page table phys address */
692
693 #define ARM_TTE_BLOCK_L1_MASK 0xFFF00000 /* mask to extract phys address from L1 section entry */
694 #define ARM_TTE_BLOCK_L1_SHIFT 20 /* shift for 1MB section phys address */
695
696 #define ARM_TTE_SUPER_L1_MASK 0xFF000000 /* mask to extract phys address from L1 super entry */
697 #define ARM_TTE_SUPER_L1_SHIFT 24 /* shift for 16MB section phys address */
698
699 #define ARM_TTE_BLOCK_SUPER 0x00040000 /* make section a 16MB section */
700 #define ARM_TTE_BLOCK_SUPER_MASK 0x00F40000 /* make section a 16MB section */
701
702 #define ARM_TTE_BLOCK_NXSHIFT 4
703 #define ARM_TTE_BLOCK_NX 0x00000010 /* section is no execute */
704 #define ARM_TTE_BLOCK_NX_MASK 0x00000010 /* mask for extracting no execute bit */
705 #define ARM_TTE_BLOCK_PNX ARM_TTE_BLOCK_NX
706
707 #define ARM_TTE_BLOCK_TEX0SHIFT 12
708 #define ARM_TTE_BLOCK_TEX0 (1<<ARM_TTE_BLOCK_TEX0SHIFT)
709 #define ARM_TTE_BLOCK_TEX0_MASK (1<<ARM_TTE_BLOCK_TEX0SHIFT)
710
711 #define ARM_TTE_BLOCK_TEX1SHIFT 13
712 #define ARM_TTE_BLOCK_TEX1 (1<<ARM_TTE_BLOCK_TEX1SHIFT)
713 #define ARM_TTE_BLOCK_TEX1_MASK (1<<ARM_TTE_BLOCK_TEX1SHIFT)
714
715 #define ARM_TTE_BLOCK_TEX2SHIFT 14
716 #define ARM_TTE_BLOCK_TEX2 (1<<ARM_TTE_BLOCK_TEX2SHIFT)
717 #define ARM_TTE_BLOCK_TEX2_MASK (1<<ARM_TTE_BLOCK_TEX2SHIFT)
718
719
720 /* mask memory attributes index */
721 #define ARM_TTE_BLOCK_ATTRINDX(i) \
722 ((((i)&0x3)<<ARM_TTE_BLOCK_CBSHIFT) | \
723 ((((i)>>2)&0x1)<<ARM_TTE_BLOCK_TEX0SHIFT))
724
725 /* mask memory attributes index */
726 #define ARM_TTE_BLOCK_ATTRINDXMASK \
727 (ARM_TTE_BLOCK_CB_MASK | ARM_TTE_BLOCK_TEX0_MASK)
728
729
730 /*
731 * Level 2 Page table entries
732 *
733 * The following page table entry types are possible:
734 *
735 * fault page entry
736 * 31 2 0
737 * +----------------------------------------+--+
738 * | ignored |00|
739 * +----------------------------------------+--+
740 *
741 * large (64KB) page entry
742 * 31 16 15 12 9 6 4 3 2 0
743 * +----------------+--+---+-+-+-+---+--+-+-+--+
744 * | base phys addr |XN|TEX|G|S|A|000|AP|C|B|01|
745 * +----------------+--+---+-+-+-+---+--+-+-+--+
746 *
747 * small (4KB) page entry
748 * 31 12 9 6 4 3 2 1 0
749 * +-----------------------+-+-+-+---+--+-+-+-+--+
750 * | base phys addr |G|S|A|TEX|AP|C|B|1|XN|
751 * +-----------------------+-+-+-+---+--+-+-+-+--+
752 *
753 * also where:
754 * 'XN' is the eXecute Never bit
755 * 'G' is the notGlobal (process-specific) bit
756 * 'S' is the shared bit
757 * 'A' in the access permission extension (ATX) bit
758 * 'TEX' remap register control bits
759 * 'AP' is the access protection
760 * 'dom' is the domain for the translation
761 * 'C' is the cache attribute
762 * 'B' is the write buffer attribute
763 */
764
765 /* markers for (invalid) PTE for a page sent to compressor */
766 #define ARM_PTE_COMPRESSED ARM_PTE_TEX1 /* compressed... */
767 #define ARM_PTE_COMPRESSED_ALT ARM_PTE_TEX2 /* ... and was "alt_acct" */
768 #define ARM_PTE_COMPRESSED_MASK (ARM_PTE_COMPRESSED | ARM_PTE_COMPRESSED_ALT)
769 #define ARM_PTE_IS_COMPRESSED(x, p) \
770 ((((x) & 0x3) == 0) && /* PTE is not valid... */ \
771 ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \
772 ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \
773 (panic("compressed PTE %p 0x%x has extra bits 0x%x: corrupted?", \
774 (p), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE)))
775
776 #define PTE_SHIFT 2 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */
777 #define PTE_PGENTRIES (1024 >> PTE_SHIFT) /* number of ptes per page */
778
779 #define ARM_PTE_EMPTY 0x00000000 /* unasigned - invalid entry */
780
781 #define ARM_PTE_TYPE_FAULT 0x00000000 /* fault entry type */
782 #define ARM_PTE_TYPE_VALID 0x00000002 /* valid L2 entry */
783 #define ARM_PTE_TYPE 0x00000002 /* small page entry type */
784 #define ARM_PTE_TYPE_MASK 0x00000002 /* mask to get pte type */
785
786 #define ARM_PTE_NG_MASK 0x00000800 /* mask to determine notGlobal bit */
787 #define ARM_PTE_NG 0x00000800 /* value for a per-process mapping */
788
789 #define ARM_PTE_SHSHIFT 10
790 #define ARM_PTE_SHMASK 0x00000400 /* shared (SMP) mapping mask */
791 #define ARM_PTE_SH 0x00000400 /* shared (SMP) mapping */
792
793 #define ARM_PTE_CBSHIFT 2
794 #define ARM_PTE_CB(x) ((x)<<ARM_PTE_CBSHIFT)
795 #define ARM_PTE_CB_MASK (0x3<<ARM_PTE_CBSHIFT)
796
797 #define ARM_PTE_AP0SHIFT 4
798 #define ARM_PTE_AP0 (1<<ARM_PTE_AP0SHIFT)
799 #define ARM_PTE_AP0_MASK (1<<ARM_PTE_AP0SHIFT)
800
801 #define ARM_PTE_AP1SHIFT 5
802 #define ARM_PTE_AP1 (1<<ARM_PTE_AP1SHIFT)
803 #define ARM_PTE_AP1_MASK (1<<ARM_PTE_AP1SHIFT)
804
805 #define ARM_PTE_AP2SHIFT 9
806 #define ARM_PTE_AP2 (1<<ARM_PTE_AP2SHIFT)
807 #define ARM_PTE_AP2_MASK (1<<ARM_PTE_AP2SHIFT)
808
809 /* access protections */
810 #define ARM_PTE_AP(ap) \
811 ((((ap)&0x1)<<ARM_PTE_AP1SHIFT) | \
812 ((((ap)>>1)&0x1)<<ARM_PTE_AP2SHIFT))
813
814 /* mask access protections */
815 #define ARM_PTE_APMASK \
816 (ARM_PTE_AP1_MASK | ARM_PTE_AP2_MASK)
817
818 #define ARM_PTE_AF ARM_PTE_AP0 /* value for access */
819 #define ARM_PTE_AFMASK ARM_PTE_AP0_MASK /* access mask */
820
821 #define ARM_PTE_PAGE_MASK 0xFFFFF000 /* mask for a small page */
822 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */
823
824 #define ARM_PTE_NXSHIFT 0
825 #define ARM_PTE_NX 0x00000001 /* small page no execute */
826 #define ARM_PTE_NX_MASK (1<<ARM_PTE_NXSHIFT)
827
828 #define ARM_PTE_PNXSHIFT 0
829 #define ARM_PTE_PNX 0x00000000 /* no privilege execute. not impl */
830 #define ARM_PTE_PNX_MASK (0<<ARM_PTE_NXSHIFT)
831
832 #define ARM_PTE_TEX0SHIFT 6
833 #define ARM_PTE_TEX0 (1<<ARM_PTE_TEX0SHIFT)
834 #define ARM_PTE_TEX0_MASK (1<<ARM_PTE_TEX0SHIFT)
835
836 #define ARM_PTE_TEX1SHIFT 7
837 #define ARM_PTE_TEX1 (1<<ARM_PTE_TEX1SHIFT)
838 #define ARM_PTE_TEX1_MASK (1<<ARM_PTE_TEX1SHIFT)
839
840 #define ARM_PTE_WRITEABLESHIFT ARM_PTE_TEX1SHIFT
841 #define ARM_PTE_WRITEABLE ARM_PTE_TEX1
842 #define ARM_PTE_WRITEABLE_MASK ARM_PTE_TEX1_MASK
843
844 #define ARM_PTE_TEX2SHIFT 8
845 #define ARM_PTE_TEX2 (1<<ARM_PTE_TEX2SHIFT)
846 #define ARM_PTE_TEX2_MASK (1<<ARM_PTE_TEX2SHIFT)
847
848 #define ARM_PTE_WIREDSHIFT ARM_PTE_TEX2SHIFT
849 #define ARM_PTE_WIRED ARM_PTE_TEX2
850 #define ARM_PTE_WIRED_MASK ARM_PTE_TEX2_MASK
851
852 /* mask memory attributes index */
853 #define ARM_PTE_ATTRINDX(indx) \
854 ((((indx)&0x3)<<ARM_PTE_CBSHIFT) | \
855 ((((indx)>>2)&0x1)<<ARM_PTE_TEX0SHIFT))
856
857 /* mask memory attributes index */
858 #define ARM_PTE_ATTRINDXMASK \
859 (ARM_PTE_CB_MASK | ARM_PTE_TEX0_MASK)
860
861 #define ARM_SMALL_PAGE_SIZE (4096) /* 4KB */
862 #define ARM_LARGE_PAGE_SIZE (64*1024) /* 64KB */
863 #define ARM_SECTION_SIZE (1024*1024) /* 1MB */
864 #define ARM_SUPERSECTION_SIZE (16*1024*1024) /* 16MB */
865
866 #define TLBI_ADDR_SHIFT (12)
867 #define TLBI_ADDR_SIZE (20)
868 #define TLBI_ADDR_MASK (((1ULL << TLBI_ADDR_SIZE) - 1))
869 #define TLBI_ASID_SHIFT (0)
870 #define TLBI_ASID_SIZE (8)
871 #define TLBI_ASID_MASK (((1ULL << TLBI_ASID_SIZE) - 1))
872 #endif
873
874 /*
875 * Format of the Debug Status and Control Register (DBGDSCR)
876 */
877 #define ARM_DBGDSCR_RXFULL (1 << 30)
878 #define ARM_DBGDSCR_TXFULL (1 << 29)
879 #define ARM_DBGDSCR_RXFULL_1 (1 << 27)
880 #define ARM_DBGDSCR_TXFULL_1 (1 << 26)
881 #define ARM_DBGDSCR_PIPEADV (1 << 25)
882 #define ARM_DBGDSCR_INSTRCOMPL_1 (1 << 24)
883 #define ARM_DBGDSCR_EXTDCCMODE_MASK (3 << 20)
884 #define ARM_DBGDSCR_EXTDCCMODE_NONBLOCKING (0 << 20)
885 #define ARM_DBGDSCR_EXTDCCMODE_STALL (1 << 20)
886 #define ARM_DBGDSCR_EXTDCCMODE_FAST (1 << 20)
887 #define ARM_DBGDSCR_ADADISCARD (1 << 19)
888 #define ARM_DBGDSCR_NS (1 << 18)
889 #define ARM_DBGDSCR_SPNIDDIS (1 << 17)
890 #define ARM_DBGDSCR_SPIDDIS (1 << 16)
891 #define ARM_DBGDSCR_MDBGEN (1 << 15)
892 #define ARM_DBGDSCR_HDBGEN (1 << 14)
893 #define ARM_DBGDSCR_ITREN (1 << 13)
894 #define ARM_DBGDSCR_UDCCDIS (1 << 12)
895 #define ARM_DBGDSCR_INTDIS (1 << 11)
896 #define ARM_DBGDSCR_DBGACK (1 << 10)
897 #define ARM_DBGDSCR_DBGNOPWRDWN (1 << 9)
898 #define ARM_DBGDSCR_UND_1 (1 << 8)
899 #define ARM_DBGDSCR_ADABORT_1 (1 << 7)
900 #define ARM_DBGDSCR_SDABORT_1 (1 << 6)
901 #define ARM_DBGDSCR_MOE_MASK (15 << 2)
902 #define ARM_DBGDSCR_MOE_HALT_REQUEST (0 << 2)
903 #define ARM_DBGDSCR_MOE_BREAKPOINT (1 << 2)
904 #define ARM_DBGDSCR_MOE_ASYNC_WATCHPOINT (2 << 2)
905 #define ARM_DBGDSCR_MOE_BKPT_INSTRUCTION (3 << 2)
906 #define ARM_DBGDSCR_MOE_EXT_DEBUG_REQ (4 << 2)
907 #define ARM_DBGDSCR_MOE_VECTOR_CATCH (5 << 2)
908 #define ARM_DBGDSCR_MOE_DSIDE_ABORT (6 << 2)
909 #define ARM_DBGDSCR_MOE_ISIDE_ABORT (7 << 2)
910 #define ARM_DBGDSCR_MOE_OS_UNLOCK_CATCH (8 << 2)
911 #define ARM_DBGDSCR_MOE_SYNC_WATCHPOINT (10 << 2)
912
913 #define ARM_DBGDSCR_RESTARTED (1 << 1)
914 #define ARM_DBGDSCR_HALTED (1 << 0)
915
916 /*
917 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers
918 * Using ARMv7 names; ARMv6 and ARMv6.1 are bit-compatible
919 */
920 #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */
921 #define ARM_DBGBVR_CONTEXTID_MASK 0xFFFFFFFF /* BVR only */
922
923 #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */
924 #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */
925 #define ARM_DBGBCR_MATCH_MATCH (0 << 22)
926 #define ARM_DBGBCR_MATCH_MISMATCH (1 << 22)
927 #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */
928 #define ARM_DBGBCR_TYPE_IVA (0 << 21)
929 #define ARM_DBGBCR_TYPE_CONTEXTID (1 << 21)
930 #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */
931 #define ARM_DBG_CR_LINKED_LINKED (1 << 20)
932 #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20)
933 #define ARM_DBG_CR_LINKED_BRP_MASK 0x000F0000 /* BCR & WCR */
934 #define ARM_DBG_CR_SECURITY_STATE_MASK (3 << 14) /* BCR & WCR */
935 #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14)
936 #define ARM_DBG_CR_SECURITY_STATE_NONSECURE (1 << 14)
937 #define ARM_DBG_CR_SECURITY_STATE_SECURE (2 << 14)
938 #define ARM_DBG_CR_HIGHER_MODE_MASK (1 << 13) /* BCR & WCR */
939 #define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13)
940 #define ARM_DBG_CR_HIGHER_MODE_DISABLE (0 << 13)
941 #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */
942 #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */
943 #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */
944 #define ARM_DBCWCR_ACCESS_CONTROL_LOAD (1 << 3)
945 #define ARM_DBCWCR_ACCESS_CONTROL_STORE (2 << 3)
946 #define ARM_DBCWCR_ACCESS_CONTROL_ANY (3 << 3)
947 #define ARM_DBG_CR_MODE_CONTROL_MASK (3 << 1) /* BCR & WCR */
948 #define ARM_DBG_CR_MODE_CONTROL_U_S_S (0 << 1) /* BCR only */
949 #define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */
950 #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */
951 #define ARM_DBG_CR_MODE_CONTROL_ANY (3 << 1) /* BCR & WCR */
952 #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */
953 #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0)
954 #define ARM_DBG_CR_ENABLE_DISABLE (0 << 0)
955
956 /*
957 * Format of the Device Power-down and Reset Status Register (DBGPRSR)
958 */
959 #define ARM_DBGPRSR_STICKY_RESET_STATUS (1 << 3)
960 #define ARM_DBGPRSR_RESET_STATUS (1 << 2)
961 #define ARM_DBGPRSR_STICKY_POWERDOWN_STATUS (1 << 1)
962 #define ARM_DBGPRSR_POWERUP_STATUS (1 << 0)
963
964 /*
965 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR)
966 */
967 #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55
968
969 /* ARMv7 Debug register map */
970 #define ARM_DEBUG_OFFSET_DBGDIDR (0x000)
971 #define ARM_DEBUG_OFFSET_DBGWFAR (0x018)
972 #define ARM_DEBUG_OFFSET_DBGVCR (0x01C)
973 #define ARM_DEBUG_OFFSET_DBGECR (0x024)
974 #define ARM_DEBUG_OFFSET_DBGDSCCR (0x028)
975 #define ARM_DEBUG_OFFSET_DBGDSMCR (0x02C)
976 #define ARM_DEBUG_OFFSET_DBGDTRRX (0x080)
977 #define ARM_DEBUG_OFFSET_DBGITR (0x084) /* Write-only */
978 #define ARM_DEBUG_OFFSET_DBGPCSR (0x084) /* Read-only */
979 #define ARM_DEBUG_OFFSET_DBGDSCR (0x088)
980 #define ARM_DEBUG_OFFSET_DBGDTRTX (0x08C)
981 #define ARM_DEBUG_OFFSET_DBGDRCR (0x090)
982 #define ARM_DEBUG_OFFSET_DBGBVR (0x100) /* 0x100 - 0x13C */
983 #define ARM_DEBUG_OFFSET_DBGBCR (0x140) /* 0x140 - 0x17C */
984 #define ARM_DEBUG_OFFSET_DBGWVR (0x180) /* 0x180 - 0x1BC */
985 #define ARM_DEBUG_OFFSET_DBGWCR (0x1C0) /* 0x1C0 - 0x1FC */
986 #define ARM_DEBUG_OFFSET_DBGOSLAR (0x300)
987 #define ARM_DEBUG_OFFSET_DBGOSLSR (0x304)
988 #define ARM_DEBUG_OFFSET_DBGOSSRR (0x308)
989 #define ARM_DEBUG_OFFSET_DBGPRCR (0x310)
990 #define ARM_DEBUG_OFFSET_DBGPRSR (0x314)
991 #define ARM_DEBUG_OFFSET_DBGITCTRL (0xF00)
992 #define ARM_DEBUG_OFFSET_DBGCLAIMSET (0xFA0)
993 #define ARM_DEBUG_OFFSET_DBGCLAIMCLR (0xFA4)
994 #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0)
995 #define ARM_DEBUG_OFFSET_DBGLSR (0xFB4)
996 #define ARM_DEBUG_OFFSET_DBGAUTHSTATUS (0xFB8)
997 #define ARM_DEBUG_OFFSET_DBGDEVID (0xFC8)
998 #define ARM_DEBUG_OFFSET_DBGDEVTYPE (0xFCC)
999 #define ARM_DEBUG_OFFSET_DBGPID0 (0xFD0)
1000 #define ARM_DEBUG_OFFSET_DBGPID1 (0xFD4)
1001 #define ARM_DEBUG_OFFSET_DBGPID2 (0xFD8)
1002 #define ARM_DEBUG_OFFSET_DBGPID3 (0xFDA)
1003 #define ARM_DEBUG_OFFSET_DBGPID4 (0xFDC)
1004 #define ARM_DEBUG_OFFSET_DBGCID0 (0xFF0)
1005 #define ARM_DEBUG_OFFSET_DBGCID1 (0xFF4)
1006 #define ARM_DEBUG_OFFSET_DBGCID2 (0xFF8)
1007 #define ARM_DEBUG_OFFSET_DBGCID3 (0xFFA)
1008 #define ARM_DEBUG_OFFSET_DBGCID4 (0xFFC)
1009
1010 /*
1011 * Media and VFP Feature Register 1 (MVFR1)
1012 */
1013 #define MVFR_ASIMD_HPFP 0x00100000UL
1014
1015 /*
1016 * Main ID Register (MIDR)
1017 *
1018 * 31 24 23 20 19 16 15 4 3 0
1019 * +-----+-----+------+------+-----+
1020 * | IMP | VAR | ARCH | PNUM | REV |
1021 * +-----+-----+------+------+-----+
1022 *
1023 * where:
1024 * IMP: Implementor code
1025 * VAR: Variant number
1026 * ARCH: Architecture code
1027 * PNUM: Primary part number
1028 * REV: Minor revision number
1029 */
1030 #define MIDR_REV_SHIFT 0
1031 #define MIDR_REV_MASK (0xf << MIDR_REV_SHIFT)
1032 #define MIDR_PNUM_SHIFT 4
1033 #define MIDR_PNUM_MASK (0xfff << MIDR_PNUM_SHIFT)
1034 #define MIDR_ARCH_SHIFT 16
1035 #define MIDR_ARCH_MASK (0xf << MIDR_ARCH_SHIFT)
1036 #define MIDR_VAR_SHIFT 20
1037 #define MIDR_VAR_MASK (0xf << MIDR_VAR_SHIFT)
1038 #define MIDR_IMP_SHIFT 24
1039 #define MIDR_IMP_MASK (0xff << MIDR_IMP_SHIFT)
1040
1041 #ifdef __arm__
1042
1043 /* Macros meant to make __builtin_arm_* functions easier to use. */
1044 #define MRC_SCTLR 15,0,1,0,0
1045 #define MCR_SCTLR(x) 15,0,(x),1,0,0
1046
1047 #define MRC_ACTLR 15,0,1,0,1
1048 #define MCR_ACTLR(x) 15,0,(x),1,0,1
1049
1050 #endif /* __arm__ */
1051
1052
1053 #endif /* _ARM_PROC_REG_H_ */
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