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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the
10 * License may not be used to create, or enable the creation or
11 * redistribution of, unlawful or unlicensed copies of an Apple operating
12 * system, or to circumvent, violate, or enable the circumvention or
13 * violation of, any terms of an Apple operating system software license
14 * agreement.
15 *
16 * Please obtain a copy of the License at
17 * http://www.opensource.apple.com/apsl/ and read it before using this
18 * file.
19 *
20 * The Original Code and all software distributed under the License are
21 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
22 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
23 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
25 * Please see the License for the specific language governing rights and
26 * limitations under the License.
27 *
28 * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
29 */
30 #ifndef _PEXPERT_PPC_PROTOS_H_
31 #define _PEXPERT_PPC_PROTOS_H_
32
33 #define mtsprg(n, reg) __asm__ volatile("mtsprg " # n ", %0" : : "r" (reg))
34 #define mfsprg(reg, n) __asm__ volatile("mfsprg %0, " # n : "=r" (reg))
35
36 #define mtspr(spr, val) __asm__ volatile("mtspr " # spr ", %0" : : "r" (val))
37 #define mfspr(reg, spr) __asm__ volatile("mfspr %0, " # spr : "=r" (reg))
38
39 /*
40 * Various memory/IO synchronisation instructions
41 */
42
43 /* Use eieio as a memory barrier to order stores.
44 * Useful for device control and PTE maintenance.
45 */
46
47 #define eieio() \
48 __asm__ volatile("eieio")
49
50 /* Use sync to ensure previous stores have completed.
51 This is required when manipulating locks and/or
52 maintaining PTEs or other shared structures on SMP
53 machines.
54 */
55
56 #define sync() \
57 __asm__ volatile("sync")
58
59 /* Use isync to sychronize context; that is, the ensure
60 no prefetching of instructions happen before the
61 instruction.
62 */
63
64 #define isync() \
65 __asm__ volatile("isync")
66
67
68 //------------------------------------------------------------------------
69 // from ppc/endian.h
70 static __inline__ unsigned int byte_reverse_word(unsigned int word);
71 static __inline__ unsigned int byte_reverse_word(unsigned int word) {
72 unsigned int result;
73 __asm__ volatile("lwbrx %0, 0, %1" : "=r" (result) : "r" (&word));
74 return result;
75 }
76
77 //------------------------------------------------------------------------
78 // from ppc/serial_io.h
79 extern void initialize_serial(void * scc_phys_base, uint32_t serial_baud);
80
81
82 //------------------------------------------------------------------------
83 // from osfmk/ppc/POWERMAC/video_console.c
84
85 extern void initialize_screen(void *, unsigned int);
86
87 extern void vc_progress_initialize( void * desc,
88 const unsigned char * data,
89 const unsigned char * clut );
90
91 extern void vc_display_icon( void * desc,
92 const unsigned char * data );
93
94 //-------------------------------------------------------------------------
95 // from osfmk/console/panic_dialog.c
96 extern void panic_ui_initialize(const unsigned char * clut);
97
98 // from osfmk/ppc/serial_console.c
99 extern int switch_to_serial_console(void);
100 extern void switch_to_old_console(int old_console);
101
102 typedef unsigned spl_t;
103
104 //------------------------------------------------------------------------
105 // from bsd/dev/ppc/busses.h which clashes with mach/device/device_types.h
106 typedef int io_req_t;
107
108
109 //typedef struct ipc_port *ipc_port_t;
110
111 extern void cninit(void);
112
113 /*
114 * Temporarily stolen from Firmware.h
115 */
116
117 extern void dbgTrace(unsigned int item1, unsigned int item2, unsigned int item3);
118 #if 1 /* (TEST/DEBUG) - eliminate inline */
119 extern __inline__ void dbgTrace(unsigned int item1, unsigned int item2, unsigned int item3) {
120
121 __asm__ volatile("mr r3,%0" : : "r" (item1) : "r3");
122 __asm__ volatile("mr r4,%0" : : "r" (item2) : "r4");
123 __asm__ volatile("mr r5,%0" : : "r" (item3) : "r5");
124 __asm__ volatile("lis r0,hi16(CutTrace)" : : : "r0");
125 __asm__ volatile("ori r0,r0,lo16(CutTrace)" : : : "r0");
126 __asm__ volatile("sc");
127 return;
128 }
129 #endif
130
131 extern void DoPreempt(void);
132 extern __inline__ void DoPreempt(void) {
133 __asm__ volatile("lis r0,hi16(DoPreemptCall)" : : : "r0");
134 __asm__ volatile("ori r0,r0,lo16(DoPreemptCall)" : : : "r0");
135 __asm__ volatile("sc");
136 return;
137 }
138
139 extern void CreateFakeIO(void);
140 extern __inline__ void CreateFakeIO(void) {
141 __asm__ volatile("lis r0,hi16(CreateFakeIOCall)" : : : "r0");
142 __asm__ volatile("ori r0,r0,lo16(CreateFakeIOCall)" : : : "r0");
143 __asm__ volatile("sc");
144 return;
145 }
146
147 extern void StoreReal(unsigned int val, unsigned int addr);
148 extern void ReadReal(unsigned int raddr, unsigned int *vaddr);
149 extern unsigned int LLTraceSet(unsigned int tflags);
150 extern void GratefulDebInit(void);
151 extern void GratefulDebDisp(unsigned int coord, unsigned int data);
152 extern void checkNMI(void);
153
154 #endif /* _PEXPERT_PPC_PROTOS_H_ */