osfmk/arm/cpuid.h

   1 /*
   2  * Copyright (c) 2007-2016 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31
  32 /*
  33  * ARM CPU identification
  34  */
  35
  36 #ifndef _MACHINE_CPUID_H_
  37 #define _MACHINE_CPUID_H_
  38
  39 #include <stdint.h>
  40 #include <mach/boolean.h>
  41 #include <machine/machine_cpuid.h>
  42
  43 typedef struct {
  44         uint32_t arm_rev : 4,  /* 00:03 revision number */
  45             arm_part         : 12,/* 04:15 primary part number */
  46             arm_arch         : 4,/* 16:19 architecture */
  47             arm_variant      : 4,/* 20:23 variant  */
  48             arm_implementor  : 8;/* 24:31 implementor (0x41) */
  49 } arm_cpuid_bits_t;
  50
  51 typedef union {
  52         arm_cpuid_bits_t arm_info; /* ARM9xx,  ARM11xx, and later processors */
  53         uint32_t         value;
  54 } arm_cpu_info_t;
  55
  56 /* Implementor codes */
  57 #define CPU_VID_ARM      0x41 // ARM Limited
  58 #define CPU_VID_DEC      0x44 // Digital Equipment Corporation
  59 #define CPU_VID_MOTOROLA 0x4D // Motorola - Freescale Semiconductor Inc.
  60 #define CPU_VID_MARVELL  0x56 // Marvell Semiconductor Inc.
  61 #define CPU_VID_INTEL    0x69 // Intel ARM parts.
  62 #define CPU_VID_APPLE    0x61 // Apple Inc.
  63
  64
  65 /* ARM Architecture Codes */
  66
  67 #define CPU_ARCH_ARMv4    0x1 /* ARMv4 */
  68 #define CPU_ARCH_ARMv4T   0x2 /* ARMv4 + Thumb */
  69 #define CPU_ARCH_ARMv5    0x3 /* ARMv5 */
  70 #define CPU_ARCH_ARMv5T   0x4 /* ARMv5 + Thumb */
  71 #define CPU_ARCH_ARMv5TE  0x5 /* ARMv5 + Thumb + Extensions(?) */
  72 #define CPU_ARCH_ARMv5TEJ 0x6 /* ARMv5 + Thumb + Extensions(?) + //Jazelle(?) XXX */
  73 #define CPU_ARCH_ARMv6    0x7 /* ARMv6 */
  74 #define CPU_ARCH_ARMv7    0x8 /* ARMv7 */
  75 #define CPU_ARCH_ARMv7f   0x9 /* ARMv7 for Cortex A9 */
  76 #define CPU_ARCH_ARMv7s   0xa /* ARMv7 for Swift */
  77 #define CPU_ARCH_ARMv7k   0xb /* ARMv7 for Cortex A7 */
  78
  79 #define CPU_ARCH_ARMv8    0xc /* Subtype for CPU_TYPE_ARM64 */
  80
  81 #define CPU_ARCH_ARMv8E   0xd /* ARMv8.3a + Apple Private ISA Subtype for CPU_TYPE_ARM64 */
  82
  83 /* special code indicating we need to look somewhere else for the architecture version */
  84 #define CPU_ARCH_EXTENDED 0xF
  85
  86 /* ARM Part Numbers */
  87 /*
  88  * XXX: ARM Todo
  89  * Fill out these part numbers more completely
  90  */
  91
  92 /* ARM9 (ARMv4T architecture) */
  93 #define CPU_PART_920T               0x920
  94 #define CPU_PART_926EJS             0x926 /* ARM926EJ-S */
  95
  96 /* ARM11  (ARMv6 architecture) */
  97 #define CPU_PART_1136JFS            0xB36 /* ARM1136JF-S or ARM1136J-S */
  98 #define CPU_PART_1176JZFS           0xB76 /* ARM1176JZF-S */
  99
 100 /* G1 (ARMv7 architecture) */
 101 #define CPU_PART_CORTEXA5           0xC05
 102
 103 /* M7 (ARMv7 architecture) */
 104 #define CPU_PART_CORTEXA7           0xC07
 105
 106 /* H2 H3 (ARMv7 architecture) */
 107 #define CPU_PART_CORTEXA8           0xC08
 108
 109 /* H4 (ARMv7 architecture) */
 110 #define CPU_PART_CORTEXA9           0xC09
 111
 112 /* H7 (ARMv8 architecture) */
 113 #define CPU_PART_TYPHOON            0x2
 114
 115 /* H7G (ARMv8 architecture) */
 116 #define CPU_PART_TYPHOON_CAPRI      0x3
 117
 118 /* H8 (ARMv8 architecture) */
 119 #define CPU_PART_TWISTER            0x4
 120
 121 /* H8G H8M (ARMv8 architecture) */
 122 #define CPU_PART_TWISTER_ELBA_MALTA 0x5
 123
 124 /* H9 (ARMv8 architecture) */
 125 #define CPU_PART_HURRICANE          0x6
 126
 127 /* H9G (ARMv8 architecture) */
 128 #define CPU_PART_HURRICANE_MYST     0x7
 129
 130 /* H10 p-Core (ARMv8 architecture) */
 131 #define CPU_PART_MONSOON            0x8
 132
 133 /* H10 e-Core (ARMv8 architecture) */
 134 #define CPU_PART_MISTRAL            0x9
 135
 136 /* H11 p-Core (ARMv8 architecture) */
 137 #define CPU_PART_VORTEX             0xB
 138
 139 /* H11 e-Core (ARMv8 architecture) */
 140 #define CPU_PART_TEMPEST            0xC
 141
 142 /* M9 e-Core (ARMv8 architecture) */
 143 #define CPU_PART_TEMPEST_M9         0xF
 144
 145 /* H11G p-Core (ARMv8 architecture) */
 146 #define CPU_PART_VORTEX_ARUBA       0x10
 147
 148 /* H11G e-Core (ARMv8 architecture) */
 149 #define CPU_PART_TEMPEST_ARUBA      0x11
 150
 151 /* H12 p-Core (ARMv8 architecture) */
 152 #define CPU_PART_LIGHTNING          0x12
 153
 154 /* H12 e-Core (ARMv8 architecture) */
 155 #define CPU_PART_THUNDER            0x13
 156
 157
 158
 159
 160
 161 /* Cache type identification */
 162
 163 /* Supported Cache Types */
 164 typedef enum {
 165         CACHE_WRITE_THROUGH,
 166         CACHE_WRITE_BACK,
 167         CACHE_READ_ALLOCATION,
 168         CACHE_WRITE_ALLOCATION,
 169         CACHE_UNKNOWN
 170 } cache_type_t;
 171
 172 typedef struct {
 173         boolean_t    c_unified;          /* unified I & D cache? */
 174         uint32_t     c_isize;            /* in Bytes (ARM caches can be 0.5 KB) */
 175         boolean_t    c_i_ppage;          /* protected page restriction for I cache
 176                                           * (see B6-11 in ARM DDI 0100I document). */
 177         uint32_t     c_dsize;            /* in Bytes (ARM caches can be 0.5 KB) */
 178         boolean_t    c_d_ppage;          /* protected page restriction for I cache
 179                                           * (see B6-11 in ARM DDI 0100I document). */
 180         cache_type_t c_type;             /* WB or WT */
 181         uint32_t     c_linesz;           /* number of bytes */
 182         uint32_t     c_assoc;            /* n-way associativity */
 183         uint32_t     c_l2size;           /* L2 size, if present */
 184         uint32_t     c_bulksize_op;      /* bulk operation size limit. 0 if disabled */
 185         uint32_t     c_inner_cache_size; /* inner dache size */
 186 } cache_info_t;
 187
 188 typedef struct {
 189         uint32_t
 190             RB:4, /* 3:0 - 32x64-bit media register bank supported: 0x2 */
 191             SP:4, /* 7:4 - Single precision supported in VFPv3: 0x2 */
 192             DP:4, /* 8:11 - Double precision supported in VFPv3: 0x2 */
 193             TE:4, /* 12-15 - Only untrapped exception handling can be selected: 0x0 */
 194             D:4, /* 19:16 - VFP hardware divide supported: 0x1 */
 195             SR:4, /* 23:20 - VFP hardware square root supported: 0x1 */
 196             SV:4, /* 27:24 - VFP short vector supported: 0x1 */
 197             RM:4; /* 31:28 - All VFP rounding modes supported: 0x1 */
 198 } arm_mvfr0_t;
 199
 200 typedef union {
 201         arm_mvfr0_t bits;
 202         uint32_t    value;
 203 } arm_mvfr0_info_t;
 204
 205 typedef struct {
 206         uint32_t
 207             FZ:4, /* 3:0 - Full denormal arithmetic supported for VFP: 0x1 */
 208             DN:4, /* 7:4 - Propagation of NaN values supported for VFP: 0x1 */
 209             LS:4, /* 11:8 - Load/store instructions supported for NEON: 0x1 */
 210             I:4, /* 15:12 - Integer instructions supported for NEON: 0x1 */
 211             SP:4, /* 19:16 - Single precision floating-point instructions supported for NEON: 0x1 */
 212             HPFP:4, /* 23:20 - Half precision floating-point instructions supported */
 213             RSVP:8; /* 31:24 - Reserved */
 214 } arm_mvfr1_t;
 215
 216 typedef union {
 217         arm_mvfr1_t bits;
 218         uint32_t    value;
 219 } arm_mvfr1_info_t;
 220
 221 typedef struct {
 222         uint32_t neon;
 223         uint32_t neon_hpfp;
 224         uint32_t neon_fp16;
 225 } arm_mvfp_info_t;
 226
 227 #ifdef __cplusplus
 228 extern "C" {
 229 #endif /* __cplusplus */
 230
 231 extern void do_cpuid(void);
 232 extern arm_cpu_info_t *cpuid_info(void);
 233 extern int cpuid_get_cpufamily(void);
 234 extern int cpuid_get_cpusubfamily(void);
 235
 236 extern void do_debugid(void);
 237 extern arm_debug_info_t *arm_debug_info(void);
 238
 239 extern void do_cacheid(void);
 240 extern cache_info_t *cache_info(void);
 241
 242 extern void do_mvfpid(void);
 243 extern arm_mvfp_info_t *arm_mvfp_info(void);
 244
 245 #ifdef __cplusplus
 246 }
 247 #endif /* __cplusplus */
 248
 249 #endif // _MACHINE_CPUID_H_