]> git.saurik.com Git - apple/xnu.git/blob - osfmk/i386/cpuid.c
projects / apple / xnu.git / blob
? search:


adcfa5608ad920fde3643c05b673bdd72b0bf440
[apple/xnu.git] / osfmk / i386 / cpuid.c
1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the
10 * License may not be used to create, or enable the creation or
11 * redistribution of, unlawful or unlicensed copies of an Apple operating
12 * system, or to circumvent, violate, or enable the circumvention or
13 * violation of, any terms of an Apple operating system software license
14 * agreement.
15 *
16 * Please obtain a copy of the License at
17 * http://www.opensource.apple.com/apsl/ and read it before using this
18 * file.
19 *
20 * The Original Code and all software distributed under the License are
21 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
22 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
23 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
25 * Please see the License for the specific language governing rights and
26 * limitations under the License.
27 *
28 * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
29 */
30 /*
31 * @OSF_COPYRIGHT@
32 */
33 #include <platforms.h>
34 #include <mach_kdb.h>
35 #include <pexpert/pexpert.h>
36
37 #include "cpuid.h"
38 #if MACH_KDB
39 #include <i386/db_machdep.h>
40 #include <ddb/db_aout.h>
41 #include <ddb/db_access.h>
42 #include <ddb/db_sym.h>
43 #include <ddb/db_variables.h>
44 #include <ddb/db_command.h>
45 #include <ddb/db_output.h>
46 #include <ddb/db_expr.h>
47 #endif
48
49 #define min(a,b) ((a) < (b) ? (a) : (b))
50 #define quad(hi,lo) (((uint64_t)(hi)) << 32 | (lo))
51
52 #define bit(n) (1UL << (n))
53 #define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
54 #define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l)
55
56 /*
57 * CPU identification routines.
58 *
59 * Note that this code assumes a processor that supports the
60 * 'cpuid' instruction.
61 */
62
63 static unsigned int cpuid_maxcpuid;
64
65 static i386_cpu_info_t cpuid_cpu_info;
66
67 uint32_t cpuid_feature; /* XXX obsolescent for compat */
68
69 /*
70 * We only identify Intel CPUs here. Adding support
71 * for others would be straightforward.
72 */
73 static void set_cpu_generic(i386_cpu_info_t *);
74 static void set_cpu_intel(i386_cpu_info_t *);
75 static void set_cpu_amd(i386_cpu_info_t *);
76 static void set_cpu_nsc(i386_cpu_info_t *);
77 static void set_cpu_unknown(i386_cpu_info_t *);
78
79 struct {
80 const char *vendor;
81 void (* func)(i386_cpu_info_t *);
82 } cpu_vendors[] = {
83 {CPUID_VID_INTEL, set_cpu_intel},
84 {CPUID_VID_AMD, set_cpu_amd},
85 {CPUID_VID_NSC, set_cpu_nsc},
86 {0, set_cpu_unknown}
87 };
88
89 void
90 cpuid_get_info(i386_cpu_info_t *info_p)
91 {
92 uint32_t cpuid_result[4];
93 int i;
94
95 bzero((void *)info_p, sizeof(i386_cpu_info_t));
96
97 /* do cpuid 0 to get vendor */
98 do_cpuid(0, cpuid_result);
99 cpuid_maxcpuid = cpuid_result[eax];
100 bcopy((char *)&cpuid_result[ebx], &info_p->cpuid_vendor[0], 4); /* ug */
101 bcopy((char *)&cpuid_result[ecx], &info_p->cpuid_vendor[8], 4);
102 bcopy((char *)&cpuid_result[edx], &info_p->cpuid_vendor[4], 4);
103 info_p->cpuid_vendor[12] = 0;
104
105 /* look up vendor */
106 for (i = 0; ; i++) {
107 if ((cpu_vendors[i].vendor == 0) ||
108 (!strcmp(cpu_vendors[i].vendor, info_p->cpuid_vendor))) {
109 cpu_vendors[i].func(info_p);
110 break;
111 }
112 }
113 }
114
115 /*
116 * Cache descriptor table. Each row has the form:
117 * (descriptor_value, cache, size, linesize,
118 * description)
119 * Note: the CACHE_DESC macro does not expand description text in the kernel.
120 */
121 static cpuid_cache_desc_t cpuid_cache_desc_tab[] = {
122 CACHE_DESC(CPUID_CACHE_ITLB_4K, Lnone, 0, 0, \
123 "Instruction TLB, 4K, pages 4-way set associative, 64 entries"),
124 CACHE_DESC(CPUID_CACHE_ITLB_4M, Lnone, 0, 0, \
125 "Instruction TLB, 4M, pages 4-way set associative, 2 entries"),
126 CACHE_DESC(CPUID_CACHE_DTLB_4K, Lnone, 0, 0, \
127 "Data TLB, 4K pages, 4-way set associative, 64 entries"),
128 CACHE_DESC(CPUID_CACHE_DTLB_4M, Lnone, 0, 0, \
129 "Data TLB, 4M pages, 4-way set associative, 8 entries"),
130 CACHE_DESC(CPUID_CACHE_ITLB_64, Lnone, 0, 0, \
131 "Instruction TLB, 4K and 2M or 4M pages, 64 entries"),
132 CACHE_DESC(CPUID_CACHE_ITLB_128, Lnone, 0, 0, \
133 "Instruction TLB, 4K and 2M or 4M pages, 128 entries"),
134 CACHE_DESC(CPUID_CACHE_ITLB_256, Lnone, 0, 0, \
135 "Instruction TLB, 4K and 2M or 4M pages, 256 entries"),
136 CACHE_DESC(CPUID_CACHE_DTLB_64, Lnone, 0, 0, \
137 "Data TLB, 4K and 4M pages, 64 entries"),
138 CACHE_DESC(CPUID_CACHE_DTLB_128, Lnone, 0, 0, \
139 "Data TLB, 4K and 4M pages, 128 entries"),
140 CACHE_DESC(CPUID_CACHE_DTLB_256, Lnone, 0, 0, \
141 "Data TLB, 4K and 4M pages, 256 entries"),
142 CACHE_DESC(CPUID_CACHE_ITLB_128_4, Lnone, 0, 0, \
143 "Instruction TLB, 4K pages, 4-way set associative, 128 entries"),
144 CACHE_DESC(CPUID_CACHE_DTLB_128_4, Lnone, 0, 0, \
145 "Data TLB, 4K pages, 4-way set associative, 128 entries"),
146 CACHE_DESC(CPUID_CACHE_ICACHE_8K, L1I, 8*1024, 32, \
147 "Instruction L1 cache, 8K, 4-way set associative, 32byte line size"),
148 CACHE_DESC(CPUID_CACHE_DCACHE_8K, L1D, 8*1024, 32, \
149 "Data L1 cache, 8K, 2-way set associative, 32byte line size"),
150 CACHE_DESC(CPUID_CACHE_ICACHE_16K, L1I, 16*1024, 32, \
151 "Instruction L1 cache, 16K, 4-way set associative, 32byte line size"),
152 CACHE_DESC(CPUID_CACHE_DCACHE_16K, L1D, 16*1024, 32, \
153 "Data L1 cache, 16K, 4-way set associative, 32byte line size"),
154 CACHE_DESC(CPUID_CACHE_DCACHE_8K_64, L1D, 8*1024, 64, \
155 "Data L1 cache, 8K, 4-way set associative, 64byte line size"),
156 CACHE_DESC(CPUID_CACHE_DCACHE_16K_64, L1D, 16*1024, 64, \
157 "Data L1 cache, 16K, 4-way set associative, 64byte line size"),
158 CACHE_DESC(CPUID_CACHE_DCACHE_32K_64, L1D, 32*1024, 64, \
159 "Data L1 cache, 32K, 4-way set associative, 64byte line size"),
160 CACHE_DESC(CPUID_CACHE_DCACHE_32K, L1D, 32*1024, 64, \
161 "Data L1 cache, 32K, 8-way set assocative, 64byte line size"),
162 CACHE_DESC(CPUID_CACHE_ICACHE_32K, L1I, 32*1024, 64, \
163 "Instruction L1 cache, 32K, 8-way set associative, 64byte line size"),
164 CACHE_DESC(CPUID_CACHE_DCACHE_16K_8, L1D, 16*1024, 64, \
165 "Data L1 cache, 16K, 8-way set associative, 64byte line size"),
166 CACHE_DESC(CPUID_CACHE_TRACE_12K, L1I, 12*1024, 64, \
167 "Trace cache, 12K-uop, 8-way set associative"),
168 CACHE_DESC(CPUID_CACHE_TRACE_16K, L1I, 16*1024, 64, \
169 "Trace cache, 16K-uop, 8-way set associative"),
170 CACHE_DESC(CPUID_CACHE_TRACE_32K, L1I, 32*1024, 64, \
171 "Trace cache, 32K-uop, 8-way set associative"),
172 CACHE_DESC(CPUID_CACHE_UCACHE_128K, L2U, 128*1024, 32, \
173 "Unified L2 cache, 128K, 4-way set associative, 32byte line size"),
174 CACHE_DESC(CPUID_CACHE_UCACHE_256K, L2U, 128*1024, 32, \
175 "Unified L2 cache, 256K, 4-way set associative, 32byte line size"),
176 CACHE_DESC(CPUID_CACHE_UCACHE_512K, L2U, 512*1024, 32, \
177 "Unified L2 cache, 512K, 4-way set associative, 32byte line size"),
178 CACHE_DESC(CPUID_CACHE_UCACHE_1M, L2U, 1*1024*1024, 32, \
179 "Unified L2 cache, 1M, 4-way set associative, 32byte line size"),
180 CACHE_DESC(CPUID_CACHE_UCACHE_2M, L2U, 2*1024*1024, 32, \
181 "Unified L2 cache, 2M, 4-way set associative, 32byte line size"),
182 CACHE_DESC(CPUID_CACHE_UCACHE_4M, L2U, 4*1024*1024, 64, \
183 "Unified L2 cache, 4M, 16-way set associative, 64byte line size"),
184 CACHE_DESC(CPUID_CACHE_UCACHE_128K_64, L2U, 128*1024, 64, \
185 "Unified L2 cache, 128K, 8-way set associative, 64byte line size"),
186 CACHE_DESC(CPUID_CACHE_UCACHE_256K_64, L2U, 256*1024, 64, \
187 "Unified L2 cache, 256K, 8-way set associative, 64byte line size"),
188 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64, L2U, 512*1024, 64, \
189 "Unified L2 cache, 512K, 8-way set associative, 64byte line size"),
190 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64, L2U, 1*1024*1024, 64, \
191 "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
192 CACHE_DESC(CPUID_CACHE_UCACHE_256K_32, L2U, 256*1024, 32, \
193 "Unified L2 cache, 256K, 8-way set associative, 32byte line size"),
194 CACHE_DESC(CPUID_CACHE_UCACHE_512K_32, L2U, 512*1024, 32, \
195 "Unified L2 cache, 512K, 8-way set associative, 32byte line size"),
196 CACHE_DESC(CPUID_CACHE_UCACHE_1M_32, L2U, 1*1024*1024, 32, \
197 "Unified L2 cache, 1M, 8-way set associative, 32byte line size"),
198 CACHE_DESC(CPUID_CACHE_UCACHE_2M_32, L2U, 2*1024*1024, 32, \
199 "Unified L2 cache, 2M, 8-way set associative, 32byte line size"),
200 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_4, L2U, 1*1024*1024, 64, \
201 "Unified L2 cache, 1M, 4-way set associative, 64byte line size"),
202 CACHE_DESC(CPUID_CACHE_UCACHE_2M_64, L2U, 2*1024*1024, 64, \
203 "Unified L2 cache, 2M, 8-way set associative, 64byte line size"),
204 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_2,L2U, 512*1024, 64, \
205 "Unified L2 cache, 512K, 2-way set associative, 64byte line size"),
206 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_4,L2U, 512*1024, 64, \
207 "Unified L2 cache, 512K, 4-way set associative, 64byte line size"),
208 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_8, L2U, 1*1024*1024, 64, \
209 "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
210 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S4, L2U, 128*1024, 64, \
211 "Unified L2 sectored cache, 128K, 4-way set associative, 64byte line size"),
212 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S2, L2U, 128*1024, 64, \
213 "Unified L2 sectored cache, 128K, 2-way set associative, 64byte line size"),
214 CACHE_DESC(CPUID_CACHE_UCACHE_256K_S4, L2U, 256*1024, 64, \
215 "Unified L2 sectored cache, 256K, 4-way set associative, 64byte line size"),
216 CACHE_DESC(CPUID_CACHE_L3CACHE_512K, L3U, 512*1024, 64, \
217 "Unified L3 cache, 512K, 4-way set associative, 64byte line size"),
218 CACHE_DESC(CPUID_CACHE_L3CACHE_1M, L3U, 1*1024*1024, 64, \
219 "Unified L3 cache, 1M, 8-way set associative, 64byte line size"),
220 CACHE_DESC(CPUID_CACHE_L3CACHE_2M, L3U, 2*1024*1024, 64, \
221 "Unified L3 cache, 2M, 8-way set associative, 64byte line size"),
222 CACHE_DESC(CPUID_CACHE_L3CACHE_4M, L3U, 4*1024*1024, 64, \
223 "Unified L3 cache, 4M, 8-way set associative, 64byte line size"),
224 CACHE_DESC(CPUID_CACHE_PREFETCH_64, Lnone, 0, 0, \
225 "64-Byte Prefetching"),
226 CACHE_DESC(CPUID_CACHE_PREFETCH_128, Lnone, 0, 0, \
227 "128-Byte Prefetching"),
228 CACHE_DESC(CPUID_CACHE_NOCACHE, Lnone, 0, 0, \
229 "No L2 cache or, if valid L2 cache, no L3 cache"),
230 CACHE_DESC(CPUID_CACHE_NULL, Lnone, 0, 0, \
231 (char *)0),
232 };
233
234 static const char * get_intel_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype)
235 {
236 *type = CPU_TYPE_X86;
237 *subtype = CPU_SUBTYPE_X86_ARCH1;
238
239 /* check for brand id string */
240 switch(info_p->cpuid_brand) {
241 case CPUID_BRAND_UNSUPPORTED:
242 /* brand ID not supported; use alternate method. */
243 switch(info_p->cpuid_family) {
244 case CPUID_FAMILY_486:
245 return "Intel 486";
246 case CPUID_FAMILY_586:
247 return "Intel Pentium";
248 case CPUID_FAMILY_686:
249 switch(info_p->cpuid_model) {
250 case CPUID_MODEL_P6:
251 return "Intel Pentium Pro";
252 case CPUID_MODEL_PII:
253 return "Intel Pentium II";
254 case CPUID_MODEL_P65:
255 case CPUID_MODEL_P66:
256 return "Intel Celeron";
257 case CPUID_MODEL_P67:
258 case CPUID_MODEL_P68:
259 case CPUID_MODEL_P6A:
260 case CPUID_MODEL_P6B:
261 return "Intel Pentium III";
262 case CPUID_MODEL_PM9:
263 case CPUID_MODEL_PMD:
264 return "Intel Pentium M";
265 default:
266 return "Unknown Intel P6 Family";
267 }
268 case CPUID_FAMILY_EXTENDED:
269 switch (info_p->cpuid_extfamily) {
270 case CPUID_EXTFAMILY_PENTIUM4:
271 *subtype = CPU_SUBTYPE_PENTIUM_4;
272 return "Intel Pentium 4";
273 default:
274 return "Unknown Intel Extended Family";
275 }
276 default:
277 return "Unknown Intel Family";
278 }
279 break;
280 case CPUID_BRAND_CELERON_1:
281 case CPUID_BRAND_CELERON_A:
282 case CPUID_BRAND_CELERON_14:
283 return "Intel Celeron";
284 case CPUID_BRAND_PENTIUM_III_2:
285 case CPUID_BRAND_PENTIUM_III_4:
286 return "Pentium III";
287 case CPUID_BRAND_PIII_XEON:
288 if (info_p->cpuid_signature == 0x6B1) {
289 return "Intel Celeron";
290 } else {
291 return "Intel Pentium III Xeon";
292 }
293 case CPUID_BRAND_PENTIUM_III_M:
294 return "Mobile Intel Pentium III-M";
295 case CPUID_BRAND_M_CELERON_7:
296 case CPUID_BRAND_M_CELERON_F:
297 case CPUID_BRAND_M_CELERON_13:
298 case CPUID_BRAND_M_CELERON_17:
299 return "Mobile Intel Celeron";
300 case CPUID_BRAND_PENTIUM4_8:
301 case CPUID_BRAND_PENTIUM4_9:
302 *subtype = CPU_SUBTYPE_PENTIUM_4;
303 return "Intel Pentium 4";
304 case CPUID_BRAND_XEON:
305 return "Intel Xeon";
306 case CPUID_BRAND_XEON_MP:
307 return "Intel Xeon MP";
308 case CPUID_BRAND_PENTIUM4_M:
309 if (info_p->cpuid_signature == 0xF13) {
310 return "Intel Xeon";
311 } else {
312 *subtype = CPU_SUBTYPE_PENTIUM_4;
313 return "Mobile Intel Pentium 4";
314 }
315 case CPUID_BRAND_CELERON_M:
316 return "Intel Celeron M";
317 case CPUID_BRAND_PENTIUM_M:
318 return "Intel Pentium M";
319 case CPUID_BRAND_MOBILE_15:
320 case CPUID_BRAND_MOBILE_17:
321 return "Mobile Intel";
322 }
323 return "Unknown Intel";
324 }
325
326 static void set_intel_cache_info( i386_cpu_info_t * info_p )
327 {
328 uint32_t cpuid_result[4];
329 uint32_t l1d_cache_linesize = 0;
330 unsigned int i;
331 unsigned int j;
332
333 /* get processor cache descriptor info */
334 do_cpuid(2, cpuid_result);
335 for (j = 0; j < 4; j++) {
336 if ((cpuid_result[j] >> 31) == 1) /* bit31 is validity */
337 continue;
338 ((uint32_t *) info_p->cache_info)[j] = cpuid_result[j];
339 }
340 /* first byte gives number of cpuid calls to get all descriptors */
341 for (i = 1; i < info_p->cache_info[0]; i++) {
342 if (i*16 > sizeof(info_p->cache_info))
343 break;
344 do_cpuid(2, cpuid_result);
345 for (j = 0; j < 4; j++) {
346 if ((cpuid_result[j] >> 31) == 1)
347 continue;
348 ((uint32_t *) info_p->cache_info)[4*i+j] =
349 cpuid_result[j];
350 }
351 }
352
353 /* decode the descriptors looking for L1/L2/L3 size info */
354 for (i = 1; i < sizeof(info_p->cache_info); i++) {
355 cpuid_cache_desc_t *descp;
356 uint8_t desc = info_p->cache_info[i];
357
358 if (desc == CPUID_CACHE_NULL)
359 continue;
360 for (descp = cpuid_cache_desc_tab;
361 descp->value != CPUID_CACHE_NULL; descp++) {
362 if (descp->value != desc)
363 continue;
364 info_p->cache_size[descp->type] = descp->size;
365 if (descp->type == L2U)
366 info_p->cache_linesize = descp->linesize;
367 if (descp->type == L1D)
368 l1d_cache_linesize = descp->linesize;
369 break;
370 }
371 }
372 /* For P-IIIs, L2 could be 256k or 512k but we can't tell */
373 if (info_p->cache_size[L2U] == 0 &&
374 info_p->cpuid_family == 0x6 && info_p->cpuid_model == 0xb) {
375 info_p->cache_size[L2U] = 256*1024;
376 info_p->cache_linesize = 32;
377 }
378 /* If we have no L2 cache, use the L1 data cache line size */
379 if (info_p->cache_size[L2U] == 0)
380 info_p->cache_linesize = l1d_cache_linesize;
381
382 /*
383 * Get cache sharing info if available.
384 */
385 do_cpuid(0, cpuid_result);
386 if (cpuid_result[eax] >= 4) {
387 uint32_t reg[4];
388 uint32_t index;
389 for (index = 0;; index++) {
390 /*
391 * Scan making calls for cpuid with %eax = 4
392 * to get info about successive cache levels
393 * until a null type is returned.
394 */
395 cache_type_t type = Lnone;
396 uint32_t cache_type;
397 uint32_t cache_level;
398 uint32_t cache_sharing;
399
400 reg[eax] = 4; /* cpuid request 4 */
401 reg[ecx] = index; /* index starting at 0 */
402 cpuid(reg);
403 //kprintf("cpuid(4) index=%d eax=%p\n", index, reg[eax]);
404 cache_type = bitfield(reg[eax], 4, 0);
405 if (cache_type == 0)
406 break; /* done with cache info */
407 cache_level = bitfield(reg[eax], 7, 5);
408 cache_sharing = bitfield(reg[eax], 25, 14);
409 info_p->cpuid_cores_per_package =
410 bitfield(reg[eax], 31, 26) + 1;
411 switch (cache_level) {
412 case 1:
413 type = cache_type == 1 ? L1D :
414 cache_type == 2 ? L1I :
415 Lnone;
416 break;
417 case 2:
418 type = cache_type == 3 ? L2U :
419 Lnone;
420 break;
421 case 3:
422 type = cache_type == 3 ? L3U :
423 Lnone;
424 }
425 if (type != Lnone)
426 info_p->cache_sharing[type] = cache_sharing + 1;
427 }
428 }
429 }
430
431 static void set_cpu_intel( i386_cpu_info_t * info_p )
432 {
433 set_cpu_generic(info_p);
434 set_intel_cache_info(info_p);
435 info_p->cpuid_model_string = get_intel_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype);
436 }
437
438 static const char * get_amd_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype )
439 {
440 *type = CPU_TYPE_X86;
441 *subtype = CPU_SUBTYPE_X86_ARCH1;
442
443 /* check for brand id string */
444 switch (info_p->cpuid_family)
445 {
446 case CPUID_FAMILY_486:
447 switch (info_p->cpuid_model) {
448 case CPUID_MODEL_AM486_DX:
449 case CPUID_MODEL_AM486_DX2:
450 case CPUID_MODEL_AM486_DX2WB:
451 case CPUID_MODEL_AM486_DX4:
452 case CPUID_MODEL_AM486_DX4WB:
453 return "Am486";
454 case CPUID_MODEL_AM486_5X86:
455 case CPUID_MODEL_AM486_5X86WB:
456 return "Am5x86";
457 }
458 break;
459 case CPUID_FAMILY_586:
460 switch (info_p->cpuid_model) {
461 case CPUID_MODEL_K5M0:
462 case CPUID_MODEL_K5M1:
463 case CPUID_MODEL_K5M2:
464 case CPUID_MODEL_K5M3:
465 return "AMD-K5";
466 case CPUID_MODEL_K6M6:
467 case CPUID_MODEL_K6M7:
468 return "AMD-K6";
469 case CPUID_MODEL_K6_2:
470 return "AMD-K6-2";
471 case CPUID_MODEL_K6_III:
472 return "AMD-K6-III";
473 }
474 break;
475 case CPUID_FAMILY_686:
476 switch (info_p->cpuid_model) {
477 case CPUID_MODEL_ATHLON_M1:
478 case CPUID_MODEL_ATHLON_M2:
479 case CPUID_MODEL_ATHLON_M4:
480 case CPUID_MODEL_ATHLON_M6:
481 case CPUID_MODEL_ATHLON_M8:
482 case CPUID_MODEL_ATHLON_M10:
483 return "AMD Athlon";
484 case CPUID_MODEL_DURON_M3:
485 case CPUID_MODEL_DURON_M7:
486 return "AMD Duron";
487 default:
488 return "Unknown AMD Athlon";
489 }
490 case CPUID_FAMILY_EXTENDED:
491 switch (info_p->cpuid_model) {
492 case CPUID_MODEL_ATHLON64:
493 return "AMD Athlon 64";
494 case CPUID_MODEL_OPTERON:
495 return "AMD Opteron";
496 default:
497 return "Unknown AMD-64";
498 }
499 }
500 return "Unknown AMD";
501 }
502
503 static void set_amd_cache_info( i386_cpu_info_t * info_p )
504 {
505 uint32_t cpuid_result[4];
506
507 /* It would make sense to fill in info_p->cache_info with complete information
508 * on the TLBs and data cache associativity, lines, etc, either by mapping
509 * to the Intel tags (if possible), or replacing cache_info with a generic
510 * mechanism. But right now, nothing makes use of that information (that I know
511 * of).
512 */
513
514 /* L1 Cache and TLB Information */
515 do_cpuid(0x80000005, cpuid_result);
516
517 /* EAX: TLB Information for 2-Mbyte and 4-MByte Pages */
518 /* (ignore) */
519
520 /* EBX: TLB Information for 4-Kbyte Pages */
521 /* (ignore) */
522
523 /* ECX: L1 Data Cache Information */
524 info_p->cache_size[L1D] = ((cpuid_result[ecx] >> 24) & 0xFF) * 1024;
525 info_p->cache_linesize = (cpuid_result[ecx] & 0xFF);
526
527 /* EDX: L1 Instruction Cache Information */
528 info_p->cache_size[L1I] = ((cpuid_result[edx] >> 24) & 0xFF) * 1024;
529
530 /* L2 Cache Information */
531 do_cpuid(0x80000006, cpuid_result);
532
533 /* EAX: L2 TLB Information for 2-Mbyte and 4-Mbyte Pages */
534 /* (ignore) */
535
536 /* EBX: L2 TLB Information for 4-Kbyte Pages */
537 /* (ignore) */
538
539 /* ECX: L2 Cache Information */
540 info_p->cache_size[L2U] = ((cpuid_result[ecx] >> 16) & 0xFFFF) * 1024;
541 if (info_p->cache_size[L2U] > 0)
542 info_p->cache_linesize = cpuid_result[ecx] & 0xFF;
543 }
544
545 static void set_cpu_amd( i386_cpu_info_t * info_p )
546 {
547 set_cpu_generic(info_p);
548 set_amd_cache_info(info_p);
549 info_p->cpuid_model_string = get_amd_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype);
550 }
551
552 static void set_cpu_nsc( i386_cpu_info_t * info_p )
553 {
554 set_cpu_generic(info_p);
555 set_amd_cache_info(info_p);
556
557 /* check for brand id string */
558 if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX1) {
559 info_p->cpuid_model_string = "AMD Geode GX1";
560 } else if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX2) {
561 info_p->cpuid_model_string = "AMD Geode GX";
562 } else {
563 info_p->cpuid_model_string = "Unknown National Semiconductor";
564 }
565 info_p->cpuid_cpu_type = CPU_TYPE_X86;
566 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1;
567 }
568
569 static void
570 set_cpu_generic(i386_cpu_info_t *info_p)
571 {
572 uint32_t cpuid_result[4];
573 uint32_t max_extid;
574 char str[128], *p;
575
576 /* get extended cpuid results */
577 do_cpuid(0x80000000, cpuid_result);
578 max_extid = cpuid_result[eax];
579
580 /* check to see if we can get brand string */
581 if (max_extid >= 0x80000004) {
582 /*
583 * The brand string 48 bytes (max), guaranteed to
584 * be NUL terminated.
585 */
586 do_cpuid(0x80000002, cpuid_result);
587 bcopy((char *)cpuid_result, &str[0], 16);
588 do_cpuid(0x80000003, cpuid_result);
589 bcopy((char *)cpuid_result, &str[16], 16);
590 do_cpuid(0x80000004, cpuid_result);
591 bcopy((char *)cpuid_result, &str[32], 16);
592 for (p = str; *p != '\0'; p++) {
593 if (*p != ' ') break;
594 }
595 strncpy(info_p->cpuid_brand_string,
596 p, sizeof(info_p->cpuid_brand_string)-1);
597 info_p->cpuid_brand_string[sizeof(info_p->cpuid_brand_string)-1] = '\0';
598
599 if (!strcmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN)) {
600 /*
601 * This string means we have a BIOS-programmable brand string,
602 * and the BIOS couldn't figure out what sort of CPU we have.
603 */
604 info_p->cpuid_brand_string[0] = '\0';
605 }
606 }
607
608 /* get processor signature and decode */
609 do_cpuid(1, cpuid_result);
610 info_p->cpuid_signature = cpuid_result[eax];
611 info_p->cpuid_stepping = bitfield(cpuid_result[eax], 3, 0);
612 info_p->cpuid_model = bitfield(cpuid_result[eax], 7, 4);
613 info_p->cpuid_family = bitfield(cpuid_result[eax], 11, 8);
614 info_p->cpuid_type = bitfield(cpuid_result[eax], 13, 12);
615 info_p->cpuid_extmodel = bitfield(cpuid_result[eax], 19, 16);
616 info_p->cpuid_extfamily = bitfield(cpuid_result[eax], 27, 20);
617 info_p->cpuid_brand = bitfield(cpuid_result[ebx], 7, 0);
618 info_p->cpuid_logical_per_package =
619 bitfield(cpuid_result[ebx], 23, 16);
620 info_p->cpuid_features = quad(cpuid_result[ecx], cpuid_result[edx]);
621
622 if (max_extid >= 0x80000001) {
623 do_cpuid(0x80000001, cpuid_result);
624 info_p->cpuid_extfeatures =
625 quad(cpuid_result[ecx], cpuid_result[edx]);
626 }
627
628 return;
629 }
630
631 static void
632 set_cpu_unknown(__unused i386_cpu_info_t *info_p)
633 {
634 info_p->cpuid_model_string = "Unknown";
635 }
636
637
638 static struct {
639 uint64_t mask;
640 const char *name;
641 } feature_map[] = {
642 {CPUID_FEATURE_FPU, "FPU",},
643 {CPUID_FEATURE_VME, "VME",},
644 {CPUID_FEATURE_DE, "DE",},
645 {CPUID_FEATURE_PSE, "PSE",},
646 {CPUID_FEATURE_TSC, "TSC",},
647 {CPUID_FEATURE_MSR, "MSR",},
648 {CPUID_FEATURE_PAE, "PAE",},
649 {CPUID_FEATURE_MCE, "MCE",},
650 {CPUID_FEATURE_CX8, "CX8",},
651 {CPUID_FEATURE_APIC, "APIC",},
652 {CPUID_FEATURE_SEP, "SEP",},
653 {CPUID_FEATURE_MTRR, "MTRR",},
654 {CPUID_FEATURE_PGE, "PGE",},
655 {CPUID_FEATURE_MCA, "MCA",},
656 {CPUID_FEATURE_CMOV, "CMOV",},
657 {CPUID_FEATURE_PAT, "PAT",},
658 {CPUID_FEATURE_PSE36, "PSE36",},
659 {CPUID_FEATURE_PSN, "PSN",},
660 {CPUID_FEATURE_CLFSH, "CLFSH",},
661 {CPUID_FEATURE_DS, "DS",},
662 {CPUID_FEATURE_ACPI, "ACPI",},
663 {CPUID_FEATURE_MMX, "MMX",},
664 {CPUID_FEATURE_FXSR, "FXSR",},
665 {CPUID_FEATURE_SSE, "SSE",},
666 {CPUID_FEATURE_SSE2, "SSE2",},
667 {CPUID_FEATURE_SS, "SS",},
668 {CPUID_FEATURE_HTT, "HTT",},
669 {CPUID_FEATURE_TM, "TM",},
670 {CPUID_FEATURE_SSE3, "SSE3"},
671 {CPUID_FEATURE_MONITOR, "MON"},
672 {CPUID_FEATURE_DSCPL, "DSCPL"},
673 {CPUID_FEATURE_VMX, "VMX"},
674 {CPUID_FEATURE_SMX, "SMX"},
675 {CPUID_FEATURE_EST, "EST"},
676 {CPUID_FEATURE_TM2, "TM2"},
677 {CPUID_FEATURE_MNI, "MNI"},
678 {CPUID_FEATURE_CID, "CID"},
679 {CPUID_FEATURE_CX16, "CX16"},
680 {CPUID_FEATURE_xTPR, "TPR"},
681 {0, 0}
682 },
683 extfeature_map[] = {
684 {CPUID_EXTFEATURE_SYSCALL, "SYSCALL"},
685 {CPUID_EXTFEATURE_XD, "XD"},
686 {CPUID_EXTFEATURE_EM64T, "EM64T"},
687 {CPUID_EXTFEATURE_LAHF, "LAHF"},
688 {0, 0}
689 };
690
691 char *
692 cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len)
693 {
694 int len = -1;
695 char *p = buf;
696 int i;
697
698 for (i = 0; feature_map[i].mask != 0; i++) {
699 if ((features & feature_map[i].mask) == 0)
700 continue;
701 if (len > 0)
702 *p++ = ' ';
703 len = min(strlen(feature_map[i].name), (buf_len-1) - (p-buf));
704 if (len == 0)
705 break;
706 bcopy(feature_map[i].name, p, len);
707 p += len;
708 }
709 *p = '\0';
710 return buf;
711 }
712
713 char *
714 cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len)
715 {
716 int len = -1;
717 char *p = buf;
718 int i;
719
720 for (i = 0; extfeature_map[i].mask != 0; i++) {
721 if ((extfeatures & extfeature_map[i].mask) == 0)
722 continue;
723 if (len > 0)
724 *p++ = ' ';
725 len = min(strlen(extfeature_map[i].name), (buf_len-1)-(p-buf));
726 if (len == 0)
727 break;
728 bcopy(extfeature_map[i].name, p, len);
729 p += len;
730 }
731 *p = '\0';
732 return buf;
733 }
734
735 void
736 cpuid_feature_display(
737 const char *header)
738 {
739 char buf[256];
740
741 kprintf("%s: %s\n", header,
742 cpuid_get_feature_names(cpuid_features(),
743 buf, sizeof(buf)));
744 if (cpuid_features() & CPUID_FEATURE_HTT) {
745 #define s_if_plural(n) ((n > 1) ? "s" : "")
746 kprintf(" HTT: %d core%s per package;"
747 " %d logical cpu%s per package\n",
748 cpuid_cpu_info.cpuid_cores_per_package,
749 s_if_plural(cpuid_cpu_info.cpuid_cores_per_package),
750 cpuid_cpu_info.cpuid_logical_per_package,
751 s_if_plural(cpuid_cpu_info.cpuid_logical_per_package));
752 }
753 }
754
755 void
756 cpuid_extfeature_display(
757 const char *header)
758 {
759 char buf[256];
760
761 kprintf("%s: %s\n", header,
762 cpuid_get_extfeature_names(cpuid_extfeatures(),
763 buf, sizeof(buf)));
764 }
765
766 void
767 cpuid_cpu_display(
768 const char *header)
769 {
770 if (cpuid_cpu_info.cpuid_brand_string[0] != '\0') {
771 kprintf("%s: %s\n", header, cpuid_cpu_info.cpuid_brand_string);
772 }
773 }
774
775 unsigned int
776 cpuid_family(void)
777 {
778 return cpuid_cpu_info.cpuid_family;
779 }
780
781 cpu_type_t
782 cpuid_cputype(void)
783 {
784 return cpuid_cpu_info.cpuid_cpu_type;
785 }
786
787 cpu_subtype_t
788 cpuid_cpusubtype(void)
789 {
790 return cpuid_cpu_info.cpuid_cpu_subtype;
791 }
792
793 uint64_t
794 cpuid_features(void)
795 {
796 static int checked = 0;
797 char fpu_arg[16] = { 0 };
798 if (!checked) {
799 /* check for boot-time fpu limitations */
800 if (PE_parse_boot_arg("_fpu", &fpu_arg[0])) {
801 printf("limiting fpu features to: %s\n", fpu_arg);
802 if (!strncmp("387", fpu_arg, sizeof "387") || !strncmp("mmx", fpu_arg, sizeof "mmx")) {
803 printf("no sse or sse2\n");
804 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR);
805 } else if (!strncmp("sse", fpu_arg, sizeof "sse")) {
806 printf("no sse2\n");
807 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE2);
808 }
809 }
810 checked = 1;
811 }
812 return cpuid_cpu_info.cpuid_features;
813 }
814
815 uint64_t
816 cpuid_extfeatures(void)
817 {
818 return cpuid_cpu_info.cpuid_extfeatures;
819 }
820
821 i386_cpu_info_t *
822 cpuid_info(void)
823 {
824 return &cpuid_cpu_info;
825 }
826
827 void
828 cpuid_set_info(void)
829 {
830 cpuid_get_info(&cpuid_cpu_info);
831 }
832
833 #if MACH_KDB
834
835 /*
836 * Display the cpuid
837 * *
838 * cp
839 */
840 void
841 db_cpuid(__unused db_expr_t addr,
842 __unused int have_addr,
843 __unused db_expr_t count,
844 __unused char *modif)
845 {
846
847 uint32_t i, mid;
848 uint32_t cpid[4];
849
850 do_cpuid(0, cpid); /* Get the first cpuid which is the number of
851 * basic ids */
852 db_printf("%08X - %08X %08X %08X %08X\n",
853 0, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
854
855 mid = cpid[eax]; /* Set the number */
856 for (i = 1; i <= mid; i++) { /* Dump 'em out */
857 do_cpuid(i, cpid); /* Get the next */
858 db_printf("%08X - %08X %08X %08X %08X\n",
859 i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
860 }
861 db_printf("\n");
862
863 do_cpuid(0x80000000, cpid); /* Get the first extended cpuid which
864 * is the number of extended ids */
865 db_printf("%08X - %08X %08X %08X %08X\n",
866 0x80000000, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
867
868 mid = cpid[eax]; /* Set the number */
869 for (i = 0x80000001; i <= mid; i++) { /* Dump 'em out */
870 do_cpuid(i, cpid); /* Get the next */
871 db_printf("%08X - %08X %08X %08X %08X\n",
872 i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
873 }
874 }
875
876 #endif
mirror of XNU