2 * Copyright (c) 2003-2007 Apple Inc. All rights reserved.
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
28 #include <vm/vm_kern.h>
29 #include <kern/kalloc.h>
30 #include <mach/machine.h>
31 #include <i386/cpu_threads.h>
32 #include <i386/cpuid.h>
33 #include <i386/machine_cpu.h>
34 #include <i386/lock.h>
35 #include <i386/perfmon.h>
36 #include <i386/pmCPU.h>
38 #define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
39 #define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l)
42 * Kernel parameter determining whether threads are halted unconditionally
43 * in the idle state. This is the default behavior.
44 * See machine_idle() for use.
48 x86_pkg_t
*x86_pkgs
= NULL
;
49 uint32_t num_packages
= 0;
50 uint32_t num_Lx_caches
[MAX_CACHE_DEPTH
] = { 0 };
52 static x86_pkg_t
*free_pkgs
= NULL
;
53 static x86_core_t
*free_cores
= NULL
;
55 static x86_cpu_cache_t
*x86_caches
= NULL
;
56 static uint32_t num_caches
= 0;
58 decl_simple_lock_data(, x86_topo_lock
);
60 static x86_cpu_cache_t
*
63 x86_cpu_cache_t
*cache
;
66 if (x86_caches
== NULL
) {
67 cache
= kalloc(sizeof(x86_cpu_cache_t
) + (MAX_CPUS
* sizeof(x86_lcpu_t
*)));
72 x86_caches
= cache
->next
;
76 bzero(cache
, sizeof(x86_cpu_cache_t
));
78 cache
->maxcpus
= MAX_CPUS
;
79 for (i
= 0; i
< cache
->maxcpus
; i
+= 1) {
80 cache
->cpus
[i
] = NULL
;
89 x86_cache_free(x86_cpu_cache_t
*cache
)
92 if (cache
->level
> 0 && cache
->level
<= MAX_CACHE_DEPTH
)
93 num_Lx_caches
[cache
->level
- 1] -= 1;
94 cache
->next
= x86_caches
;
99 * This returns a list of cache structures that represent the
100 * caches for a CPU. Some of the structures may have to be
101 * "freed" if they are actually shared between CPUs.
103 static x86_cpu_cache_t
*
106 x86_cpu_cache_t
*root
= NULL
;
107 x86_cpu_cache_t
*cur
= NULL
;
108 x86_cpu_cache_t
*last
= NULL
;
110 uint32_t cache_info
[4];
113 do_cpuid(0, cache_info
);
115 if (cache_info
[eax
] < 4) {
117 * Processor does not support deterministic
118 * cache information. Don't report anything
123 for (index
= 0; ; index
+= 1) {
125 cache_info
[ecx
] = index
;
132 * See if all levels have been queried.
134 if (bitfield(cache_info
[eax
], 4, 0) == 0)
137 cur
= x86_cache_alloc();
142 cur
->type
= bitfield(cache_info
[eax
], 4, 0);
143 cur
->level
= bitfield(cache_info
[eax
], 7, 5);
144 cur
->nlcpus
= bitfield(cache_info
[eax
], 25, 14) + 1;
145 cur
->line_size
= bitfield(cache_info
[ebx
], 11, 0) + 1;
146 cur
->partitions
= bitfield(cache_info
[ebx
], 21, 12) + 1;
147 cur
->ways
= bitfield(cache_info
[ebx
], 31, 22) + 1;
148 nsets
= bitfield(cache_info
[ecx
], 31, 0) + 1;
149 cur
->cache_size
= cur
->line_size
* cur
->ways
* cur
->partitions
* nsets
;
159 num_Lx_caches
[cur
->level
- 1] += 1;
166 cpu_is_hyperthreaded(void)
168 if (cpuid_features() & CPUID_FEATURE_HTT
)
169 return (cpuid_info()->cpuid_logical_per_package
/
170 cpuid_info()->cpuid_cores_per_package
) > 1;
176 x86_lcpu_init(int cpu
)
182 cpup
= cpu_datap(cpu
);
190 lcpu
->pnum
= cpup
->cpu_phys_number
;
191 lcpu
->halted
= FALSE
; /* XXX is this correct? */
192 lcpu
->idle
= FALSE
; /* XXX is this correct? */
193 for (i
= 0; i
< MAX_CACHE_DEPTH
; i
+= 1)
194 lcpu
->caches
[i
] = NULL
;
196 lcpu
->master
= (lcpu
->pnum
== (unsigned int) master_cpu
);
197 lcpu
->primary
= (lcpu
->pnum
% cpuid_info()->cpuid_logical_per_package
) == 0;
201 x86_core_alloc(int cpu
)
206 uint32_t lcpus_per_core
;
208 cpup
= cpu_datap(cpu
);
210 simple_lock(&x86_topo_lock
);
211 if (free_cores
!= NULL
) {
213 free_cores
= core
->next
;
215 simple_unlock(&x86_topo_lock
);
217 simple_unlock(&x86_topo_lock
);
218 core
= kalloc(sizeof(x86_core_t
));
220 panic("x86_core_alloc() kalloc of x86_core_t failed!\n");
223 bzero((void *) core
, sizeof(x86_core_t
));
225 cpu_in_pkg
= cpu
% cpuid_info()->cpuid_logical_per_package
;
226 lcpus_per_core
= cpuid_info()->cpuid_logical_per_package
/
227 cpuid_info()->cpuid_cores_per_package
;
229 core
->pcore_num
= cpup
->cpu_phys_number
/ lcpus_per_core
;
230 core
->lcore_num
= core
->pcore_num
% cpuid_info()->cpuid_cores_per_package
;
232 core
->flags
= X86CORE_FL_PRESENT
| X86CORE_FL_READY
;
238 x86_core_free(x86_core_t
*core
)
240 simple_lock(&x86_topo_lock
);
241 core
->next
= free_cores
;
243 simple_unlock(&x86_topo_lock
);
247 x86_package_find(int cpu
)
253 cpup
= cpu_datap(cpu
);
255 pkg_num
= cpup
->cpu_phys_number
/ cpuid_info()->cpuid_logical_per_package
;
258 while (pkg
!= NULL
) {
259 if (pkg
->ppkg_num
== pkg_num
)
268 x86_core_find(int cpu
)
275 cpup
= cpu_datap(cpu
);
277 core_num
= cpup
->cpu_phys_number
278 / (cpuid_info()->cpuid_logical_per_package
279 / cpuid_info()->cpuid_cores_per_package
);
281 pkg
= x86_package_find(cpu
);
286 while (core
!= NULL
) {
287 if (core
->pcore_num
== core_num
)
296 x86_core_add_lcpu(x86_core_t
*core
, x86_lcpu_t
*lcpu
)
298 x86_cpu_cache_t
*list
;
299 x86_cpu_cache_t
*cur
;
300 x86_core_t
*cur_core
;
301 x86_lcpu_t
*cur_lcpu
;
307 assert(core
!= NULL
);
308 assert(lcpu
!= NULL
);
311 * Add the cache data to the topology.
313 list
= x86_cache_list();
315 simple_lock(&x86_topo_lock
);
317 while (list
!= NULL
) {
319 * Remove the cache from the front of the list.
324 level
= cur
->level
- 1;
327 * If the cache isn't shared then just put it where it
330 if (cur
->nlcpus
== 1) {
335 * We'll assume that all of the caches at a particular level
336 * have the same sharing. So if we have a cache already at
337 * this level, we'll just skip looking for the match.
339 if (lcpu
->caches
[level
] != NULL
) {
345 * This is a shared cache, so we have to figure out if
346 * this is the first time we've seen this cache. We do
347 * this by searching through the package and seeing if
348 * a related core is already describing this cache.
350 * NOTE: This assumes that CPUs whose ID mod <# sharing cache>
351 * are indeed sharing the cache.
353 cpu_mask
= lcpu
->pnum
& ~(cur
->nlcpus
- 1);
354 cur_core
= core
->package
->cores
;
357 while (cur_core
!= NULL
&& !found
) {
358 cur_lcpu
= cur_core
->lcpus
;
359 while (cur_lcpu
!= NULL
&& !found
) {
360 if ((cur_lcpu
->pnum
& ~(cur
->nlcpus
- 1)) == cpu_mask
) {
361 lcpu
->caches
[level
] = cur_lcpu
->caches
[level
];
366 * Put the new CPU into the list of the cache.
368 cur
= lcpu
->caches
[level
];
369 for (i
= 0; i
< cur
->nlcpus
; i
+= 1) {
370 if (cur
->cpus
[i
] == NULL
) {
376 cur_lcpu
= cur_lcpu
->next
;
379 cur_core
= cur_core
->next
;
384 cur
->next
= lcpu
->caches
[level
];
385 lcpu
->caches
[level
] = cur
;
391 * Add the Logical CPU to the core.
393 lcpu
->next
= core
->lcpus
;
396 core
->num_lcpus
+= 1;
398 simple_unlock(&x86_topo_lock
);
402 x86_package_alloc(int cpu
)
407 cpup
= cpu_datap(cpu
);
409 simple_lock(&x86_topo_lock
);
410 if (free_pkgs
!= NULL
) {
412 free_pkgs
= pkg
->next
;
414 simple_unlock(&x86_topo_lock
);
416 simple_unlock(&x86_topo_lock
);
417 pkg
= kalloc(sizeof(x86_pkg_t
));
419 panic("x86_package_alloc() kalloc of x86_pkg_t failed!\n");
422 bzero((void *) pkg
, sizeof(x86_pkg_t
));
424 pkg
->ppkg_num
= cpup
->cpu_phys_number
425 / cpuid_info()->cpuid_logical_per_package
;
427 pkg
->lpkg_num
= num_packages
;
428 atomic_incl((long *) &num_packages
, 1);
430 pkg
->flags
= X86PKG_FL_PRESENT
| X86PKG_FL_READY
;
435 x86_package_free(x86_pkg_t
*pkg
)
437 simple_lock(&x86_topo_lock
);
438 pkg
->next
= free_pkgs
;
440 atomic_decl((long *) &num_packages
, 1);
441 simple_unlock(&x86_topo_lock
);
445 x86_package_add_core(x86_pkg_t
*pkg
, x86_core_t
*core
)
448 assert(core
!= NULL
);
450 core
->next
= pkg
->cores
;
457 cpu_thread_alloc(int cpu
)
464 cpup
= cpu_datap(cpu
);
466 phys_cpu
= cpup
->cpu_phys_number
;
471 * Assume that all cpus have the same features.
473 if (cpu_is_hyperthreaded()) {
474 cpup
->cpu_threadtype
= CPU_THREADTYPE_INTEL_HTT
;
476 cpup
->cpu_threadtype
= CPU_THREADTYPE_NONE
;
480 * Only allow one to manipulate the topology at a time.
482 simple_lock(&x86_topo_lock
);
485 * Get the core for this logical CPU.
488 core
= x86_core_find(cpu
);
491 * Core structure hasn't been created yet, do it now.
493 * Get the package that the core is part of.
496 pkg
= x86_package_find(cpu
);
499 * Package structure hasn't been created yet, do it now.
501 simple_unlock(&x86_topo_lock
);
502 pkg
= x86_package_alloc(cpu
);
503 simple_lock(&x86_topo_lock
);
504 if (x86_package_find(cpu
) != NULL
) {
505 x86_package_free(pkg
);
510 * Add the new package to the global list of packages.
512 pkg
->next
= x86_pkgs
;
517 * Allocate the core structure now.
519 simple_unlock(&x86_topo_lock
);
520 core
= x86_core_alloc(cpu
);
521 simple_lock(&x86_topo_lock
);
522 if (x86_core_find(cpu
) != NULL
) {
528 * Add it to the package.
530 x86_package_add_core(pkg
, core
);
531 machine_info
.physical_cpu_max
+= 1;
534 * Allocate performance counter structure.
536 simple_unlock(&x86_topo_lock
);
537 core
->pmc
= pmc_alloc();
538 simple_lock(&x86_topo_lock
);
542 * Done manipulating the topology, so others can get in.
544 machine_info
.logical_cpu_max
+= 1;
545 simple_unlock(&x86_topo_lock
);
547 x86_core_add_lcpu(core
, &cpup
->lcpu
);
549 return (void *) core
;
553 cpu_thread_init(void)
555 int my_cpu
= get_cpu_number();
556 cpu_data_t
*cpup
= current_cpu_datap();
558 static int initialized
= 0;
561 * If we're the boot processor, we do all of the initialization of
562 * the CPU topology infrastructure.
564 if (my_cpu
== master_cpu
&& !initialized
) {
565 simple_lock_init(&x86_topo_lock
, 0);
568 * Put this logical CPU into the physical CPU topology.
570 cpup
->lcpu
.core
= cpu_thread_alloc(my_cpu
);
576 * Do the CPU accounting.
578 core
= cpup
->lcpu
.core
;
579 simple_lock(&x86_topo_lock
);
580 machine_info
.logical_cpu
+= 1;
581 if (core
->active_lcpus
== 0)
582 machine_info
.physical_cpu
+= 1;
583 core
->active_lcpus
+= 1;
584 cpup
->lcpu
.halted
= FALSE
;
585 cpup
->lcpu
.idle
= FALSE
;
586 simple_unlock(&x86_topo_lock
);
588 pmCPUMarkRunning(cpup
);
589 etimer_resync_deadlines();
593 * Called for a cpu to halt permanently
594 * (as opposed to halting and expecting an interrupt to awaken it).
597 cpu_thread_halt(void)
600 cpu_data_t
*cpup
= current_cpu_datap();
602 simple_lock(&x86_topo_lock
);
603 machine_info
.logical_cpu
-= 1;
604 cpup
->lcpu
.idle
= TRUE
;
605 core
= cpup
->lcpu
.core
;
606 core
->active_lcpus
-= 1;
607 if (core
->active_lcpus
== 0)
608 machine_info
.physical_cpu
-= 1;
609 simple_unlock(&x86_topo_lock
);
612 * Let the power management code determine the best way to "stop"
615 ml_set_interrupts_enabled(FALSE
);
617 pmCPUHalt(PM_HALT_NORMAL
);