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2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
4 * @APPLE_LICENSE_HEADER_START@
6 * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
8 * This file contains Original Code and/or Modifications of Original Code
9 * as defined in and that are subject to the Apple Public Source License
10 * Version 2.0 (the 'License'). You may not use this file except in
11 * compliance with the License. Please obtain a copy of the License at
12 * http://www.opensource.apple.com/apsl/ and read it before using this
15 * The Original Code and all software distributed under the License are
16 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
17 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
18 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
20 * Please see the License for the specific language governing rights and
21 * limitations under the License.
23 * @APPLE_LICENSE_HEADER_END@
25 #ifndef _PEXPERT_PPC_PROTOS_H_
26 #define _PEXPERT_PPC_PROTOS_H_
28 #define mtibatu(n, reg) __asm__ volatile("mtibatu " # n ", %0" : : "r" (reg))
29 #define mtibatl(n, reg) __asm__ volatile("mtibatl " # n ", %0" : : "r" (reg))
31 #define mtdbatu(n, reg) __asm__ volatile("mtdbatu " # n ", %0" : : "r" (reg))
32 #define mtdbatl(n, reg) __asm__ volatile("mtdbatl " # n ", %0" : : "r" (reg))
34 #define mfibatu(reg, n) __asm__ volatile("mfibatu %0, " # n : "=r" (reg))
35 #define mfibatl(reg, n) __asm__ volatile("mfibatl %0, " # n : "=r" (reg))
37 #define mfdbatu(reg, n) __asm__ volatile("mfdbatu %0, " # n : "=r" (reg))
38 #define mfdbatl(reg, n) __asm__ volatile("mfdbatl %0, " # n : "=r" (reg))
40 #define mtsprg(n, reg) __asm__ volatile("mtsprg " # n ", %0" : : "r" (reg))
41 #define mfsprg(reg, n) __asm__ volatile("mfsprg %0, " # n : "=r" (reg))
43 #define mtspr(spr, val) __asm__ volatile("mtspr " # spr ", %0" : : "r" (val))
44 #define mfspr(reg, spr) __asm__ volatile("mfspr %0, " # spr : "=r" (reg))
47 * Various memory/IO synchronisation instructions
50 /* Use eieio as a memory barrier to order stores.
51 * Useful for device control and PTE maintenance.
55 __asm__ volatile("eieio")
57 /* Use sync to ensure previous stores have completed.
58 This is required when manipulating locks and/or
59 maintaining PTEs or other shared structures on SMP
64 __asm__ volatile("sync")
66 /* Use isync to sychronize context; that is, the ensure
67 no prefetching of instructions happen before the
72 __asm__ volatile("isync")
75 //------------------------------------------------------------------------
77 static __inline__
unsigned int byte_reverse_word(unsigned int word
);
78 static __inline__
unsigned int byte_reverse_word(unsigned int word
) {
80 __asm__
volatile("lwbrx %0, 0, %1" : "=r" (result
) : "r" (&word
));
84 //------------------------------------------------------------------------
85 // from ppc/serial_io.h
86 extern void initialize_serial(void * scc_phys_base
);
89 //------------------------------------------------------------------------
90 // from ppc/POWERMAC/device_tree.h
91 extern void ofw_init(void *);
93 //------------------------------------------------------------------------
94 // from osfmk/ppc/POWERMAC/video_console.c
96 extern void initialize_screen(void *, unsigned int);
98 extern boolean_t
vc_progress_initialize( void * desc
,
99 const unsigned char * data
,
100 const unsigned char * clut
);
102 extern void vc_display_icon( void * desc
,
103 const unsigned char * data
);
105 // from osfmk/ppc/serial_console.c
106 extern int switch_to_serial_console(void);
107 extern void switch_to_old_console(int old_console
);
109 //------------------------------------------------------------------------
111 /* Note also : if any new SPL's are introduced, please add to debugging list*/
112 #define SPLOFF 0 /* all interrupts disabled TODO NMGS */
113 #define SPLPOWER 1 /* power failure (unused) */
114 #define SPLHIGH 2 /* TODO NMGS any non-zero, non-INTPRI value */
115 #define SPLSCHED SPLHIGH
116 #define SPLCLOCK SPLSCHED /* hard clock */
117 #define SPLVM 4 /* pmap manipulations */
118 #define SPLBIO 8 /* block I/O */
119 #define SPLIMP 8 /* network & malloc */
120 #define SPLTTY 16 /* TTY */
121 #define SPLNET 24 /* soft net */
122 #define SPLSCLK 27 /* soft clock */
123 #define SPLLO 32 /* no interrupts masked */
125 /* internal - masked in to spl level if ok to lower priority (splx, splon)
126 * the mask bit is never seen externally
128 #define SPL_LOWER_MASK 0x8000
130 #define SPL_CMP_GT(a, b) ((unsigned)(a) > (unsigned)(b))
131 #define SPL_CMP_LT(a, b) ((unsigned)(a) < (unsigned)(b))
132 #define SPL_CMP_GE(a, b) ((unsigned)(a) >= (unsigned)(b))
133 #define SPL_CMP_LE(a, b) ((unsigned)(a) <= (unsigned)(b))
135 typedef unsigned spl_t
;
137 //------------------------------------------------------------------------
138 // from bsd/dev/ppc/busses.h which clashes with mach/device/device_types.h
139 typedef int io_req_t
;
142 //typedef struct ipc_port *ipc_port_t;
144 extern void cninit(void);
147 * Temporarily stolen from Firmware.h
150 void dbgDisp(unsigned int port
, unsigned int id
, unsigned int data
);
151 void dbgDispLL(unsigned int port
, unsigned int id
, unsigned int data
);
152 void fwSCCinit(unsigned int port
);
154 extern void dbgTrace(unsigned int item1
, unsigned int item2
, unsigned int item3
);
155 #if 1 /* (TEST/DEBUG) - eliminate inline */
156 extern __inline__
void dbgTrace(unsigned int item1
, unsigned int item2
, unsigned int item3
) {
158 __asm__
volatile("mr r3,%0" : : "r" (item1
) : "r3");
159 __asm__
volatile("mr r4,%0" : : "r" (item2
) : "r4");
160 __asm__
volatile("mr r5,%0" : : "r" (item3
) : "r5");
162 __asm__
volatile("lis r0,CutTrace@h" : : : "r0");
163 __asm__
volatile("ori r0,r0,CutTrace@l" : : : "r0");
165 __asm__
volatile("lis r0,hi16(CutTrace)" : : : "r0");
166 __asm__
volatile("ori r0,r0,lo16(CutTrace)" : : : "r0");
168 __asm__
volatile("sc");
173 extern void DoPreempt(void);
174 extern __inline__
void DoPreempt(void) {
176 __asm__
volatile("lis r0,DoPreemptCall@h" : : : "r0");
177 __asm__
volatile("ori r0,r0,DoPreemptCall@l" : : : "r0");
179 __asm__
volatile("lis r0,hi16(DoPreemptCall)" : : : "r0");
180 __asm__
volatile("ori r0,r0,lo16(DoPreemptCall)" : : : "r0");
182 __asm__
volatile("sc");
186 extern void CreateFakeIO(void);
187 extern __inline__
void CreateFakeIO(void) {
189 __asm__
volatile("lis r0,CreateFakeIOCall@h" : : : "r0");
190 __asm__
volatile("ori r0,r0,CreateFakeIOCall@l" : : : "r0");
192 __asm__
volatile("lis r0,hi16(CreateFakeIOCall)" : : : "r0");
193 __asm__
volatile("ori r0,r0,lo16(CreateFakeIOCall)" : : : "r0");
195 __asm__
volatile("sc");
199 extern void StoreReal(unsigned int val
, unsigned int addr
);
200 extern void ReadReal(unsigned int raddr
, unsigned int *vaddr
);
201 extern void ClearReal(unsigned int addr
, unsigned int lgn
);
202 extern void LoadDBATs(unsigned int *bat
);
203 extern void LoadIBATs(unsigned int *bat
);
204 extern unsigned int LLTraceSet(unsigned int tflags
);
205 extern void GratefulDebInit(void);
206 extern void GratefulDebDisp(unsigned int coord
, unsigned int data
);
207 extern void checkNMI(void);
210 * Temporarily stolen from ppc/cpu_number.h
212 int cpu_number(void);
214 #endif /* _PEXPERT_PPC_PROTOS_H_ */