osfmk/ppc/commpage/cacheflush.s

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
   7  *
   8  * This file contains Original Code and/or Modifications of Original Code
   9  * as defined in and that are subject to the Apple Public Source License
  10  * Version 2.0 (the 'License'). You may not use this file except in
  11  * compliance with the License. Please obtain a copy of the License at
  12  * http://www.opensource.apple.com/apsl/ and read it before using this
  13  * file.
  14  *
  15  * The Original Code and all software distributed under the License are
  16  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  17  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  18  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  20  * Please see the License for the specific language governing rights and
  21  * limitations under the License.
  22  *
  23  * @APPLE_LICENSE_HEADER_END@
  24  */
  25
  26 #define ASSEMBLER
  27 #include <sys/appleapiopts.h>
  28 #include <ppc/asm.h>                                    // EXT, LEXT
  29 #include <machine/cpu_capabilities.h>
  30 #include <machine/commpage.h>
  31
  32         .text
  33         .align  2
  34         .globl  EXT(commpage_flush_dcache)
  35         .globl  EXT(commpage_flush_icache)
  36
  37
  38 // *********************************************
  39 // * C O M M P A G E _ F L U S H _ D C A C H E *
  40 // *********************************************
  41 //
  42 //      r3 = ptr to 1st byte to flush
  43 //      r4 = length to flush (may be 0)
  44
  45 commpage_flush_dcache:
  46         cmpwi   r4,0                    // length 0?
  47         lhz             r5,_COMM_PAGE_CACHE_LINESIZE(0)
  48         subi    r9,r5,1                 // get (linesize-1)
  49         and             r0,r3,r9                // get offset within line of 1st byte
  50         add             r4,r4,r0                // adjust length so we flush them all
  51         add             r4,r4,r9                // round length up...
  52         andc    r4,r4,r9                // ...to multiple of cache lines
  53         beqlr--                                 // length was 0, so exit
  54 1:
  55         sub.    r4,r4,r5                // more to go?
  56         dcbf    0,r3                    // flush another line
  57         add             r3,r3,r5
  58         bne             1b
  59         sync                                    // make sure lines are flushed before we return
  60         blr
  61
  62         COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,0)        // matches all CPUs
  63
  64
  65 // *********************************************
  66 // * C O M M P A G E _ F L U S H _ I C A C H E *
  67 // *********************************************
  68 //
  69 //      r3 = ptr to 1st byte to flush
  70 //      r4 = length to flush (may be 0)
  71
  72 commpage_flush_icache:
  73         cmpwi   r4,0                    // length 0?
  74         lhz             r5,_COMM_PAGE_CACHE_LINESIZE(0)
  75         subi    r9,r5,1                 // get (linesize-1)
  76         and             r0,r3,r9                // get offset within line of 1st byte
  77         add             r4,r4,r0                // adjust length so we flush them all
  78         mr              r7,r3                   // copy ptr
  79         add             r4,r4,r9                // round length up...
  80         andc    r4,r4,r9                // ...to multiple of cache lines
  81         mr              r6,r4                   // copy length
  82         beqlr--                                 // length was 0, so exit
  83 1:
  84         sub.    r4,r4,r5                // more to go?
  85         dcbf    0,r3                    // flush another line
  86         add             r3,r3,r5
  87         bne             1b
  88         sync                                    // make sure lines are flushed
  89 2:
  90         sub.    r6,r6,r5                // more to go?
  91         icbi    0,r7
  92         add             r7,r7,r5
  93         bne             2b
  94         isync                                   // make sure we haven't prefetched old instructions
  95
  96         blr
  97
  98         COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,0)        // matches all CPUs
  99
 100