osfmk/arm/trap.h

   1 /*
   2  * Copyright (c) 2007 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31 /*
  32  * Mach Operating System
  33  * Copyright (c) 1991,1990 Carnegie Mellon University
  34  * All Rights Reserved.
  35  *
  36  * Permission to use, copy, modify and distribute this software and its
  37  * documentation is hereby granted, provided that both the copyright
  38  * notice and this permission notice appear in all copies of the
  39  * software, derivative works or modified versions, and any portions
  40  * thereof, and that both notices appear in supporting documentation.
  41  *
  42  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  43  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  44  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  45  *
  46  * Carnegie Mellon requests users of this software to return to
  47  *
  48  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  49  *  School of Computer Science
  50  *  Carnegie Mellon University
  51  *  Pittsburgh PA 15213-3890
  52  *
  53  * any improvements or extensions that they make and grant Carnegie Mellon
  54  * the rights to redistribute these changes.
  55  */
  56 /*
  57  */
  58
  59 #ifndef _ARM_TRAP_H_
  60 #define _ARM_TRAP_H_
  61
  62 /*
  63  * Hardware trap vectors for ARM.
  64  */
  65
  66 #define T_RESET                 0
  67 #define T_UNDEF                 1
  68 #define T_SWI                   2
  69 #define T_PREFETCH_ABT          3
  70 #define T_DATA_ABT              4
  71 #define T_IRQ                   6
  72 #define T_FIQ                   7
  73 #define T_PMU                   8
  74
  75
  76 #define TRAP_NAMES "reset", "undefined instruction", "software interrupt", \
  77                    "prefetch abort", "data abort", "irq interrupt", \
  78                    "fast interrupt", "perfmon"
  79
  80 /*
  81  * Page-fault trap codes.
  82  */
  83 #define T_PF_PROT               0x1             /* protection violation */
  84 #define T_PF_WRITE              0x2             /* write access */
  85 #define T_PF_USER               0x4             /* from user state */
  86
  87 #if !defined(ASSEMBLER) && defined(MACH_KERNEL)
  88
  89 #include <arm/thread.h>
  90
  91 #define GDB_TRAP_INSTR1 0xe7ffdefe
  92 #define GDB_TRAP_INSTR2 0xe7ffdeff
  93
  94 #define ARM_GDB_INSTR1  GDB_TRAP_INSTR1
  95 #define ARM_GDB_INSTR2  GDB_TRAP_INSTR2
  96
  97 #define IS_ARM_GDB_TRAP(op)     \
  98         (((op) == ARM_GDB_INSTR1) || ((op) == ARM_GDB_INSTR2))
  99
 100 #define THUMB_GDB_INSTR1        (GDB_TRAP_INSTR1 & 0xFFFF)
 101 #define THUMB_GDB_INSTR2        (GDB_TRAP_INSTR2 & 0xFFFF)
 102
 103 #define IS_THUMB_GDB_TRAP(op)   \
 104         (((op) == THUMB_GDB_INSTR1) || ((op) == THUMB_GDB_INSTR2))
 105
 106
 107 #define ARM_STR                 0x04000000      /* STR */
 108 #define ARM_STRH                0x000000B0      /* STRH */
 109 #define ARM_STRH_MASK           0x0E1000F0      /* STRH MASK */
 110 #define ARM_SDX_MASK            0x0C100000      /* SINGLE DATA TRANSFER */
 111 #define ARM_SNGL_DX_MASK        0x0C000000      /* SINGLE DATA TRANSFER MASK */
 112 #define ARM_SDX                 0x04000000
 113
 114 #define ARM_STM                 0x08000000      /* STM */
 115 #define ARM_BDX_MASK            0x0E100000      /* BLOCK DATA TRANSFER */
 116 #define ARM_BLK_MASK            0x0E000000      /* BLOCK DATA TRANSFER */
 117 #define ARM_BDX                 0x08000000      /* BLOCK DATA TRANSFER */
 118
 119 #define ARM_WRITE_BACK          0x00200000
 120 #define ARM_BASE_REG            0x000F0000
 121 #define ARM_INCREMENT           0x00800000
 122
 123 #define ARM_STC                 0x0C000000      /* STC */
 124 #define ARM_CDX_MASK            ARM_BDX_MASK    /* COPROCESSOR DATA TRANSFER */
 125 #define ARM_CBLK_MASK           ARM_BLK_MASK
 126 #define ARM_CDX                 0x0C000000      /* COPROCESSOR DATA TRANSFER */
 127
 128 #define ARM_SWP                 0x01000090      /* SWP */
 129 #define ARM_SWP_MASK            0x0FB00FF0      /* SWP */
 130
 131 #define ARM_POST_INDEXING       0x01000000
 132 #define ARM_IMMEDIATE           0x02000000
 133 #define ARM_LSL                 0
 134 #define ARM_LSR                 1
 135 #define ARM_ASR                 2
 136 #define ARM_ROR                 3
 137
 138 #define MCR_MASK        0x0F100F10
 139 #define MCR_CP15        0x0E000F10
 140 #define MCRR_MASK       0x0FF00F00
 141 #define MCRR_CP15       0x0C400F00
 142
 143 #define arm_mcr_cp15(op)        (((op)&MCR_MASK) == 0x0E000F10)
 144 #define arm_mcrr_cp15(op)       (((op)&0x0FF00F00) == 0x0C400F00)
 145
 146 #define IS_THUMB32(op)  (       \
 147         (((op) & 0xE000) == 0xE000) && (((op) & 0x1800) != 0x0000))
 148
 149 #define THUMB_LDR_1_MASK        0x8800          /* (1) forms of LD* instructions */
 150 #define THUMB_STR_1_MASK        0xF800          /* (1) forms of ST* instructions */
 151 #define THUMB_STR_2_MASK        0xFE00          /* (2) forms of ST* instructions */
 152 #define THUMB_STR_3_MASK        0xF800          /* (3) forms of ST* instructions */
 153 #define THUMB_PUSH_MASK         0xFE00          /* PUSH instruction */
 154
 155 #define THUMB_LDRH_1            0x8800          /* LDRH(1) */
 156 #define THUMB_STMIA             0xC000          /* STMIA */
 157 #define THUMB_STR_1             0x6000          /* STR(1) */
 158 #define THUMB_STR_2             0x5000          /* STR(2) */
 159 #define THUMB_STR_3             0x9000          /* STR(3) */
 160 #define THUMB_STRB_1            0x7000          /* STRB(1) */
 161 #define THUMB_STRB_2            0x5400          /* STRB(2) */
 162 #define THUMB_STRH_1            0x8000          /* STRH(1) */
 163 #define THUMB_STRH_2            0x5200          /* STRH(2) */
 164 #define THUMB_PUSH              0xB400          /* PUSH */
 165 #define THUMB_LDMIA             0xC800          /* LDMIA */
 166 #define THUMB_POP               0xBC00          /* POP */
 167
 168
 169 /*
 170  * Shifts, masks, and other values for load/store multiple decoding; largely needed for
 171  * supporting misaligned accesses.
 172  */
 173 #define THUMB_STR_1_BASE_OFFSET 8               /* Offset of the base register field */
 174 #define THUMB_PUSH_EXTRA_OFFSET 8               /* Offset of the "extra" register field */
 175 #define ARM_STM_BASE_OFFSET     16              /* Offset of the base register field */
 176 #define ARM_STM_LOAD_OFFSET     20              /* Offset of the load flag */
 177 #define ARM_STM_WBACK_OFFSET    21              /* Offset of the writeback flag */
 178 #define ARM_STM_INCR_OFFSET     23              /* Offset of the increment flag */
 179 #define ARM_STM_BEFORE_OFFSET   24              /* Offset of the pre-index flag */
 180 #define ARM_REG_LIST_LR_OFFSET  14              /* Offset of LR in the register list */
 181 #define ARM_REG_LIST_PC_OFFSET  15              /* Offset of PC in the register list */
 182
 183 #define THUMB_STR_REG_LIST_MASK 0x000000FF      /* Offset of the reg list is 0 */
 184 #define THUMB_STR_1_BASE_MASK   0x00000700
 185 #define THUMB_PUSH_EXTRA_MASK   0x00000100
 186 #define ARM_STM_REG_LIST_MASK   0x0000FFFF      /* Offset of the reg list is 0 */
 187 #define ARM_STM_BASE_MASK       0x000F0000
 188 #define ARM_STM_LOAD_MASK       0x00100000
 189 #define ARM_STM_WBACK_MASK      0x00200000
 190 #define ARM_STM_INCR_MASK       0x00800000
 191 #define ARM_STM_BEFORE_MASK     0x01000000
 192 #define ARM_COND_MASK           0xF0000000      /* Mask for the condition code */
 193
 194 #define ARM_COND_UNCOND         0xF0000000      /* Instruction does not support condition codes */
 195
 196 #define ARM_SIMD_MASK0          0xFE000000
 197 #define ARM_SIMD_CODE0          0xF2000000
 198
 199 #define ARM_VFP_MASK0           0x0F000E10
 200 #define ARM_VFP_CODE0           0x0E000A00
 201
 202 #define ARM_SIMD_VFP_MASK0      0x0E000E00
 203 #define ARM_SIMD_VFP_CODE0      0x0C000A00
 204 #define ARM_SIMD_VFP_MASK1      0xFF100000
 205 #define ARM_SIMD_VFP_CODE1      0xF4000000
 206 #define ARM_SIMD_VFP_MASK2      0x0F000E10
 207 #define ARM_SIMD_VFP_CODE2      0x0E000A10
 208 #define ARM_SIMD_VFP_MASK3      0x0FE00E00
 209 #define ARM_SIMD_VFP_CODE3      0x0C400A00
 210
 211 #define IS_ARM_VFP(op)  (       \
 212         (((op) & ARM_SIMD_MASK0) == ARM_SIMD_CODE0)     \
 213          ||(((op) & ARM_VFP_MASK0) == ARM_VFP_CODE0)    \
 214          ||(((op) & ARM_SIMD_VFP_MASK0) == ARM_SIMD_VFP_CODE0)  \
 215          ||(((op) & ARM_SIMD_VFP_MASK1) == ARM_SIMD_VFP_CODE1)  \
 216          ||(((op) & ARM_SIMD_VFP_MASK2) == ARM_SIMD_VFP_CODE2)  \
 217          || (((op) & ARM_SIMD_VFP_MASK3) == ARM_SIMD_VFP_CODE3))
 218
 219 #define THUMB_SIMD_MASK0        0xEF000000
 220 #define THUMB_SIMD_CODE0        0xEF000000
 221
 222 #define THUMB_VFP_MASK0         0xEF000E10
 223 #define THUMB_VFP_CODE0         0xEE000A00
 224
 225 #define THUMB_SIMD_VFP_MASK0    0xEE000E00
 226 #define THUMB_SIMD_VFP_CODE0    0xEC000A00
 227 #define THUMB_SIMD_VFP_MASK1    0xFF100000
 228 #define THUMB_SIMD_VFP_CODE1    0xF9000000
 229 #define THUMB_SIMD_VFP_MASK2    0xEF000E10
 230 #define THUMB_SIMD_VFP_CODE2    0xEE000A10
 231 #define THUMB_SIMD_VFP_MASK3    0xEFE00E00
 232 #define THUMB_SIMD_VFP_CODE3    0xEC400A00
 233
 234 #define IS_THUMB_VFP(op)        (       \
 235         (((op) & THUMB_SIMD_MASK0) == THUMB_SIMD_CODE0 )        \
 236          || (((op) & THUMB_VFP_MASK0) == THUMB_VFP_CODE0 )      \
 237          || (((op) & THUMB_SIMD_VFP_MASK0) == THUMB_SIMD_VFP_CODE0 )    \
 238          || (((op) & THUMB_SIMD_VFP_MASK1) == THUMB_SIMD_VFP_CODE1 )    \
 239          || (((op) & THUMB_SIMD_VFP_MASK2) == THUMB_SIMD_VFP_CODE2 )    \
 240          || (((op) & THUMB_SIMD_VFP_MASK3) == THUMB_SIMD_VFP_CODE3))
 241
 242 extern boolean_t arm_swap_readable_type(vm_map_address_t, unsigned int /* spsr */);
 243 extern boolean_t arm_force_fast_fault(ppnum_t, vm_prot_t, int, void *);
 244 extern kern_return_t arm_fast_fault(pmap_t, vm_map_address_t, vm_prot_t, boolean_t);
 245
 246 /*
 247  * Determines if the aborted instruction is read or write operation
 248  */
 249 #define arm_fault_type(op,spsr,vaddr) \
 250        (((((op)&ARM_CDX_MASK) == ARM_STC) || \
 251          (((op)&ARM_STRH_MASK) == ARM_STRH) || \
 252          (((op)&ARM_BDX_MASK) == ARM_STM) || \
 253          (((op)&ARM_SDX_MASK) == ARM_STR) || \
 254          ((((op)&ARM_SWP_MASK) == ARM_SWP) && \
 255                 arm_swap_readable_type(vaddr,spsr))) ?  \
 256                         (VM_PROT_WRITE|VM_PROT_READ) : (VM_PROT_READ))
 257
 258 #define thumb_fault_type(op,spsr,vaddr) \
 259         (((((op)&THUMB_STR_1_MASK) == THUMB_STMIA) || \
 260           (((op)&THUMB_STR_1_MASK) == THUMB_STR_1) || \
 261           (((op)&THUMB_STR_2_MASK) == THUMB_STR_2) || \
 262           (((op)&THUMB_STR_3_MASK) == THUMB_STR_3) || \
 263           (((op)&THUMB_STR_1_MASK) == THUMB_STRB_1) || \
 264           (((op)&THUMB_STR_2_MASK) == THUMB_STRB_2) || \
 265           (((op)&THUMB_STR_1_MASK) == THUMB_STRH_1) || \
 266           (((op)&THUMB_STR_2_MASK) == THUMB_STRH_2) || \
 267           (((op)&THUMB_PUSH_MASK) == THUMB_PUSH)) ? \
 268                 (VM_PROT_WRITE|VM_PROT_READ) : (VM_PROT_READ))
 269
 270 typedef kern_return_t (*perfCallback)(
 271                                 int                     trapno,
 272                                 struct arm_saved_state  *ss,
 273                                 uintptr_t *,
 274                                       int);
 275
 276 #endif  /* !ASSEMBLER && MACH_KERNEL */
 277
 278 #endif  /* _ARM_TRAP_H_ */