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1 /*
2 * Copyright (c) 2000-2018 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /*
32 * Mach Operating System
33 * Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56 /*
57 */
58
59 /*
60 * Hardware trap/fault handler.
61 */
62
63 #include <mach_kdp.h>
64 #include <mach_ldebug.h>
65
66 #include <types.h>
67 #include <i386/eflags.h>
68 #include <i386/trap.h>
69 #include <i386/pmap.h>
70 #include <i386/fpu.h>
71 #include <i386/misc_protos.h> /* panic_io_port_read() */
72 #include <i386/lapic.h>
73
74 #include <mach/exception.h>
75 #include <mach/kern_return.h>
76 #include <mach/vm_param.h>
77 #include <mach/i386/thread_status.h>
78
79 #include <vm/vm_kern.h>
80 #include <vm/vm_fault.h>
81
82 #include <kern/kern_types.h>
83 #include <kern/processor.h>
84 #include <kern/thread.h>
85 #include <kern/task.h>
86 #include <kern/sched.h>
87 #include <kern/sched_prim.h>
88 #include <kern/exception.h>
89 #include <kern/spl.h>
90 #include <kern/misc_protos.h>
91 #include <kern/debug.h>
92 #if CONFIG_TELEMETRY
93 #include <kern/telemetry.h>
94 #endif
95 #include <sys/kdebug.h>
96 #include <prng/random.h>
97
98 #include <string.h>
99
100 #include <i386/postcode.h>
101 #include <i386/mp_desc.h>
102 #include <i386/proc_reg.h>
103 #if CONFIG_MCA
104 #include <i386/machine_check.h>
105 #endif
106 #include <mach/i386/syscall_sw.h>
107
108 #include <libkern/OSDebug.h>
109 #include <i386/cpu_threads.h>
110 #include <machine/pal_routines.h>
111
112 extern void throttle_lowpri_io(int);
113 extern void kprint_state(x86_saved_state64_t *saved_state);
114
115 /*
116 * Forward declarations
117 */
118 static void user_page_fault_continue(kern_return_t kret);
119 static void panic_trap(x86_saved_state64_t *saved_state, uint32_t pl, kern_return_t fault_result);
120 static void set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip);
121
122 #if CONFIG_DTRACE
123 /* See <rdar://problem/4613924> */
124 perfCallback tempDTraceTrapHook = NULL; /* Pointer to DTrace fbt trap hook routine */
125
126 extern boolean_t dtrace_tally_fault(user_addr_t);
127 #endif
128
129 extern boolean_t pmap_smep_enabled;
130 extern boolean_t pmap_smap_enabled;
131
132 __attribute__((noreturn))
133 void
134 thread_syscall_return(
135 kern_return_t ret)
136 {
137 thread_t thr_act = current_thread();
138 boolean_t is_mach;
139 int code;
140
141 pal_register_cache_state(thr_act, DIRTY);
142
143 if (thread_is_64bit(thr_act)) {
144 x86_saved_state64_t *regs;
145
146 regs = USER_REGS64(thr_act);
147
148 code = (int) (regs->rax & SYSCALL_NUMBER_MASK);
149 is_mach = (regs->rax & SYSCALL_CLASS_MASK)
150 == (SYSCALL_CLASS_MACH << SYSCALL_CLASS_SHIFT);
151 if (kdebug_enable && is_mach) {
152 /* Mach trap */
153 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
154 MACHDBG_CODE(DBG_MACH_EXCP_SC,code)|DBG_FUNC_END,
155 ret, 0, 0, 0, 0);
156 }
157 regs->rax = ret;
158 #if DEBUG
159 if (is_mach)
160 DEBUG_KPRINT_SYSCALL_MACH(
161 "thread_syscall_return: 64-bit mach ret=%u\n",
162 ret);
163 else
164 DEBUG_KPRINT_SYSCALL_UNIX(
165 "thread_syscall_return: 64-bit unix ret=%u\n",
166 ret);
167 #endif
168 } else {
169 x86_saved_state32_t *regs;
170
171 regs = USER_REGS32(thr_act);
172
173 code = ((int) regs->eax);
174 is_mach = (code < 0);
175 if (kdebug_enable && is_mach) {
176 /* Mach trap */
177 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
178 MACHDBG_CODE(DBG_MACH_EXCP_SC,-code)|DBG_FUNC_END,
179 ret, 0, 0, 0, 0);
180 }
181 regs->eax = ret;
182 #if DEBUG
183 if (is_mach)
184 DEBUG_KPRINT_SYSCALL_MACH(
185 "thread_syscall_return: 32-bit mach ret=%u\n",
186 ret);
187 else
188 DEBUG_KPRINT_SYSCALL_UNIX(
189 "thread_syscall_return: 32-bit unix ret=%u\n",
190 ret);
191 #endif
192 }
193
194 #if DEBUG || DEVELOPMENT
195 kern_allocation_name_t
196 prior __assert_only = thread_get_kernel_state(thr_act)->allocation_name;
197 assertf(prior == NULL, "thread_set_allocation_name(\"%s\") not cleared", kern_allocation_get_name(prior));
198 #endif /* DEBUG || DEVELOPMENT */
199
200 throttle_lowpri_io(1);
201
202 thread_exception_return();
203 /*NOTREACHED*/
204 }
205
206
207 static inline void
208 user_page_fault_continue(
209 kern_return_t kr)
210 {
211 thread_t thread = current_thread();
212 user_addr_t vaddr;
213
214 if (thread_is_64bit(thread)) {
215 x86_saved_state64_t *uregs;
216
217 uregs = USER_REGS64(thread);
218
219 vaddr = (user_addr_t)uregs->cr2;
220 } else {
221 x86_saved_state32_t *uregs;
222
223 uregs = USER_REGS32(thread);
224
225 vaddr = uregs->cr2;
226 }
227
228
229 /* PAL debug hook */
230 pal_dbg_page_fault( thread, vaddr, kr );
231
232 i386_exception(EXC_BAD_ACCESS, kr, vaddr);
233 /*NOTREACHED*/
234 }
235
236 /*
237 * Fault recovery in copyin/copyout routines.
238 */
239 struct recovery {
240 uintptr_t fault_addr;
241 uintptr_t recover_addr;
242 };
243
244 extern struct recovery recover_table[];
245 extern struct recovery recover_table_end[];
246
247 const char * trap_type[] = {TRAP_NAMES};
248 unsigned TRAP_TYPES = sizeof(trap_type)/sizeof(trap_type[0]);
249
250 extern void PE_incoming_interrupt(int interrupt);
251
252 #if defined(__x86_64__) && DEBUG
253 void
254 kprint_state(x86_saved_state64_t *saved_state)
255 {
256 kprintf("current_cpu_datap() 0x%lx\n", (uintptr_t)current_cpu_datap());
257 kprintf("Current GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_GS_BASE));
258 kprintf("Kernel GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_KERNEL_GS_BASE));
259 kprintf("state at 0x%lx:\n", (uintptr_t) saved_state);
260
261 kprintf(" rdi 0x%llx\n", saved_state->rdi);
262 kprintf(" rsi 0x%llx\n", saved_state->rsi);
263 kprintf(" rdx 0x%llx\n", saved_state->rdx);
264 kprintf(" r10 0x%llx\n", saved_state->r10);
265 kprintf(" r8 0x%llx\n", saved_state->r8);
266 kprintf(" r9 0x%llx\n", saved_state->r9);
267
268 kprintf(" cr2 0x%llx\n", saved_state->cr2);
269 kprintf("real cr2 0x%lx\n", get_cr2());
270 kprintf(" r15 0x%llx\n", saved_state->r15);
271 kprintf(" r14 0x%llx\n", saved_state->r14);
272 kprintf(" r13 0x%llx\n", saved_state->r13);
273 kprintf(" r12 0x%llx\n", saved_state->r12);
274 kprintf(" r11 0x%llx\n", saved_state->r11);
275 kprintf(" rbp 0x%llx\n", saved_state->rbp);
276 kprintf(" rbx 0x%llx\n", saved_state->rbx);
277 kprintf(" rcx 0x%llx\n", saved_state->rcx);
278 kprintf(" rax 0x%llx\n", saved_state->rax);
279
280 kprintf(" gs 0x%x\n", saved_state->gs);
281 kprintf(" fs 0x%x\n", saved_state->fs);
282
283 kprintf(" isf.trapno 0x%x\n", saved_state->isf.trapno);
284 kprintf(" isf._pad 0x%x\n", saved_state->isf._pad);
285 kprintf(" isf.trapfn 0x%llx\n", saved_state->isf.trapfn);
286 kprintf(" isf.err 0x%llx\n", saved_state->isf.err);
287 kprintf(" isf.rip 0x%llx\n", saved_state->isf.rip);
288 kprintf(" isf.cs 0x%llx\n", saved_state->isf.cs);
289 kprintf(" isf.rflags 0x%llx\n", saved_state->isf.rflags);
290 kprintf(" isf.rsp 0x%llx\n", saved_state->isf.rsp);
291 kprintf(" isf.ss 0x%llx\n", saved_state->isf.ss);
292 }
293 #endif
294
295
296 /*
297 * Non-zero indicates latency assert is enabled and capped at valued
298 * absolute time units.
299 */
300
301 uint64_t interrupt_latency_cap = 0;
302 boolean_t ilat_assert = FALSE;
303
304 void
305 interrupt_latency_tracker_setup(void) {
306 uint32_t ilat_cap_us;
307 if (PE_parse_boot_argn("interrupt_latency_cap_us", &ilat_cap_us, sizeof(ilat_cap_us))) {
308 interrupt_latency_cap = ilat_cap_us * NSEC_PER_USEC;
309 nanoseconds_to_absolutetime(interrupt_latency_cap, &interrupt_latency_cap);
310 } else {
311 interrupt_latency_cap = LockTimeOut;
312 }
313 PE_parse_boot_argn("-interrupt_latency_assert_enable", &ilat_assert, sizeof(ilat_assert));
314 }
315
316 void interrupt_reset_latency_stats(void) {
317 uint32_t i;
318 for (i = 0; i < real_ncpus; i++) {
319 cpu_data_ptr[i]->cpu_max_observed_int_latency =
320 cpu_data_ptr[i]->cpu_max_observed_int_latency_vector = 0;
321 }
322 }
323
324 void interrupt_populate_latency_stats(char *buf, unsigned bufsize) {
325 uint32_t i, tcpu = ~0;
326 uint64_t cur_max = 0;
327
328 for (i = 0; i < real_ncpus; i++) {
329 if (cur_max < cpu_data_ptr[i]->cpu_max_observed_int_latency) {
330 cur_max = cpu_data_ptr[i]->cpu_max_observed_int_latency;
331 tcpu = i;
332 }
333 }
334
335 if (tcpu < real_ncpus)
336 snprintf(buf, bufsize, "0x%x 0x%x 0x%llx", tcpu, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency_vector, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency);
337 }
338
339 uint32_t interrupt_timer_coalescing_enabled = 1;
340 uint64_t interrupt_coalesced_timers;
341
342 /*
343 * Handle interrupts:
344 * - local APIC interrupts (IPIs, timers, etc) are handled by the kernel,
345 * - device interrupts go to the platform expert.
346 */
347 void
348 interrupt(x86_saved_state_t *state)
349 {
350 uint64_t rip;
351 uint64_t rsp;
352 int interrupt_num;
353 boolean_t user_mode = FALSE;
354 int ipl;
355 int cnum = cpu_number();
356 cpu_data_t *cdp = cpu_data_ptr[cnum];
357 int itype = DBG_INTR_TYPE_UNKNOWN;
358
359 x86_saved_state64_t *state64 = saved_state64(state);
360 rip = state64->isf.rip;
361 rsp = state64->isf.rsp;
362 interrupt_num = state64->isf.trapno;
363 if(state64->isf.cs & 0x03)
364 user_mode = TRUE;
365
366 if (cpu_data_ptr[cnum]->lcpu.package->num_idle == topoParms.nLThreadsPerPackage)
367 cpu_data_ptr[cnum]->cpu_hwIntpexits[interrupt_num]++;
368
369 if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_INTERPROCESSOR_INTERRUPT))
370 itype = DBG_INTR_TYPE_IPI;
371 else if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_TIMER_INTERRUPT))
372 itype = DBG_INTR_TYPE_TIMER;
373 else
374 itype = DBG_INTR_TYPE_OTHER;
375
376 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
377 MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_START,
378 interrupt_num,
379 (user_mode ? rip : VM_KERNEL_UNSLIDE(rip)),
380 user_mode, itype, 0);
381
382 SCHED_STATS_INTERRUPT(current_processor());
383
384 #if CONFIG_TELEMETRY
385 if (telemetry_needs_record) {
386 telemetry_mark_curthread(user_mode);
387 }
388 #endif
389
390 ipl = get_preemption_level();
391
392 /*
393 * Handle local APIC interrupts
394 * else call platform expert for devices.
395 */
396 if (!lapic_interrupt(interrupt_num, state)) {
397 PE_incoming_interrupt(interrupt_num);
398 }
399
400 if (__improbable(get_preemption_level() != ipl)) {
401 panic("Preemption level altered by interrupt vector 0x%x: initial 0x%x, final: 0x%x\n", interrupt_num, ipl, get_preemption_level());
402 }
403
404
405 if (__improbable(cdp->cpu_nested_istack)) {
406 cdp->cpu_nested_istack_events++;
407 }
408 else {
409 uint64_t ctime = mach_absolute_time();
410 uint64_t int_latency = ctime - cdp->cpu_int_event_time;
411 uint64_t esdeadline, ehdeadline;
412 /* Attempt to process deferred timers in the context of
413 * this interrupt, unless interrupt time has already exceeded
414 * TCOAL_ILAT_THRESHOLD.
415 */
416 #define TCOAL_ILAT_THRESHOLD (30000ULL)
417
418 if ((int_latency < TCOAL_ILAT_THRESHOLD) &&
419 interrupt_timer_coalescing_enabled) {
420 esdeadline = cdp->rtclock_timer.queue.earliest_soft_deadline;
421 ehdeadline = cdp->rtclock_timer.deadline;
422 if ((ctime >= esdeadline) && (ctime < ehdeadline)) {
423 interrupt_coalesced_timers++;
424 TCOAL_DEBUG(0x88880000 | DBG_FUNC_START, ctime, esdeadline, ehdeadline, interrupt_coalesced_timers, 0);
425 rtclock_intr(state);
426 TCOAL_DEBUG(0x88880000 | DBG_FUNC_END, ctime, esdeadline, interrupt_coalesced_timers, 0, 0);
427 } else {
428 TCOAL_DEBUG(0x77770000, ctime, cdp->rtclock_timer.queue.earliest_soft_deadline, cdp->rtclock_timer.deadline, interrupt_coalesced_timers, 0);
429 }
430 }
431
432 if (__improbable(ilat_assert && (int_latency > interrupt_latency_cap) && !machine_timeout_suspended())) {
433 panic("Interrupt vector 0x%x exceeded interrupt latency threshold, 0x%llx absolute time delta, prior signals: 0x%x, current signals: 0x%x", interrupt_num, int_latency, cdp->cpu_prior_signals, cdp->cpu_signals);
434 }
435
436 if (__improbable(int_latency > cdp->cpu_max_observed_int_latency)) {
437 cdp->cpu_max_observed_int_latency = int_latency;
438 cdp->cpu_max_observed_int_latency_vector = interrupt_num;
439 }
440 }
441
442 /*
443 * Having serviced the interrupt first, look at the interrupted stack depth.
444 */
445 if (!user_mode) {
446 uint64_t depth = cdp->cpu_kernel_stack
447 + sizeof(struct thread_kernel_state)
448 + sizeof(struct i386_exception_link *)
449 - rsp;
450 if (__improbable(depth > kernel_stack_depth_max)) {
451 kernel_stack_depth_max = (vm_offset_t)depth;
452 KERNEL_DEBUG_CONSTANT(
453 MACHDBG_CODE(DBG_MACH_SCHED, MACH_STACK_DEPTH),
454 (long) depth, (long) VM_KERNEL_UNSLIDE(rip), 0, 0, 0);
455 }
456 }
457
458 if (cnum == master_cpu)
459 ml_entropy_collect();
460
461 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
462 MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_END,
463 interrupt_num, 0, 0, 0, 0);
464
465 assert(ml_get_interrupts_enabled() == FALSE);
466 }
467
468 static inline void
469 reset_dr7(void)
470 {
471 long dr7 = 0x400; /* magic dr7 reset value; 32 bit on i386, 64 bit on x86_64 */
472 __asm__ volatile("mov %0,%%dr7" : : "r" (dr7));
473 }
474 #if MACH_KDP
475 unsigned kdp_has_active_watchpoints = 0;
476 #define NO_WATCHPOINTS (!kdp_has_active_watchpoints)
477 #else
478 #define NO_WATCHPOINTS 1
479 #endif
480 /*
481 * Trap from kernel mode. Only page-fault errors are recoverable,
482 * and then only in special circumstances. All other errors are
483 * fatal. Return value indicates if trap was handled.
484 */
485
486 void
487 kernel_trap(
488 x86_saved_state_t *state,
489 uintptr_t *lo_spp)
490 {
491 x86_saved_state64_t *saved_state;
492 int code;
493 user_addr_t vaddr;
494 int type;
495 vm_map_t map = 0; /* protected by T_PAGE_FAULT */
496 kern_return_t result = KERN_FAILURE;
497 kern_return_t fault_result = KERN_SUCCESS;
498 thread_t thread;
499 boolean_t intr;
500 vm_prot_t prot;
501 struct recovery *rp;
502 vm_offset_t kern_ip;
503 #if NCOPY_WINDOWS > 0
504 int fault_in_copy_window = -1;
505 #endif
506 int is_user;
507 int trap_pl = get_preemption_level();
508
509 thread = current_thread();
510
511 if (__improbable(is_saved_state32(state)))
512 panic("kernel_trap(%p) with 32-bit state", state);
513 saved_state = saved_state64(state);
514
515 /* Record cpu where state was captured */
516 saved_state->isf.cpu = cpu_number();
517
518 vaddr = (user_addr_t)saved_state->cr2;
519 type = saved_state->isf.trapno;
520 code = (int)(saved_state->isf.err & 0xffff);
521 intr = (saved_state->isf.rflags & EFL_IF) != 0; /* state of ints at trap */
522 kern_ip = (vm_offset_t)saved_state->isf.rip;
523
524 is_user = (vaddr < VM_MAX_USER_PAGE_ADDRESS);
525
526 #if CONFIG_DTRACE
527 /*
528 * Is there a DTrace hook?
529 */
530 if (__improbable(tempDTraceTrapHook != NULL)) {
531 if (tempDTraceTrapHook(type, state, lo_spp, 0) == KERN_SUCCESS) {
532 /*
533 * If it succeeds, we are done...
534 */
535 return;
536 }
537 }
538 #endif /* CONFIG_DTRACE */
539
540 /*
541 * we come here with interrupts off as we don't want to recurse
542 * on preemption below. but we do want to re-enable interrupts
543 * as soon we possibly can to hold latency down
544 */
545 if (__improbable(T_PREEMPT == type)) {
546 ast_taken_kernel();
547
548 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
549 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
550 0, 0, 0, VM_KERNEL_UNSLIDE(kern_ip), 0);
551 return;
552 }
553
554 user_addr_t kd_vaddr = is_user ? vaddr : VM_KERNEL_UNSLIDE(vaddr);
555 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
556 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
557 (unsigned)(kd_vaddr >> 32), (unsigned)kd_vaddr, is_user,
558 VM_KERNEL_UNSLIDE(kern_ip), 0);
559
560
561 if (T_PAGE_FAULT == type) {
562 /*
563 * assume we're faulting in the kernel map
564 */
565 map = kernel_map;
566
567 if (__probable(thread != THREAD_NULL && thread->map != kernel_map)) {
568 #if NCOPY_WINDOWS > 0
569 vm_offset_t copy_window_base;
570 vm_offset_t kvaddr;
571 int window_index;
572
573 kvaddr = (vm_offset_t)vaddr;
574 /*
575 * must determine if fault occurred in
576 * the copy window while pre-emption is
577 * disabled for this processor so that
578 * we only need to look at the window
579 * associated with this processor
580 */
581 copy_window_base = current_cpu_datap()->cpu_copywindow_base;
582
583 if (kvaddr >= copy_window_base && kvaddr < (copy_window_base + (NBPDE * NCOPY_WINDOWS)) ) {
584
585 window_index = (int)((kvaddr - copy_window_base) / NBPDE);
586
587 if (thread->machine.copy_window[window_index].user_base != (user_addr_t)-1) {
588
589 kvaddr -= (copy_window_base + (NBPDE * window_index));
590 vaddr = thread->machine.copy_window[window_index].user_base + kvaddr;
591
592 map = thread->map;
593 fault_in_copy_window = window_index;
594 }
595 }
596 #else
597 if (__probable(vaddr < VM_MAX_USER_PAGE_ADDRESS)) {
598 /* fault occurred in userspace */
599 map = thread->map;
600
601 /* Intercept a potential Supervisor Mode Execute
602 * Protection fault. These criteria identify
603 * both NX faults and SMEP faults, but both
604 * are fatal. We avoid checking PTEs (racy).
605 * (The VM could just redrive a SMEP fault, hence
606 * the intercept).
607 */
608 if (__improbable((code == (T_PF_PROT | T_PF_EXECUTE)) &&
609 (pmap_smep_enabled) && (saved_state->isf.rip == vaddr))) {
610 goto debugger_entry;
611 }
612
613 /*
614 * Additionally check for SMAP faults...
615 * which are characterized by page-present and
616 * the AC bit unset (i.e. not from copyin/out path).
617 */
618 if (__improbable(code & T_PF_PROT &&
619 pmap_smap_enabled &&
620 (saved_state->isf.rflags & EFL_AC) == 0)) {
621 goto debugger_entry;
622 }
623
624 /*
625 * If we're not sharing cr3 with the user
626 * and we faulted in copyio,
627 * then switch cr3 here and dismiss the fault.
628 */
629 if (no_shared_cr3 &&
630 (thread->machine.specFlags&CopyIOActive) &&
631 map->pmap->pm_cr3 != get_cr3_base()) {
632 pmap_assert(current_cpu_datap()->cpu_pmap_pcid_enabled == FALSE);
633 set_cr3_raw(map->pmap->pm_cr3);
634 return;
635 }
636 if (__improbable(vaddr < PAGE_SIZE) &&
637 ((thread->machine.specFlags & CopyIOActive) == 0)) {
638 goto debugger_entry;
639 }
640 }
641 #endif
642 }
643 }
644
645 (void) ml_set_interrupts_enabled(intr);
646
647 switch (type) {
648
649 case T_NO_FPU:
650 fpnoextflt();
651 return;
652
653 case T_FPU_FAULT:
654 fpextovrflt();
655 return;
656
657 case T_FLOATING_POINT_ERROR:
658 fpexterrflt();
659 return;
660
661 case T_SSE_FLOAT_ERROR:
662 fpSSEexterrflt();
663 return;
664
665 case T_INVALID_OPCODE:
666 fpUDflt(kern_ip);
667 goto debugger_entry;
668
669 case T_DEBUG:
670 if ((saved_state->isf.rflags & EFL_TF) == 0 && NO_WATCHPOINTS)
671 {
672 /* We've somehow encountered a debug
673 * register match that does not belong
674 * to the kernel debugger.
675 * This isn't supposed to happen.
676 */
677 reset_dr7();
678 return;
679 }
680 goto debugger_entry;
681 case T_INT3:
682 goto debugger_entry;
683 case T_PAGE_FAULT:
684
685 #if CONFIG_DTRACE
686 if (thread != THREAD_NULL && thread->options & TH_OPT_DTRACE) { /* Executing under dtrace_probe? */
687 if (dtrace_tally_fault(vaddr)) { /* Should a fault under dtrace be ignored? */
688 /*
689 * DTrace has "anticipated" the possibility of this fault, and has
690 * established the suitable recovery state. Drop down now into the
691 * recovery handling code in "case T_GENERAL_PROTECTION:".
692 */
693 goto FALL_THROUGH;
694 }
695 }
696 #endif /* CONFIG_DTRACE */
697
698 prot = VM_PROT_READ;
699
700 if (code & T_PF_WRITE)
701 prot |= VM_PROT_WRITE;
702 if (code & T_PF_EXECUTE)
703 prot |= VM_PROT_EXECUTE;
704
705 fault_result = result = vm_fault(map,
706 vaddr,
707 prot,
708 FALSE, VM_KERN_MEMORY_NONE,
709 THREAD_UNINT, NULL, 0);
710
711 if (result == KERN_SUCCESS) {
712 #if NCOPY_WINDOWS > 0
713 if (fault_in_copy_window != -1) {
714 ml_set_interrupts_enabled(FALSE);
715 copy_window_fault(thread, map,
716 fault_in_copy_window);
717 (void) ml_set_interrupts_enabled(intr);
718 }
719 #endif /* NCOPY_WINDOWS > 0 */
720 return;
721 }
722 /*
723 * fall through
724 */
725 #if CONFIG_DTRACE
726 FALL_THROUGH:
727 #endif /* CONFIG_DTRACE */
728
729 case T_GENERAL_PROTECTION:
730 /*
731 * If there is a failure recovery address
732 * for this fault, go there.
733 */
734 for (rp = recover_table; rp < recover_table_end; rp++) {
735 if (kern_ip == rp->fault_addr) {
736 set_recovery_ip(saved_state, rp->recover_addr);
737 return;
738 }
739 }
740
741 /*
742 * Check thread recovery address also.
743 */
744 if (thread != THREAD_NULL && thread->recover) {
745 set_recovery_ip(saved_state, thread->recover);
746 thread->recover = 0;
747 return;
748 }
749 /*
750 * Unanticipated page-fault errors in kernel
751 * should not happen.
752 *
753 * fall through...
754 */
755 default:
756 /*
757 * Exception 15 is reserved but some chips may generate it
758 * spuriously. Seen at startup on AMD Athlon-64.
759 */
760 if (type == 15) {
761 kprintf("kernel_trap() ignoring spurious trap 15\n");
762 return;
763 }
764 debugger_entry:
765 /* Ensure that the i386_kernel_state at the base of the
766 * current thread's stack (if any) is synchronized with the
767 * context at the moment of the trap, to facilitate
768 * access through the debugger.
769 */
770 sync_iss_to_iks(state);
771 #if MACH_KDP
772 if (kdp_i386_trap(type, saved_state, result, (vm_offset_t)vaddr))
773 return;
774 #endif
775 }
776 pal_cli();
777 panic_trap(saved_state, trap_pl, fault_result);
778 /*
779 * NO RETURN
780 */
781 }
782
783 static void
784 set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip)
785 {
786 saved_state->isf.rip = ip;
787 }
788
789 static void
790 panic_trap(x86_saved_state64_t *regs, uint32_t pl, kern_return_t fault_result)
791 {
792 const char *trapname = "Unknown";
793 pal_cr_t cr0, cr2, cr3, cr4;
794 boolean_t potential_smep_fault = FALSE, potential_kernel_NX_fault = FALSE;
795 boolean_t potential_smap_fault = FALSE;
796
797 pal_get_control_registers( &cr0, &cr2, &cr3, &cr4 );
798 assert(ml_get_interrupts_enabled() == FALSE);
799 current_cpu_datap()->cpu_fatal_trap_state = regs;
800 /*
801 * Issue an I/O port read if one has been requested - this is an
802 * event logic analyzers can use as a trigger point.
803 */
804 panic_io_port_read();
805
806 kprintf("CPU %d panic trap number 0x%x, rip 0x%016llx\n",
807 cpu_number(), regs->isf.trapno, regs->isf.rip);
808 kprintf("cr0 0x%016llx cr2 0x%016llx cr3 0x%016llx cr4 0x%016llx\n",
809 cr0, cr2, cr3, cr4);
810
811 if (regs->isf.trapno < TRAP_TYPES)
812 trapname = trap_type[regs->isf.trapno];
813
814 if ((regs->isf.trapno == T_PAGE_FAULT) && (regs->isf.err == (T_PF_PROT | T_PF_EXECUTE)) && (regs->isf.rip == regs->cr2)) {
815 if (pmap_smep_enabled && (regs->isf.rip < VM_MAX_USER_PAGE_ADDRESS)) {
816 potential_smep_fault = TRUE;
817 } else if (regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
818 potential_kernel_NX_fault = TRUE;
819 }
820 } else if (pmap_smap_enabled &&
821 regs->isf.trapno == T_PAGE_FAULT &&
822 regs->isf.err & T_PF_PROT &&
823 regs->cr2 < VM_MAX_USER_PAGE_ADDRESS &&
824 regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
825 potential_smap_fault = TRUE;
826 }
827
828 #undef panic
829 panic("Kernel trap at 0x%016llx, type %d=%s, registers:\n"
830 "CR0: 0x%016llx, CR2: 0x%016llx, CR3: 0x%016llx, CR4: 0x%016llx\n"
831 "RAX: 0x%016llx, RBX: 0x%016llx, RCX: 0x%016llx, RDX: 0x%016llx\n"
832 "RSP: 0x%016llx, RBP: 0x%016llx, RSI: 0x%016llx, RDI: 0x%016llx\n"
833 "R8: 0x%016llx, R9: 0x%016llx, R10: 0x%016llx, R11: 0x%016llx\n"
834 "R12: 0x%016llx, R13: 0x%016llx, R14: 0x%016llx, R15: 0x%016llx\n"
835 "RFL: 0x%016llx, RIP: 0x%016llx, CS: 0x%016llx, SS: 0x%016llx\n"
836 "Fault CR2: 0x%016llx, Error code: 0x%016llx, Fault CPU: 0x%x%s%s%s%s, PL: %d, VF: %d\n",
837 regs->isf.rip, regs->isf.trapno, trapname,
838 cr0, cr2, cr3, cr4,
839 regs->rax, regs->rbx, regs->rcx, regs->rdx,
840 regs->isf.rsp, regs->rbp, regs->rsi, regs->rdi,
841 regs->r8, regs->r9, regs->r10, regs->r11,
842 regs->r12, regs->r13, regs->r14, regs->r15,
843 regs->isf.rflags, regs->isf.rip, regs->isf.cs & 0xFFFF,
844 regs->isf.ss & 0xFFFF,regs->cr2, regs->isf.err, regs->isf.cpu,
845 virtualized ? " VMM" : "",
846 potential_kernel_NX_fault ? " Kernel NX fault" : "",
847 potential_smep_fault ? " SMEP/User NX fault" : "",
848 potential_smap_fault ? " SMAP fault" : "",
849 pl,
850 fault_result);
851 /*
852 * This next statement is not executed,
853 * but it's needed to stop the compiler using tail call optimization
854 * for the panic call - which confuses the subsequent backtrace.
855 */
856 cr0 = 0;
857 }
858
859 #if CONFIG_DTRACE
860 extern kern_return_t dtrace_user_probe(x86_saved_state_t *);
861 #endif
862
863 #if DEBUG
864 uint32_t fsigs[2];
865 uint32_t fsigns, fsigcs;
866 #endif
867
868 /*
869 * Trap from user mode.
870 */
871 void
872 user_trap(
873 x86_saved_state_t *saved_state)
874 {
875 int exc;
876 int err;
877 mach_exception_code_t code;
878 mach_exception_subcode_t subcode;
879 int type;
880 user_addr_t vaddr;
881 vm_prot_t prot;
882 thread_t thread = current_thread();
883 kern_return_t kret;
884 user_addr_t rip;
885 unsigned long dr6 = 0; /* 32 bit for i386, 64 bit for x86_64 */
886
887 assert((is_saved_state32(saved_state) && !thread_is_64bit(thread)) ||
888 (is_saved_state64(saved_state) && thread_is_64bit(thread)));
889
890 if (is_saved_state64(saved_state)) {
891 x86_saved_state64_t *regs;
892
893 regs = saved_state64(saved_state);
894
895 /* Record cpu where state was captured */
896 regs->isf.cpu = cpu_number();
897
898 type = regs->isf.trapno;
899 err = (int)regs->isf.err & 0xffff;
900 vaddr = (user_addr_t)regs->cr2;
901 rip = (user_addr_t)regs->isf.rip;
902 } else {
903 x86_saved_state32_t *regs;
904
905 regs = saved_state32(saved_state);
906
907 /* Record cpu where state was captured */
908 regs->cpu = cpu_number();
909
910 type = regs->trapno;
911 err = regs->err & 0xffff;
912 vaddr = (user_addr_t)regs->cr2;
913 rip = (user_addr_t)regs->eip;
914 }
915
916 if ((type == T_DEBUG) && thread->machine.ids) {
917 unsigned long clear = 0;
918 /* Stash and clear this processor's DR6 value, in the event
919 * this was a debug register match
920 */
921 __asm__ volatile ("mov %%db6, %0" : "=r" (dr6));
922 __asm__ volatile ("mov %0, %%db6" : : "r" (clear));
923 }
924
925 pal_sti();
926
927 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
928 (MACHDBG_CODE(DBG_MACH_EXCP_UTRAP_x86, type)) | DBG_FUNC_NONE,
929 (unsigned)(vaddr>>32), (unsigned)vaddr,
930 (unsigned)(rip>>32), (unsigned)rip, 0);
931
932 code = 0;
933 subcode = 0;
934 exc = 0;
935
936 #if CONFIG_DTRACE
937 /*
938 * DTrace does not consume all user traps, only INT_3's for now.
939 * Avoid needlessly calling tempDTraceTrapHook here, and let the
940 * INT_3 case handle them.
941 */
942 #endif
943
944 DEBUG_KPRINT_SYSCALL_MASK(1,
945 "user_trap: type=0x%x(%s) err=0x%x cr2=%p rip=%p\n",
946 type, trap_type[type], err, (void *)(long) vaddr, (void *)(long) rip);
947
948 switch (type) {
949
950 case T_DIVIDE_ERROR:
951 exc = EXC_ARITHMETIC;
952 code = EXC_I386_DIV;
953 break;
954
955 case T_DEBUG:
956 {
957 pcb_t pcb;
958 /*
959 * Update the PCB with this processor's DR6 value
960 * in the event this was a debug register match.
961 */
962 pcb = THREAD_TO_PCB(thread);
963 if (pcb->ids) {
964 /*
965 * We can get and set the status register
966 * in 32-bit mode even on a 64-bit thread
967 * because the high order bits are not
968 * used on x86_64
969 */
970 if (thread_is_64bit(thread)) {
971 x86_debug_state64_t *ids = pcb->ids;
972 ids->dr6 = dr6;
973 } else { /* 32 bit thread */
974 x86_debug_state32_t *ids = pcb->ids;
975 ids->dr6 = (uint32_t) dr6;
976 }
977 }
978 exc = EXC_BREAKPOINT;
979 code = EXC_I386_SGL;
980 break;
981 }
982 case T_INT3:
983 #if CONFIG_DTRACE
984 if (dtrace_user_probe(saved_state) == KERN_SUCCESS)
985 return; /* If it succeeds, we are done... */
986 #endif
987 exc = EXC_BREAKPOINT;
988 code = EXC_I386_BPT;
989 break;
990
991 case T_OVERFLOW:
992 exc = EXC_ARITHMETIC;
993 code = EXC_I386_INTO;
994 break;
995
996 case T_OUT_OF_BOUNDS:
997 exc = EXC_SOFTWARE;
998 code = EXC_I386_BOUND;
999 break;
1000
1001 case T_INVALID_OPCODE:
1002 #if !defined(RC_HIDE_XNU_J137)
1003 fpUDflt(rip); /* May return from exception directly */
1004 #endif
1005 exc = EXC_BAD_INSTRUCTION;
1006 code = EXC_I386_INVOP;
1007 break;
1008
1009 case T_NO_FPU:
1010 fpnoextflt();
1011 return;
1012
1013 case T_FPU_FAULT:
1014 fpextovrflt(); /* Propagates exception directly, doesn't return */
1015 return;
1016
1017 case T_INVALID_TSS: /* invalid TSS == iret with NT flag set */
1018 exc = EXC_BAD_INSTRUCTION;
1019 code = EXC_I386_INVTSSFLT;
1020 subcode = err;
1021 break;
1022
1023 case T_SEGMENT_NOT_PRESENT:
1024 exc = EXC_BAD_INSTRUCTION;
1025 code = EXC_I386_SEGNPFLT;
1026 subcode = err;
1027 break;
1028
1029 case T_STACK_FAULT:
1030 exc = EXC_BAD_INSTRUCTION;
1031 code = EXC_I386_STKFLT;
1032 subcode = err;
1033 break;
1034
1035 case T_GENERAL_PROTECTION:
1036 /*
1037 * There's a wide range of circumstances which generate this
1038 * class of exception. From user-space, many involve bad
1039 * addresses (such as a non-canonical 64-bit address).
1040 * So we map this to EXC_BAD_ACCESS (and thereby SIGSEGV).
1041 * The trouble is cr2 doesn't contain the faulting address;
1042 * we'd need to decode the faulting instruction to really
1043 * determine this. We'll leave that to debuggers.
1044 * However, attempted execution of privileged instructions
1045 * (e.g. cli) also generate GP faults and so we map these to
1046 * to EXC_BAD_ACCESS (and thence SIGSEGV) also - rather than
1047 * EXC_BAD_INSTRUCTION which is more accurate. We just can't
1048 * win!
1049 */
1050 exc = EXC_BAD_ACCESS;
1051 code = EXC_I386_GPFLT;
1052 subcode = err;
1053 break;
1054
1055 case T_PAGE_FAULT:
1056 {
1057 prot = VM_PROT_READ;
1058
1059 if (err & T_PF_WRITE)
1060 prot |= VM_PROT_WRITE;
1061 if (__improbable(err & T_PF_EXECUTE))
1062 prot |= VM_PROT_EXECUTE;
1063 #if DEVELOPMENT || DEBUG
1064 uint32_t fsig = 0;
1065 fsig = thread_fpsimd_hash(thread);
1066 #if DEBUG
1067 fsigs[0] = fsig;
1068 #endif
1069 #endif
1070 kret = vm_fault(thread->map,
1071 vaddr,
1072 prot, FALSE, VM_KERN_MEMORY_NONE,
1073 THREAD_ABORTSAFE, NULL, 0);
1074 #if DEVELOPMENT || DEBUG
1075 if (fsig) {
1076 uint32_t fsig2 = thread_fpsimd_hash(thread);
1077 #if DEBUG
1078 fsigcs++;
1079 fsigs[1] = fsig2;
1080 #endif
1081 if (fsig != fsig2) {
1082 panic("FP/SIMD state hash mismatch across fault thread: %p 0x%x->0x%x", thread, fsig, fsig2);
1083 }
1084 } else {
1085 #if DEBUG
1086 fsigns++;
1087 #endif
1088 }
1089 #endif
1090 if (__probable((kret == KERN_SUCCESS) || (kret == KERN_ABORTED))) {
1091 thread_exception_return();
1092 /*NOTREACHED*/
1093 }
1094
1095 user_page_fault_continue(kret);
1096 } /* NOTREACHED */
1097 break;
1098
1099 case T_SSE_FLOAT_ERROR:
1100 fpSSEexterrflt(); /* Propagates exception directly, doesn't return */
1101 return;
1102
1103
1104 case T_FLOATING_POINT_ERROR:
1105 fpexterrflt(); /* Propagates exception directly, doesn't return */
1106 return;
1107
1108 case T_DTRACE_RET:
1109 #if CONFIG_DTRACE
1110 if (dtrace_user_probe(saved_state) == KERN_SUCCESS)
1111 return; /* If it succeeds, we are done... */
1112 #endif
1113 /*
1114 * If we get an INT 0x7f when we do not expect to,
1115 * treat it as an illegal instruction
1116 */
1117 exc = EXC_BAD_INSTRUCTION;
1118 code = EXC_I386_INVOP;
1119 break;
1120
1121 default:
1122 panic("Unexpected user trap, type %d", type);
1123 return;
1124 }
1125 /* Note: Codepaths that directly return from user_trap() have pending
1126 * ASTs processed in locore
1127 */
1128 i386_exception(exc, code, subcode);
1129 /* NOTREACHED */
1130 }
1131
1132 /*
1133 * Handle exceptions for i386.
1134 *
1135 * If we are an AT bus machine, we must turn off the AST for a
1136 * delayed floating-point exception.
1137 *
1138 * If we are providing floating-point emulation, we may have
1139 * to retrieve the real register values from the floating point
1140 * emulator.
1141 */
1142 void
1143 i386_exception(
1144 int exc,
1145 mach_exception_code_t code,
1146 mach_exception_subcode_t subcode)
1147 {
1148 mach_exception_data_type_t codes[EXCEPTION_CODE_MAX];
1149
1150 DEBUG_KPRINT_SYSCALL_MACH("i386_exception: exc=%d code=0x%llx subcode=0x%llx\n",
1151 exc, code, subcode);
1152 codes[0] = code; /* new exception interface */
1153 codes[1] = subcode;
1154 exception_triage(exc, codes, 2);
1155 /*NOTREACHED*/
1156 }
1157
1158
1159 /* Synchronize a thread's x86_kernel_state (if any) with the given
1160 * x86_saved_state_t obtained from the trap/IPI handler; called in
1161 * kernel_trap() prior to entering the debugger, and when receiving
1162 * an "MP_KDP" IPI. Called with null saved_state if an incoming IPI
1163 * was detected from the kernel while spinning with interrupts masked.
1164 */
1165
1166 void
1167 sync_iss_to_iks(x86_saved_state_t *saved_state)
1168 {
1169 struct x86_kernel_state *iks = NULL;
1170 vm_offset_t kstack;
1171 boolean_t record_active_regs = FALSE;
1172
1173 /* The PAL may have a special way to sync registers */
1174 if (saved_state && saved_state->flavor == THREAD_STATE_NONE)
1175 pal_get_kern_regs( saved_state );
1176
1177 if (current_thread() != NULL &&
1178 (kstack = current_thread()->kernel_stack) != 0) {
1179 x86_saved_state64_t *regs = saved_state64(saved_state);
1180
1181 iks = STACK_IKS(kstack);
1182
1183 /* Did we take the trap/interrupt in kernel mode? */
1184 if (saved_state == NULL || /* NULL => polling in kernel */
1185 regs == USER_REGS64(current_thread()))
1186 record_active_regs = TRUE;
1187 else {
1188 iks->k_rbx = regs->rbx;
1189 iks->k_rsp = regs->isf.rsp;
1190 iks->k_rbp = regs->rbp;
1191 iks->k_r12 = regs->r12;
1192 iks->k_r13 = regs->r13;
1193 iks->k_r14 = regs->r14;
1194 iks->k_r15 = regs->r15;
1195 iks->k_rip = regs->isf.rip;
1196 }
1197 }
1198
1199 if (record_active_regs == TRUE) {
1200 /* Show the trap handler path */
1201 __asm__ volatile("movq %%rbx, %0" : "=m" (iks->k_rbx));
1202 __asm__ volatile("movq %%rsp, %0" : "=m" (iks->k_rsp));
1203 __asm__ volatile("movq %%rbp, %0" : "=m" (iks->k_rbp));
1204 __asm__ volatile("movq %%r12, %0" : "=m" (iks->k_r12));
1205 __asm__ volatile("movq %%r13, %0" : "=m" (iks->k_r13));
1206 __asm__ volatile("movq %%r14, %0" : "=m" (iks->k_r14));
1207 __asm__ volatile("movq %%r15, %0" : "=m" (iks->k_r15));
1208 /* "Current" instruction pointer */
1209 __asm__ volatile("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:"
1210 : "=m" (iks->k_rip)
1211 :
1212 : "rax");
1213 }
1214 }
1215
1216 /*
1217 * This is used by the NMI interrupt handler (from mp.c) to
1218 * uncondtionally sync the trap handler context to the IKS
1219 * irrespective of whether the NMI was fielded in kernel
1220 * or user space.
1221 */
1222 void
1223 sync_iss_to_iks_unconditionally(__unused x86_saved_state_t *saved_state) {
1224 struct x86_kernel_state *iks;
1225 vm_offset_t kstack;
1226
1227 if ((kstack = current_thread()->kernel_stack) != 0) {
1228 iks = STACK_IKS(kstack);
1229 /* Display the trap handler path */
1230 __asm__ volatile("movq %%rbx, %0" : "=m" (iks->k_rbx));
1231 __asm__ volatile("movq %%rsp, %0" : "=m" (iks->k_rsp));
1232 __asm__ volatile("movq %%rbp, %0" : "=m" (iks->k_rbp));
1233 __asm__ volatile("movq %%r12, %0" : "=m" (iks->k_r12));
1234 __asm__ volatile("movq %%r13, %0" : "=m" (iks->k_r13));
1235 __asm__ volatile("movq %%r14, %0" : "=m" (iks->k_r14));
1236 __asm__ volatile("movq %%r15, %0" : "=m" (iks->k_r15));
1237 /* "Current" instruction pointer */
1238 __asm__ volatile("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:" : "=m" (iks->k_rip)::"rax");
1239 }
1240 }
1241
1242 #if DEBUG
1243 #define TERI 1
1244 #endif
1245
1246 #if TERI
1247 extern void thread_exception_return_internal(void) __dead2;
1248
1249 void thread_exception_return(void) {
1250 thread_t thread = current_thread();
1251 ml_set_interrupts_enabled(FALSE);
1252 if (thread_is_64bit(thread) != task_has_64BitAddr(thread->task)) {
1253 panic("Task/thread bitness mismatch %p %p, task: %d, thread: %d", thread, thread->task, thread_is_64bit(thread), task_has_64BitAddr(thread->task));
1254 }
1255
1256 if (thread_is_64bit(thread)) {
1257 if ((gdt_desc_p(USER64_CS)->access & ACC_PL_U) == 0) {
1258 panic("64-GDT mismatch %p, descriptor: %p", thread, gdt_desc_p(USER64_CS));
1259 }
1260 } else {
1261 if ((gdt_desc_p(USER_CS)->access & ACC_PL_U) == 0) {
1262 panic("32-GDT mismatch %p, descriptor: %p", thread, gdt_desc_p(USER_CS));
1263
1264 }
1265 }
1266 thread_exception_return_internal();
1267 }
1268 #endif
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