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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_COPYRIGHT@
24 */
25
26 /* Miscellaneous constants and structures used by the exception
27 * handlers
28 */
29
30 #ifndef _PPC_EXCEPTION_H_
31 #define _PPC_EXCEPTION_H_
32
33 #include <ppc/savearea.h>
34
35 #ifndef ASSEMBLER
36
37 #include <cpus.h>
38 #include <mach_kdb.h>
39 #include <mach_kdp.h>
40
41 #include <mach/machine/vm_types.h>
42 #include <mach/boolean.h>
43 #include <kern/cpu_data.h>
44 #include <pexpert/pexpert.h>
45 #include <IOKit/IOInterrupts.h>
46 #include <ppc/machine_routines.h>
47
48 /* Per processor CPU features */
49 #pragma pack(4) /* Make sure the structure stays as we defined it */
50 struct procFeatures {
51 unsigned int Available; /* 0x000 */
52 #define pfFloat 0x80000000
53 #define pfFloatb 0
54 #define pfAltivec 0x40000000
55 #define pfAltivecb 1
56 #define pfAvJava 0x20000000
57 #define pfAvJavab 2
58 #define pfSMPcap 0x10000000
59 #define pfSMPcapb 3
60 #define pfCanSleep 0x08000000
61 #define pfCanSleepb 4
62 #define pfCanNap 0x04000000
63 #define pfCanNapb 5
64 #define pfCanDoze 0x02000000
65 #define pfCanDozeb 6
66 #define pfSlowNap 0x00400000
67 #define pfSlowNapb 9
68 #define pfNoMuMMCK 0x00200000
69 #define pfNoMuMMCKb 10
70 #define pfNoL2PFNap 0x00100000
71 #define pfNoL2PFNapb 11
72 #define pfSCOMFixUp 0x00080000
73 #define pfSCOMFixUpb 12
74 #define pfHasDcba 0x00040000
75 #define pfHasDcbab 13
76 #define pfL1fa 0x00010000
77 #define pfL1fab 15
78 #define pfL2 0x00008000
79 #define pfL2b 16
80 #define pfL2fa 0x00004000
81 #define pfL2fab 17
82 #define pfL2i 0x00002000
83 #define pfL2ib 18
84 #define pfLClck 0x00001000
85 #define pfLClckb 19
86 #define pfWillNap 0x00000800
87 #define pfWillNapb 20
88 #define pfNoMSRir 0x00000400
89 #define pfNoMSRirb 21
90 #define pfL3pdet 0x00000200
91 #define pfL3pdetb 22
92 #define pf128Byte 0x00000080
93 #define pf128Byteb 24
94 #define pf32Byte 0x00000020
95 #define pf32Byteb 26
96 #define pf64Bit 0x00000010
97 #define pf64Bitb 27
98 #define pfL3 0x00000004
99 #define pfL3b 29
100 #define pfL3fa 0x00000002
101 #define pfL3fab 30
102 #define pfValid 0x00000001
103 #define pfValidb 31
104 unsigned short rptdProc; /* 0x004 */
105 unsigned short lineSize; /* 0x006 */
106 unsigned int l1iSize; /* 0x008 */
107 unsigned int l1dSize; /* 0x00C */
108 unsigned int l2cr; /* 0x010 */
109 unsigned int l2Size; /* 0x014 */
110 unsigned int l3cr; /* 0x018 */
111 unsigned int l3Size; /* 0x01C */
112 unsigned int pfMSSCR0; /* 0x020 */
113 unsigned int pfMSSCR1; /* 0x024 */
114 unsigned int pfICTRL; /* 0x028 */
115 unsigned int pfLDSTCR; /* 0x02C */
116 unsigned int pfLDSTDB; /* 0x030 */
117 unsigned int pfMaxVAddr; /* 0x034 */
118 unsigned int pfMaxPAddr; /* 0x038 */
119 unsigned int pfPTEG; /* 0x03C */
120 uint64_t pfHID0; /* 0x040 */
121 uint64_t pfHID1; /* 0x048 */
122 uint64_t pfHID2; /* 0x050 */
123 uint64_t pfHID3; /* 0x058 */
124 uint64_t pfHID4; /* 0x060 */
125 uint64_t pfHID5; /* 0x068 */
126 unsigned int l2crOriginal; /* 0x070 */
127 unsigned int l3crOriginal; /* 0x074 */
128 unsigned int pfBootConfig; /* 0x078 */
129 unsigned int pfPowerModes; /* 0x07C */
130 #define pmDPLLVmin 0x00010000
131 #define pmDPLLVminb 15
132 #define pmPowerTune 0x00000004
133 #define pmPowerTuneb 29
134 #define pmDFS 0x00000002
135 #define pmDFSb 30
136 #define pmDualPLL 0x00000001
137 #define pmDualPLLb 31
138 unsigned int pfPowerTune0; /* 0x080 */
139 unsigned int pfPowerTune1; /* 0x084 */
140 unsigned int rsrvd88[6]; /* 0x088 */
141 };
142 #pragma pack()
143
144 typedef struct procFeatures procFeatures;
145
146
147 /*
148 *
149 * Various performance counters
150 */
151 #pragma pack(4) /* Make sure the structure stays as we defined it */
152 struct hwCtrs {
153
154 unsigned int hwInVains; /* In vain */
155 unsigned int hwResets; /* Reset */
156 unsigned int hwMachineChecks; /* Machine check */
157 unsigned int hwDSIs; /* DSIs */
158 unsigned int hwISIs; /* ISIs */
159 unsigned int hwExternals; /* Externals */
160 unsigned int hwAlignments; /* Alignment */
161 unsigned int hwPrograms; /* Program */
162 unsigned int hwFloatPointUnavailable; /* Floating point */
163 unsigned int hwDecrementers; /* Decrementer */
164 unsigned int hwIOErrors; /* I/O error */
165 unsigned int hwrsvd0; /* Reserved */
166 unsigned int hwSystemCalls; /* System call */
167 unsigned int hwTraces; /* Trace */
168 unsigned int hwFloatingPointAssists; /* Floating point assist */
169 unsigned int hwPerformanceMonitors; /* Performance monitor */
170 unsigned int hwAltivecs; /* VMX */
171 unsigned int hwrsvd1; /* Reserved */
172 unsigned int hwrsvd2; /* Reserved */
173 unsigned int hwrsvd3; /* Reserved */
174 unsigned int hwInstBreakpoints; /* Instruction breakpoint */
175 unsigned int hwSystemManagements; /* System management */
176 unsigned int hwAltivecAssists; /* Altivec Assist */
177 unsigned int hwThermal; /* Thermals */
178 unsigned int hwrsvd5; /* Reserved */
179 unsigned int hwrsvd6; /* Reserved */
180 unsigned int hwrsvd7; /* Reserved */
181 unsigned int hwrsvd8; /* Reserved */
182 unsigned int hwrsvd9; /* Reserved */
183 unsigned int hwrsvd10; /* Reserved */
184 unsigned int hwrsvd11; /* Reserved */
185 unsigned int hwrsvd12; /* Reserved */
186 unsigned int hwrsvd13; /* Reserved */
187 unsigned int hwTrace601; /* Trace */
188 unsigned int hwSIGPs; /* SIGP */
189 unsigned int hwPreemptions; /* Preemption */
190 unsigned int hwContextSwitchs; /* Context switch */
191 unsigned int hwShutdowns; /* Shutdowns */
192 unsigned int hwChokes; /* System ABENDs */
193 unsigned int hwDataSegments; /* Data Segment Interruptions */
194 unsigned int hwInstructionSegments; /* Instruction Segment Interruptions */
195 unsigned int hwSoftPatches; /* Soft Patch interruptions */
196 unsigned int hwMaintenances; /* Maintenance interruptions */
197 unsigned int hwInstrumentations; /* Instrumentation interruptions */
198 unsigned int hwrsvd14; /* Reswerved */
199 /* 0x0B4 */
200
201 unsigned int hwspare0[17]; /* Reserved */
202 unsigned int hwRedrives; /* Number of redriven interrupts */
203 unsigned int hwSteals; /* PTE Steals */
204 /* 0x100 */
205
206 unsigned int hwMckHang; /* ? */
207 unsigned int hwMckSLBPE; /* ? */
208 unsigned int hwMckTLBPE; /* ? */
209 unsigned int hwMckERCPE; /* ? */
210 unsigned int hwMckL1DPE; /* ? */
211 unsigned int hwMckL1TPE; /* ? */
212 unsigned int hwMckUE; /* ? */
213 unsigned int hwMckIUE; /* ? */
214 unsigned int hwMckIUEr; /* ? */
215 unsigned int hwMckDUE; /* ? */
216 unsigned int hwMckDTW; /* ? */
217 unsigned int hwMckUnk; /* ? */
218 unsigned int hwMckExt; /* ? */
219 unsigned int hwMckICachePE; /* ? */
220 unsigned int hwMckITagPE; /* ? */
221 unsigned int hwMckIEratPE; /* ? */
222 unsigned int hwMckDEratPE; /* ? */
223 unsigned int hwspare2[15]; /* Pad to next 128 bndry */
224 /* 0x180 */
225
226 unsigned int napStamp[2]; /* Time base when we napped */
227 unsigned int napTotal[2]; /* Total nap time in ticks */
228 unsigned int numSIGPast; /* Number of SIGP asts recieved */
229 unsigned int numSIGPcpureq; /* Number of SIGP cpu requests recieved */
230 unsigned int numSIGPdebug; /* Number of SIGP debugs recieved */
231 unsigned int numSIGPwake; /* Number of SIGP wakes recieved */
232 unsigned int numSIGPtimo; /* Number of SIGP send timeouts */
233 unsigned int numSIGPmast; /* Number of SIGPast messages merged */
234 unsigned int numSIGPmwake; /* Number of SIGPwake messages merged */
235
236 unsigned int hwspare3[21]; /* Pad to 512 */
237
238 };
239 #pragma pack()
240
241 typedef struct hwCtrs hwCtrs;
242
243 struct patch_entry {
244 unsigned int *addr;
245 unsigned int data;
246 unsigned int type;
247 unsigned int value;
248 };
249
250 typedef struct patch_entry patch_entry_t;
251
252 #define PATCH_INVALID 0
253 #define PATCH_PROCESSOR 1
254 #define PATCH_FEATURE 2
255
256 #define PATCH_TABLE_SIZE 12
257
258 #define PatchExt32 0x80000000
259 #define PatchExt32b 0
260 #define PatchLwsync 0x40000000
261 #define PatchLwsyncb 1
262
263 /* When an exception is taken, this info is accessed via sprg0 */
264 /* We should always have this one on a cache line boundary */
265
266 #pragma pack(4) /* Make sure the structure stays as we defined it */
267 struct per_proc_info {
268 unsigned short cpu_number;
269 unsigned short cpu_flags; /* Various low-level flags */
270 vm_offset_t istackptr;
271 vm_offset_t intstack_top_ss;
272
273 vm_offset_t debstackptr;
274 vm_offset_t debstack_top_ss;
275
276 unsigned int spcFlags; /* Special thread flags */
277 unsigned int Uassist; /* User Assist Word */
278 unsigned int old_thread;
279
280 /* PPC cache line boundary here - 020 */
281
282 unsigned int rsrvd020[2];
283 unsigned int need_ast; /* pointer to need_ast[CPU_NO] */
284 /*
285 * Note: the following two pairs of words need to stay in order and each pair must
286 * be in the same reservation (line) granule
287 */
288 struct facility_context *FPU_owner; /* Owner of the FPU on this cpu */
289 unsigned int liveVRSave; /* VRSave assiciated with live vector registers */
290 struct facility_context *VMX_owner; /* Owner of the VMX on this cpu */
291 unsigned int holdQFret; /* Hold off releasing quickfret list */
292 unsigned int save_exception_type;
293
294 /* PPC cache line boundary here - 040 */
295 addr64_t quickfret; /* List of saveareas to release */
296 addr64_t lclfree; /* Pointer to local savearea list */
297 unsigned int lclfreecnt; /* Entries in local savearea list */
298 unsigned int spcTRc; /* Special trace count */
299 unsigned int spcTRp; /* Special trace buffer pointer */
300 unsigned int ppbbTaskEnv; /* BlueBox Task Environment */
301
302 /* PPC cache line boundary here - 060 */
303 boolean_t interrupts_enabled;
304 IOInterruptHandler interrupt_handler;
305 void * interrupt_nub;
306 unsigned int interrupt_source;
307 void * interrupt_target;
308 void * interrupt_refCon;
309 uint64_t next_savearea; /* pointer to the next savearea */
310
311 /* PPC cache line boundary here - 080 */
312 unsigned int MPsigpStat; /* Signal Processor status (interlocked update for this one) */
313 #define MPsigpMsgp 0xC0000000 /* Message pending (busy + pass ) */
314 #define MPsigpBusy 0x80000000 /* Processor area busy, i.e., locked */
315 #define MPsigpPass 0x40000000 /* Busy lock passed to receiving processor */
316 #define MPsigpAck 0x20000000 /* Ack Busy lock passed to receiving processor */
317 #define MPsigpSrc 0x000000FF /* Processor that owns busy, i.e., the ID of */
318 /* whomever set busy. When a busy is passed, */
319 /* this is the requestor of the function. */
320 #define MPsigpFunc 0x0000FF00 /* Current function */
321 #define MPsigpIdle 0x00 /* No function pending */
322 #define MPsigpSigp 0x04 /* Signal a processor */
323 #define SIGPast 0 /* Requests an ast on target processor */
324 #define SIGPcpureq 1 /* Requests CPU specific function */
325 #define SIGPdebug 2 /* Requests a debugger entry */
326 #define SIGPwake 3 /* Wake up a sleeping processor */
327 #define CPRQtemp 0 /* Get temprature of processor */
328 #define CPRQtimebase 1 /* Get timebase of processor */
329 #define CPRQsegload 2 /* Segment registers reload */
330 #define CPRQscom 3 /* SCOM */
331 #define CPRQchud 4 /* CHUD perfmon */
332 unsigned int MPsigpParm0; /* SIGP parm 0 */
333 unsigned int MPsigpParm1; /* SIGP parm 1 */
334 unsigned int MPsigpParm2; /* SIGP parm 2 */
335 cpu_id_t cpu_id;
336 vm_offset_t start_paddr;
337 unsigned int ruptStamp[2]; /* Timebase at last interruption */
338
339 /* PPC cache line boundary here - 0A0 */
340 procFeatures pf; /* Processor features */
341
342 /* PPC cache line boundary here - 140 */
343 unsigned int ppRsvd140[8]; /* Reserved */
344
345 /* PPC cache line boundary here - 160 */
346 time_base_enable_t time_base_enable;
347 unsigned int ppRsvd164[4]; /* Reserved */
348 cpu_data_t pp_cpu_data; /* cpu data info */
349
350 /* PPC cache line boundary here - 180 */
351 unsigned int ppRsvd180[2]; /* Reserved */
352 uint64_t validSegs; /* Valid SR/STB slots */
353 addr64_t ppUserPmap; /* Current user state pmap (physical address) */
354 unsigned int ppUserPmapVirt; /* Current user state pmap (virtual address) */
355 unsigned int ppMapFlags; /* Mapping flags */
356
357 /* PPC cache line boundary here - 1A0 */
358 unsigned short ppInvSeg; /* Forces complete invalidate of SRs/SLB (this must stay with ppInvSeg) */
359 unsigned short ppCurSeg; /* Set to 1 if user segments, 0 if kernel (this must stay with ppInvSeg) */
360 unsigned int ppSegSteal; /* Count of segment slot steals */
361 ppnum_t VMMareaPhys; /* vmm state page physical addr */
362 unsigned int VMMXAFlgs; /* vmm extended flags */
363 unsigned int FAMintercept; /* vmm FAM Exceptions to intercept */
364 unsigned int rsrvd1B4[3]; /* Reserved slots */
365
366 /* PPC cache line boundary here - 1C0 */
367 unsigned int ppCIOmp[16]; /* Linkage mapping for copyin/out - 64 bytes */
368
369 /* PPC cache line boundary here - 200 */
370 uint64_t tempr0; /* temporary savearea */
371 uint64_t tempr1;
372 uint64_t tempr2;
373 uint64_t tempr3;
374
375 uint64_t tempr4;
376 uint64_t tempr5;
377 uint64_t tempr6;
378 uint64_t tempr7;
379
380 uint64_t tempr8;
381 uint64_t tempr9;
382 uint64_t tempr10;
383 uint64_t tempr11;
384
385 uint64_t tempr12;
386 uint64_t tempr13;
387 uint64_t tempr14;
388 uint64_t tempr15;
389
390 uint64_t tempr16;
391 uint64_t tempr17;
392 uint64_t tempr18;
393 uint64_t tempr19;
394
395 uint64_t tempr20;
396 uint64_t tempr21;
397 uint64_t tempr22;
398 uint64_t tempr23;
399
400 uint64_t tempr24;
401 uint64_t tempr25;
402 uint64_t tempr26;
403 uint64_t tempr27;
404
405 uint64_t tempr28;
406 uint64_t tempr29;
407 uint64_t tempr30;
408 uint64_t tempr31;
409
410
411 /* PPC cache line boundary here - 300 */
412 double emfp0; /* Copies of floating point registers */
413 double emfp1; /* Used for emulation purposes */
414 double emfp2;
415 double emfp3;
416
417 double emfp4;
418 double emfp5;
419 double emfp6;
420 double emfp7;
421
422 double emfp8;
423 double emfp9;
424 double emfp10;
425 double emfp11;
426
427 double emfp12;
428 double emfp13;
429 double emfp14;
430 double emfp15;
431
432 double emfp16;
433 double emfp17;
434 double emfp18;
435 double emfp19;
436
437 double emfp20;
438 double emfp21;
439 double emfp22;
440 double emfp23;
441
442 double emfp24;
443 double emfp25;
444 double emfp26;
445 double emfp27;
446
447 double emfp28;
448 double emfp29;
449 double emfp30;
450 double emfp31;
451
452 /* - 400 */
453 unsigned int emfpscr_pad;
454 unsigned int emfpscr;
455 unsigned int empadfp[6];
456
457 /* - 420 */
458 unsigned int emvr0[4]; /* Copies of vector registers used both */
459 unsigned int emvr1[4]; /* for full vector emulation or */
460 unsigned int emvr2[4]; /* as saveareas while assisting denorms */
461 unsigned int emvr3[4];
462 unsigned int emvr4[4];
463 unsigned int emvr5[4];
464 unsigned int emvr6[4];
465 unsigned int emvr7[4];
466 unsigned int emvr8[4];
467 unsigned int emvr9[4];
468 unsigned int emvr10[4];
469 unsigned int emvr11[4];
470 unsigned int emvr12[4];
471 unsigned int emvr13[4];
472 unsigned int emvr14[4];
473 unsigned int emvr15[4];
474 unsigned int emvr16[4];
475 unsigned int emvr17[4];
476 unsigned int emvr18[4];
477 unsigned int emvr19[4];
478 unsigned int emvr20[4];
479 unsigned int emvr21[4];
480 unsigned int emvr22[4];
481 unsigned int emvr23[4];
482 unsigned int emvr24[4];
483 unsigned int emvr25[4];
484 unsigned int emvr26[4];
485 unsigned int emvr27[4];
486 unsigned int emvr28[4];
487 unsigned int emvr29[4];
488 unsigned int emvr30[4];
489 unsigned int emvr31[4];
490 unsigned int emvscr[4];
491 unsigned int empadvr[4];
492 /* - 640 */
493 /* note implicit dependence on kSkipListMaxLists, which must be <= 28 */
494 addr64_t skipListPrev[28]; /* prev ptrs saved as side effect of calling mapSearchFull() */
495
496 /* - 720 */
497
498 unsigned int patcharea[56];
499 /* - 800 */
500
501 hwCtrs hwCtr; /* Hardware exception counters */
502 /* - A00 */
503
504 unsigned int pppadpage[384]; /* Pad to end of page */
505 /* - 1000 */
506
507
508 };
509
510 #define pp_preemption_count pp_cpu_data.preemption_level
511 #define pp_simple_lock_count pp_cpu_data.simple_lock_count
512 #define pp_interrupt_level pp_cpu_data.interrupt_level
513
514 #pragma pack()
515
516
517 extern struct per_proc_info per_proc_info[NCPUS];
518
519
520 extern char *trap_type[];
521
522 #endif /* ndef ASSEMBLER */ /* with this savearea should be redriven */
523
524 /* cpu_flags defs */
525 #define SIGPactive 0x8000
526 #define needSRload 0x4000
527 #define turnEEon 0x2000
528 #define traceBE 0x1000 /* user mode BE tracing in enabled */
529 #define traceBEb 3 /* bit number for traceBE */
530 #define SleepState 0x0800
531 #define SleepStateb 4
532 #define mcountOff 0x0400
533 #define SignalReady 0x0200
534 #define BootDone 0x0100
535 #define loadMSR 0x7FF4
536
537 #define T_VECTOR_SIZE 4 /* function pointer size */
538
539 /* Hardware exceptions */
540
541 #define T_IN_VAIN (0x00 * T_VECTOR_SIZE)
542 #define T_RESET (0x01 * T_VECTOR_SIZE)
543 #define T_MACHINE_CHECK (0x02 * T_VECTOR_SIZE)
544 #define T_DATA_ACCESS (0x03 * T_VECTOR_SIZE)
545 #define T_INSTRUCTION_ACCESS (0x04 * T_VECTOR_SIZE)
546 #define T_INTERRUPT (0x05 * T_VECTOR_SIZE)
547 #define T_ALIGNMENT (0x06 * T_VECTOR_SIZE)
548 #define T_PROGRAM (0x07 * T_VECTOR_SIZE)
549 #define T_FP_UNAVAILABLE (0x08 * T_VECTOR_SIZE)
550 #define T_DECREMENTER (0x09 * T_VECTOR_SIZE)
551 #define T_IO_ERROR (0x0a * T_VECTOR_SIZE)
552 #define T_RESERVED (0x0b * T_VECTOR_SIZE)
553 #define T_SYSTEM_CALL (0x0c * T_VECTOR_SIZE)
554 #define T_TRACE (0x0d * T_VECTOR_SIZE)
555 #define T_FP_ASSIST (0x0e * T_VECTOR_SIZE)
556 #define T_PERF_MON (0x0f * T_VECTOR_SIZE)
557 #define T_VMX (0x10 * T_VECTOR_SIZE)
558 #define T_INVALID_EXCP0 (0x11 * T_VECTOR_SIZE)
559 #define T_INVALID_EXCP1 (0x12 * T_VECTOR_SIZE)
560 #define T_INVALID_EXCP2 (0x13 * T_VECTOR_SIZE)
561 #define T_INSTRUCTION_BKPT (0x14 * T_VECTOR_SIZE)
562 #define T_SYSTEM_MANAGEMENT (0x15 * T_VECTOR_SIZE)
563 #define T_ALTIVEC_ASSIST (0x16 * T_VECTOR_SIZE)
564 #define T_THERMAL (0x17 * T_VECTOR_SIZE)
565 #define T_INVALID_EXCP5 (0x18 * T_VECTOR_SIZE)
566 #define T_INVALID_EXCP6 (0x19 * T_VECTOR_SIZE)
567 #define T_INVALID_EXCP7 (0x1A * T_VECTOR_SIZE)
568 #define T_INVALID_EXCP8 (0x1B * T_VECTOR_SIZE)
569 #define T_INVALID_EXCP9 (0x1C * T_VECTOR_SIZE)
570 #define T_INVALID_EXCP10 (0x1D * T_VECTOR_SIZE)
571 #define T_INVALID_EXCP11 (0x1E * T_VECTOR_SIZE)
572 #define T_INVALID_EXCP12 (0x1F * T_VECTOR_SIZE)
573 #define T_EMULATE (0x20 * T_VECTOR_SIZE)
574
575 #define T_RUNMODE_TRACE (0x21 * T_VECTOR_SIZE) /* 601 only */
576
577 #define T_SIGP (0x22 * T_VECTOR_SIZE)
578 #define T_PREEMPT (0x23 * T_VECTOR_SIZE)
579 #define T_CSWITCH (0x24 * T_VECTOR_SIZE)
580 #define T_SHUTDOWN (0x25 * T_VECTOR_SIZE)
581 #define T_CHOKE (0x26 * T_VECTOR_SIZE)
582
583 #define T_DATA_SEGMENT (0x27 * T_VECTOR_SIZE)
584 #define T_INSTRUCTION_SEGMENT (0x28 * T_VECTOR_SIZE)
585
586 #define T_SOFT_PATCH (0x29 * T_VECTOR_SIZE)
587 #define T_MAINTENANCE (0x2A * T_VECTOR_SIZE)
588 #define T_INSTRUMENTATION (0x2B * T_VECTOR_SIZE)
589 #define T_ARCHDEP0 (0x2C * T_VECTOR_SIZE)
590
591 #define T_AST (0x100 * T_VECTOR_SIZE)
592 #define T_MAX T_CHOKE /* Maximum exception no */
593
594 #define T_FAM 0x00004000
595
596 #define EXCEPTION_VECTOR(exception) (exception * 0x100 / T_VECTOR_SIZE )
597
598 /*
599 * System choke (failure) codes
600 */
601
602 #define failDebug 0
603 #define failStack 1
604 #define failMapping 2
605 #define failContext 3
606 #define failNoSavearea 4
607 #define failSaveareaCorr 5
608 #define failBadLiveContext 6
609 #define failSkipLists 7
610 #define failUnalignedStk 8
611
612 /* Always must be last - update failNames table in model_dep.c as well */
613 #define failUnknown 9
614
615 #ifndef ASSEMBLER
616
617 #pragma pack(4) /* Make sure the structure stays as we defined it */
618 typedef struct resethandler {
619 unsigned int type;
620 vm_offset_t call_paddr;
621 vm_offset_t arg__paddr;
622 } resethandler_t;
623 #pragma pack()
624
625 extern resethandler_t ResetHandler;
626
627 #endif
628
629 #define RESET_HANDLER_NULL 0x0
630 #define RESET_HANDLER_START 0x1
631 #define RESET_HANDLER_BUPOR 0x2
632 #define RESET_HANDLER_IGNORE 0x3
633
634 #endif /* _PPC_EXCEPTION_H_ */
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