iokit/Drivers/network/drvPPCUniN/UniNEnetMII.h

   1 /*
   2  * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22
  23 /*
  24  * Copyright (c) 1998-1999 by Apple Computer, Inc., All rights reserved.
  25  *
  26  * MII protocol and PHY register definitions.
  27  *
  28  * HISTORY
  29  *
  30  */
  31
  32 /*
  33  *      MII command frame (32-bits) as documented in IEEE 802.3u
  34  */
  35 #define MII_OP_READ     0x02
  36 #define MII_OP_WRITE    0x01
  37
  38 #define MII_MAX_PHY                             32
  39
  40 /* MII Registers */
  41 #define MII_CONTROL                             0
  42 #define MII_STATUS                              1
  43 #define MII_ID0                                 2
  44 #define MII_ID1                                 3
  45 #define MII_ADVERTISEMENT                       4
  46 #define MII_LINKPARTNER                         5
  47 #define MII_EXPANSION                           6
  48 #define MII_NEXTPAGE                            7
  49
  50 /* MII Control register bits */
  51 #define MII_CONTROL_RESET                       0x8000
  52 #define MII_CONTROL_LOOPBACK                    0x4000
  53 #define MII_CONTROL_SPEED_SELECTION             0x2000
  54 #define MII_CONTROL_AUTONEGOTIATION             0x1000
  55 #define MII_CONTROL_POWERDOWN                   0x800
  56 #define MII_CONTROL_ISOLATE                     0x400
  57 #define MII_CONTROL_RESTART_NEGOTIATION         0x200
  58 #define MII_CONTROL_FULLDUPLEX                  0x100
  59 #define MII_CONTROL_COLLISION_TEST              0x80
  60
  61 /* MII Status register bits */
  62 #define MII_STATUS_100BASET4                    0x8000
  63 #define MII_STATUS_100BASETX_FD                 0x4000
  64 #define MII_STATUS_100BASETX                    0x2000
  65 #define MII_STATUS_10BASET_FD                   0x1000
  66 #define MII_STATUS_10BASET                      0x800
  67 #define MII_STATUS_NEGOTIATION_COMPLETE         0x20
  68 #define MII_STATUS_REMOTE_FAULT                 0x10
  69 #define MII_STATUS_NEGOTIATION_ABILITY          0x8
  70 #define MII_STATUS_LINK_STATUS                  0x4
  71 #define MII_STATUS_JABBER_DETECT                0x2
  72 #define MII_STATUS_EXTENDED_CAPABILITY          0x1
  73
  74 /* MII ANAR register bits */
  75 #define MII_ANAR_ASYM_PAUSE                     0x800
  76 #define MII_ANAR_PAUSE                          0x400
  77 #define MII_ANAR_100BASET4                      0x200
  78 #define MII_ANAR_100BASETX_FD                   0x100
  79 #define MII_ANAR_100BASETX                      0x80
  80 #define MII_ANAR_10BASET_FD                     0x40
  81 #define MII_ANAR_10BASET                        0x20
  82
  83 /* MII ANLPAR register bits */
  84 #define MII_LPAR_NEXT_PAGE                      0x8000
  85 #define MII_LPAR_ACKNOWLEDGE                    0x4000
  86 #define MII_LPAR_REMOTE_FAULT                   0x2000
  87 #define MII_LPAR_ASYM_PAUSE                     0x0800
  88 #define MII_LPAR_PAUSE                          0x0400
  89 #define MII_LPAR_100BASET4                      0x200
  90 #define MII_LPAR_100BASETX_FD                   0x100
  91 #define MII_LPAR_100BASETX                      0x80
  92 #define MII_LPAR_10BASET_FD                     0x40
  93 #define MII_LPAR_10BASET                        0x20
  94
  95
  96 /* MII BCM5201 Specific */
  97
  98 /* MII BCM5201 ID */
  99 #define MII_BCM5201_OUI                         0x001018
 100 #define MII_BCM5201_MODEL                       0x21
 101 #define MII_BCM5201_REV                         0x01
 102 #define MII_BCM5201_ID                          ((MII_BCM5201_OUI << 10) | (MII_BCM5201_MODEL << 4))
 103 #define MII_BCM5201_MASK                        0xfffffff0
 104
 105 #define MII_BCM5201_DELAY                       1
 106
 107 /* MII BCM5201 Regs */
 108 #define MII_BCM5201_AUXSTATUS                   0x18
 109
 110 /* MII BCM5201 AUXSTATUS register bits */
 111 #define MII_BCM5201_AUXSTATUS_DUPLEX            0x0001
 112 #define MII_BCM5201_AUXSTATUS_SPEED             0x0002
 113
 114 /* MII BCM5201 MULTIPHY interrupt register.
 115  * Added 4/20/2000 by A.W. for power management */
 116 #define MII_BCM5201_INTERRUPT                   0x1A
 117 #define MII_BCM5201_INTERRUPT_INTENABLE         0x4000
 118
 119 #define MII_BCM5201_AUXMODE2                    0x1B
 120 #define MII_BCM5201_AUXMODE2_LOWPOWER           0x0008
 121
 122 #define MII_BCM5201_MULTIPHY                    0x1E
 123
 124 /* MII BCM5201 MULTIPHY register bits */
 125 #define MII_BCM5201_MULTIPHY_SERIALMODE         0x0002
 126 #define MII_BCM5201_MULTIPHY_SUPERISOLATE       0x0008
 127
 128
 129 /* MII LXT971 (Level One) Specific */
 130
 131 /* MII LXT971 ID */
 132 #define MII_LXT971_OUI                          0x0004de
 133 #define MII_LXT971_MODEL                        0x0e
 134 #define MII_LXT971_REV                          0x01
 135 #define MII_LXT971_ID                           ((MII_LXT971_OUI << 10) | (MII_LXT971_MODEL << 4))
 136 #define MII_LXT971_MASK                         0xfffffff0
 137
 138 #define MII_LXT971_DELAY                        1
 139
 140 /* MII LXT971 Regs */
 141 #define MII_LXT971_STATUS_2                     0x11
 142
 143 /* MII LXT971 Status #2 register bits */
 144 #define MII_LXT971_STATUS_2_DUPLEX              0x0200
 145 #define MII_LXT971_STATUS_2_SPEED               0x4000
 146
 147 /* MII BCM5400 Specific */
 148
 149 /* MII BCM5400 ID */
 150 #define MII_BCM5400_OUI                         0x000818
 151 #define MII_BCM5400_MODEL                       0x04
 152 #define MII_BCM5401_MODEL                       0x05
 153 #define MII_BCM5400_REV                         0x01
 154 #define MII_BCM5400_ID                          ((MII_BCM5400_OUI << 10) | (MII_BCM5400_MODEL << 4))
 155 #define MII_BCM5401_ID                          ((MII_BCM5400_OUI << 10) | (MII_BCM5401_MODEL << 4))
 156 #define MII_BCM5400_MASK                        0xfffffff0
 157
 158 #define MII_BCM5400_DELAY                       1
 159
 160 /* MII BCM5400 Regs */
 161
 162 #define MII_BCM5400_1000BASETCONTROL            0x09
 163 /* MII BCM5400 1000-BASET Control register bits */
 164
 165 #define MII_BCM5400_1000BASETCONTROL_FULLDUPLEXCAP      0x0200
 166
 167 #define MII_BCM5400_AUXCONTROL                  0x18
 168
 169 /* MII BCM5400 AUXCONTROL register bits */
 170 #define MII_BCM5400_AUXCONTROL_PWR10BASET       0x0004
 171
 172 #define MII_BCM5400_AUXSTATUS                   0x19
 173
 174 /* MII BCM5400 AUXSTATUS register bits */
 175 #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK     0x0700
 176 #define MII_BCM5400_AUXSTATUS_LINKMODE_BIT      0x0100
 177
 178
 179 /* MII ST10040 Specific */
 180
 181 /* MII ST10040 ID */
 182 #define MII_ST10040_OUI                         0x1e0400
 183 #define MII_ST10040_MODEL                       0x00
 184 #define MII_ST10040_REV                         0x01
 185 #define MII_ST10040_ID                          ((MII_ST10040_OUI << 10) | (MII_ST10040_MODEL << 4))
 186 #define MII_ST10040_MASK                        0xfffffff0
 187
 188 #define MII_ST10040_DELAY                       1
 189
 190 /* MII ST10040 Regs */
 191 #define MII_ST10040_CHIPST                      0x14
 192
 193 /* MII ST10040 CHIPST register bits */
 194 #define MII_ST10040_CHIPST_LINK                 0x2000
 195 #define MII_ST10040_CHIPST_DUPLEX               0x1000
 196 #define MII_ST10040_CHIPST_SPEED                0x0800
 197 #define MII_ST10040_CHIPST_NEGOTIATION          0x0020
 198
 199
 200 /* MII DP83843 Specific */
 201
 202 /* MII DP83843 ID */
 203 #define MII_DP83843_OUI                         0x080017
 204 #define MII_DP83843_MODEL                       0x01
 205 #define MII_DP83843_REV                         0x00
 206 #define MII_DP83843_ID                          ((MII_DP83843_OUI << 10) | (MII_DP83843_MODEL << 4))
 207 #define MII_DP83843_MASK                        0xfffffff0
 208
 209 #define MII_DP83843_DELAY                       20
 210
 211 /* MII DP83843 PHYSTS register bits */
 212 #define MII_DP83843_PHYSTS                      0x10
 213 #define MII_DP83843_PHYSTS_LINK                 0x0001
 214 #define MII_DP83843_PHYSTS_SPEED10              0x0002
 215 #define MII_DP83843_PHYSTS_DUPLEX               0x0004
 216 #define MII_DP83843_PHYSTS_NEGOTIATION          0x0020
 217
 218
 219 /* MII timeout */
 220 #define MII_DEFAULT_DELAY                       20
 221 #define MII_RESET_TIMEOUT                       100
 222 #define MII_RESET_DELAY                         10
 223
 224 #define MII_LINK_TIMEOUT                        2500
 225 #define MII_LINK_DELAY                          20
 226
 227 /* A few constants needed for miiWriteWord() */
 228 enum {
 229     kPHYAddr0  = 0x00000000,    //PHY addr is 0
 230     kPHYAddr1F = 0x0000001F
 231 };