osfmk/i386/cpuid.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
   7  *
   8  * This file contains Original Code and/or Modifications of Original Code
   9  * as defined in and that are subject to the Apple Public Source License
  10  * Version 2.0 (the 'License'). You may not use this file except in
  11  * compliance with the License. Please obtain a copy of the License at
  12  * http://www.opensource.apple.com/apsl/ and read it before using this
  13  * file.
  14  *
  15  * The Original Code and all software distributed under the License are
  16  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  17  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  18  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  20  * Please see the License for the specific language governing rights and
  21  * limitations under the License.
  22  *
  23  * @APPLE_LICENSE_HEADER_END@
  24  */
  25 /*
  26  * @OSF_COPYRIGHT@
  27  */
  28
  29 /*
  30  * x86 CPU identification
  31  *
  32  * TODO : Add TI/Thomson processors
  33  */
  34
  35 #ifndef _MACHINE_CPUID_H_
  36 #define _MACHINE_CPUID_H_
  37
  38 #define CPUID_VID_SIZE          12
  39 #define CPUID_VID_INTEL         "GenuineIntel"
  40 #define CPUID_VID_UMC           "UMC UMC UMC "
  41 #define CPUID_VID_AMD           "AuthenticAMD"
  42 #define CPUID_VID_CYRIX         "CyrixInstead"
  43 #define CPUID_VID_NEXTGEN       "NexGenDriven"
  44
  45 #define CPUID_FEATURE_FPU    0x00000001 /* Floating point unit on-chip */
  46 #define CPUID_FEATURE_VME    0x00000002 /* Virtual Mode Extension */
  47 #define CPUID_FEATURE_IOB    0x00000004 /* I/O Breakpoints */
  48 #define CPUID_FEATURE_PSE    0x00000008 /* Page Size Extension */
  49 #define CPUID_FEATURE_TSC    0x00000010 /* Time Stamp Counter */
  50 #define CPUID_FEATURE_MSR    0x00000020 /* Model Specific Registers */
  51 #define CPUID_FEATURE_MCE    0x00000080 /* Machine Check Exception */
  52 #define CPUID_FEATURE_CX8    0x00000100 /* CMPXCHG8B */
  53 #define CPUID_FEATURE_APIC   0x00000200 /* On-chip APIC */
  54 #define CPUID_FEATURE_MTRR   0x00001000 /* Memory Type Range Register */
  55 #define CPUID_FEATURE_PGE    0x00002000 /* Page Global Enable */
  56 #define CPUID_FEATURE_MCA    0x00004000 /* Machine Check Architecture */
  57 #define CPUID_FEATURE_CMOV   0x00008000 /* Conditional Move Instruction */
  58
  59 #define CPUID_TYPE_OEM              0x0 /* Original processor */
  60 #define CPUID_TYPE_OVERDRIVE        0x1 /* Overdrive processor */
  61 #define CPUID_TYPE_DUAL             0x2 /* Can be used as dual processor */
  62 #define CPUID_TYPE_RESERVED         0x3 /* Reserved */
  63
  64 #define CPUID_FAMILY_386            0x3 /* Intel 386 (not part of CPUID) */
  65 #define CPUID_FAMILY_486            0x4 /* Intel 486 */
  66 #define CPUID_FAMILY_P5             0x5 /* Intel Pentium */
  67 #define CPUID_FAMILY_PPRO           0x6 /* Intel Pentium Pro */
  68
  69 #define CPUID_MODEL_I386_DX         0x0 /* Intel 386 (not part of CPUID) */
  70
  71 #define CPUID_MODEL_I486_DX         0x0 /* Intel 486DX */
  72 #define CPUID_MODEL_I486_DX_S       0x1 /* Intel 486DX-S */
  73 #define CPUID_MODEL_I486_SX         0x2 /* Intel 486SX */
  74 #define CPUID_MODEL_I486_DX2        0x3 /* Intel 486DX2 */
  75 #define CPUID_MODEL_I486_SL         0x4 /* Intel 486SL */
  76 #define CPUID_MODEL_I486_SX2        0x5 /* Intel 486SX2 */
  77 #define CPUID_MODEL_I486_DX2WB      0x7 /* Intel 486DX2WB */
  78 #define CPUID_MODEL_I486_DX4        0x8 /* Intel 486DX4 */
  79 #define CPUID_MODEL_I486_DX4WB      0x9 /* Intel 486DX4WB */
  80
  81 #define CPUID_MODEL_AM486_DX        0x1 /* AMD 486DX */
  82 #define CPUID_MODEL_AM486_DX2       0x3 /* AMD 486DX2 */
  83 #define CPUID_MODEL_AM486_DX2WB     0x7 /* AMD 486DX2WB */
  84 #define CPUID_MODEL_AM486_DX4       0x8 /* AMD 486DX4 */
  85 #define CPUID_MODEL_AM486_DX4WB     0x9 /* AMD 486DX4WB */
  86 #define CPUID_MODEL_AM486_5X86      0xE /* AMD 5x86 */
  87 #define CPUID_MODEL_AM486_5X86WB    0xF /* AMD 5x86WB */
  88
  89 #define CPUID_MODEL_CYRIX5X86       0x9 /* CYRIX 5X86 */
  90
  91 #define CPUID_MODEL_UMC5SD          0x1 /* UMC U5SD */
  92 #define CPUID_MODEL_UMC5S           0x2 /* UMC U5S */
  93 #define CPUID_MODEL_UMC486_DX2      0x3 /* UMC U486_DX2 */
  94 #define CPUID_MODEL_UMC486_SX2      0x5 /* UMC U486_SX2 */
  95
  96 #define CPUID_MODEL_P5A             0x0 /* Intel P5 60/66 Step A */
  97 #define CPUID_MODEL_P5              0x1 /* Intel P5 60/66 */
  98 #define CPUID_MODEL_P54             0x2 /* Intel P5 75/80/100/120/133/166 */
  99 #define CPUID_MODEL_P24T            0x3 /* Intel P5 Overdrive 63/83 */
 100
 101 #define CPUID_MODEL_P6              0x1 /* Intel P6 */
 102 #define CPUID_MODEL_PII             0x3 /* Intel PII */
 103
 104 #define CPUID_CACHE_SIZE        16      /* Number of descriptor vales */
 105 #define CPUID_CACHE_VALID        4      /* Index of descriptor validity */
 106
 107 #define CPUID_CACHE_NULL           0x00 /* NULL */
 108 #define CPUID_CACHE_ITLB_4K        0x01 /* Instruction TLB, 4K pages */
 109 #define CPUID_CACHE_ITLB_4M        0x02 /* Instruction TLB, 4M pages */
 110 #define CPUID_CACHE_DTLB_4K        0x03 /* Data TLB, 4K pages */
 111 #define CPUID_CACHE_DTLB_4M        0x04 /* Data TLB, 4M pages */
 112 #define CPUID_CACHE_ICACHE_8K      0x06 /* Instruction cache, 8K */
 113 #define CPUID_CACHE_DCACHE_8K      0x0A /* Data cache, 8K */
 114 #define CPUID_CACHE_UCACHE_128K    0x41 /* Unified cache, 128K */
 115 #define CPUID_CACHE_UCACHE_256K    0x42 /* Unified cache, 256K */
 116 #define CPUID_CACHE_UCACHE_512K    0x43 /* Unified cache, 512K */
 117
 118 #ifndef ASSEMBLER
 119 #include <mach/machine.h>
 120
 121 extern unsigned int     cpuid_value;
 122 extern unsigned char    cpuid_type;
 123 extern unsigned char    cpuid_family;
 124 extern unsigned char    cpuid_model;
 125 extern unsigned char    cpuid_stepping;
 126 extern unsigned int     cpuid_feature;
 127 extern char             cpuid_vid[];
 128 extern unsigned char    cpuid_cache[];
 129
 130 /*
 131  * Product ID arrays per vendor
 132  */
 133 struct cpuid_product {
 134     unsigned char               type;           /* CPU type */
 135     unsigned char               family;         /* CPU family */
 136     unsigned char               model;          /* CPU model */
 137     unsigned int                delay;          /* 1MHz Delay (scale 1000) */
 138     unsigned int                *frequency;     /* Frequency array */
 139     char                        *name;          /* Model name */
 140 };
 141
 142 /*
 143  * Vendor ID structure
 144  */
 145 struct cpuid_name {
 146     char                        *name;          /* Vendor ID name */
 147     struct cpuid_product        *product;       /* product array */
 148     unsigned int                size;           /* #elements in product array */
 149 };
 150
 151 /*
 152  * Cache ID description structure
 153  */
 154 struct cpuid_cache_desc {
 155     unsigned char               value;          /* Descriptor value */
 156     char                        *description;   /* Cache description */
 157 };
 158
 159 /*
 160  * External declarations
 161  */
 162 extern cpu_type_t       cpuid_cputype(int);
 163 extern void             cpuid_cpu_display(char *, int);
 164 extern void             cpuid_cache_display(char *, int);
 165
 166 #endif /* ASSEMBLER */
 167 #endif /* _MACHINE_CPUID_H_ */