osfmk/chud/ppc/chud_cpu_asm.s

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #define ASSEMBLER
  30 #include <chud/ppc/chud_spr.h>
  31 #include <ppc/asm.h>
  32 #include <mach/kern_return.h>
  33
  34 /*
  35  * kern_return_t mfspr64(uint64_t *val, int spr);
  36  *
  37  * r3: address to store value in
  38  * r4: spr to read from
  39  *
  40  */
  41
  42 ;           Force a line boundry here
  43             .align  5
  44             .globl  EXT(mfspr64)
  45
  46 EXT(mfspr64):
  47             ;; generic PPC 64-bit wide SPRs
  48             cmpwi       r4,chud_ppc_srr0
  49             beq         mfspr64_srr0
  50             cmpwi       r4,chud_ppc_srr1
  51             beq         mfspr64_srr1
  52             cmpwi       r4,chud_ppc_dar
  53             beq         mfspr64_dar
  54             cmpwi       r4,chud_ppc_sdr1
  55             beq         mfspr64_sdr1
  56             cmpwi       r4,chud_ppc_sprg0
  57             beq         mfspr64_sprg0
  58             cmpwi       r4,chud_ppc_sprg1
  59             beq         mfspr64_sprg1
  60             cmpwi       r4,chud_ppc_sprg2
  61             beq         mfspr64_sprg2
  62             cmpwi       r4,chud_ppc_sprg3
  63             beq         mfspr64_sprg3
  64             cmpwi       r4,chud_ppc64_asr
  65             beq         mfspr64_asr
  66             cmpwi       r4,chud_ppc_dabr
  67             beq         mfspr64_dabr
  68
  69             ;; GPUL specific 64-bit wide SPRs
  70             cmpwi       r4,chud_970_hid0
  71             beq         mfspr64_hid0
  72             cmpwi       r4,chud_970_hid1
  73             beq         mfspr64_hid1
  74             cmpwi       r4,chud_970_hid4
  75             beq         mfspr64_hid4
  76             cmpwi       r4,chud_970_hid5
  77             beq         mfspr64_hid5
  78             cmpwi       r4,chud_970_mmcr0
  79             beq         mfspr64_mmcr0
  80             cmpwi       r4,chud_970_mmcr1
  81             beq         mfspr64_mmcr1
  82             cmpwi       r4,chud_970_mmcra
  83             beq         mfspr64_mmcra
  84             cmpwi       r4,chud_970_siar
  85             beq         mfspr64_siar
  86             cmpwi       r4,chud_970_sdar
  87             beq         mfspr64_sdar
  88             cmpwi       r4,chud_970_imc
  89             beq         mfspr64_imc
  90             cmpwi       r4,chud_970_rmor
  91             beq         mfspr64_rmor
  92             cmpwi       r4,chud_970_hrmor
  93             beq         mfspr64_hrmor
  94             cmpwi       r4,chud_970_hior
  95             beq         mfspr64_hior
  96             cmpwi       r4,chud_970_lpidr
  97             beq         mfspr64_lpidr
  98             cmpwi       r4,chud_970_lpcr
  99             beq         mfspr64_lpcr
 100             cmpwi       r4,chud_970_dabrx
 101             beq         mfspr64_dabrx
 102             cmpwi       r4,chud_970_hsprg0
 103             beq         mfspr64_hsprg0
 104             cmpwi       r4,chud_970_hsprg1
 105             beq         mfspr64_hsprg1
 106             cmpwi       r4,chud_970_hsrr0
 107             beq         mfspr64_hsrr0
 108             cmpwi       r4,chud_970_hsrr1
 109             beq         mfspr64_hsrr1
 110             cmpwi       r4,chud_970_hdec
 111             beq         mfspr64_hdec
 112             cmpwi       r4,chud_970_trig0
 113             beq         mfspr64_trig0
 114             cmpwi       r4,chud_970_trig1
 115             beq         mfspr64_trig1
 116             cmpwi       r4,chud_970_trig2
 117             beq         mfspr64_trig2
 118             cmpwi       r4,chud_ppc64_accr
 119             beq         mfspr64_accr
 120             cmpwi       r4,chud_970_scomc
 121             beq         mfspr64_scomc
 122             cmpwi       r4,chud_970_scomd
 123             beq         mfspr64_scomd
 124
 125             b           mfspr64_failure
 126
 127 mfspr64_srr0:
 128             mfspr       r5,chud_ppc_srr0
 129             std         r5,0(r3)
 130             b           mfspr64_success
 131 mfspr64_srr1:
 132             mfspr       r5,chud_ppc_srr1
 133             std         r5,0(r3)
 134             b           mfspr64_success
 135 mfspr64_dar:
 136             mfspr       r5,chud_ppc_dar
 137             std         r5,0(r3)
 138             b           mfspr64_success
 139 mfspr64_sdr1:
 140             mfspr       r5,chud_ppc_sdr1
 141             std         r5,0(r3)
 142             b           mfspr64_success
 143 mfspr64_sprg0:
 144             mfspr       r5,chud_ppc_sprg0
 145             std         r5,0(r3)
 146             b           mfspr64_success
 147 mfspr64_sprg1:
 148             mfspr       r5,chud_ppc_sprg1
 149             std         r5,0(r3)
 150             b           mfspr64_success
 151 mfspr64_sprg2:
 152             mfspr       r5,chud_ppc_sprg2
 153             std         r5,0(r3)
 154             b           mfspr64_success
 155 mfspr64_sprg3:
 156             mfspr       r5,chud_ppc_sprg3
 157             std         r5,0(r3)
 158             b           mfspr64_success
 159 mfspr64_asr:
 160             mfspr       r5,chud_ppc64_asr
 161             std         r5,0(r3)
 162             b           mfspr64_success
 163 mfspr64_dabr:
 164             mfspr       r5,chud_ppc_dabr
 165             std         r5,0(r3)
 166             b           mfspr64_success
 167 mfspr64_hid0:
 168             mfspr       r5,chud_970_hid0
 169             std         r5,0(r3)
 170             b           mfspr64_success
 171 mfspr64_hid1:
 172             mfspr       r5,chud_970_hid1
 173             std         r5,0(r3)
 174             b           mfspr64_success
 175 mfspr64_hid4:
 176             mfspr       r5,chud_970_hid4
 177             std         r5,0(r3)
 178             b           mfspr64_success
 179 mfspr64_hid5:
 180             mfspr       r5,chud_970_hid5
 181             std         r5,0(r3)
 182             b           mfspr64_success
 183 mfspr64_mmcr0:
 184             mfspr       r5,chud_970_mmcr0
 185             std         r5,0(r3)
 186             b           mfspr64_success
 187 mfspr64_mmcr1:
 188             mfspr       r5,chud_970_mmcr1
 189             std         r5,0(r3)
 190             b           mfspr64_success
 191 mfspr64_mmcra:
 192             mfspr       r5,chud_970_mmcra
 193             std         r5,0(r3)
 194             b           mfspr64_success
 195 mfspr64_siar:
 196             mfspr       r5,chud_970_siar
 197             std         r5,0(r3)
 198             b           mfspr64_success
 199 mfspr64_sdar:
 200             mfspr       r5,chud_970_sdar
 201             std         r5,0(r3)
 202             b           mfspr64_success
 203 mfspr64_imc:
 204             mfspr       r5,chud_970_imc
 205             std         r5,0(r3)
 206             b           mfspr64_success
 207 mfspr64_rmor:
 208             mfspr       r5,chud_970_rmor
 209             std         r5,0(r3)
 210             b           mfspr64_success
 211 mfspr64_hrmor:
 212             mfspr       r5,chud_970_hrmor
 213             std         r5,0(r3)
 214             b           mfspr64_success
 215 mfspr64_hior:
 216             mfspr       r5,chud_970_hior
 217             std         r5,0(r3)
 218             b           mfspr64_success
 219 mfspr64_lpidr:
 220             mfspr       r5,chud_970_lpidr
 221             std         r5,0(r3)
 222             b           mfspr64_success
 223 mfspr64_lpcr:
 224             mfspr       r5,chud_970_lpcr
 225             std         r5,0(r3)
 226             b           mfspr64_success
 227 mfspr64_dabrx:
 228             mfspr       r5,chud_970_dabrx
 229             std         r5,0(r3)
 230             b           mfspr64_success
 231 mfspr64_hsprg0:
 232             mfspr       r5,chud_970_hsprg0
 233             std         r5,0(r3)
 234             b           mfspr64_success
 235 mfspr64_hsprg1:
 236             mfspr       r5,chud_970_hsprg1
 237             std         r5,0(r3)
 238             b           mfspr64_success
 239 mfspr64_hsrr0:
 240             mfspr       r5,chud_970_hsrr0
 241             std         r5,0(r3)
 242             b           mfspr64_success
 243 mfspr64_hsrr1:
 244             mfspr       r5,chud_970_hsrr1
 245             std         r5,0(r3)
 246             b           mfspr64_success
 247 mfspr64_hdec:
 248             mfspr       r5,chud_970_hdec
 249             std         r5,0(r3)
 250             b           mfspr64_success
 251 mfspr64_trig0:
 252             mfspr       r5,chud_970_trig0
 253             std         r5,0(r3)
 254             b           mfspr64_success
 255 mfspr64_trig1:
 256             mfspr       r5,chud_970_trig1
 257             std         r5,0(r3)
 258             b           mfspr64_success
 259 mfspr64_trig2:
 260             mfspr       r5,chud_970_trig2
 261             std         r5,0(r3)
 262             b           mfspr64_success
 263 mfspr64_accr:
 264             mfspr       r5,chud_ppc64_accr
 265             std         r5,0(r3)
 266             b           mfspr64_success
 267 mfspr64_scomc:
 268             mfspr       r5,chud_970_scomc
 269             std         r5,0(r3)
 270             b           mfspr64_success
 271 mfspr64_scomd:
 272             mfspr       r5,chud_970_scomd
 273             std         r5,0(r3)
 274             b           mfspr64_success
 275
 276 mfspr64_failure:
 277             li          r3,KERN_FAILURE
 278             blr
 279
 280 mfspr64_success:
 281             li          r3,KERN_SUCCESS
 282             blr
 283
 284
 285 /*
 286  * kern_return_t mtspr64(int spr, uint64_t *val);
 287  *
 288  * r3: spr to write to
 289  * r4: address to get value from
 290  *
 291  */
 292
 293 ;           Force a line boundry here
 294             .align  5
 295             .globl  EXT(mtspr64)
 296
 297 EXT(mtspr64):
 298             ;; generic PPC 64-bit wide SPRs
 299             cmpwi       r3,chud_ppc_srr0
 300             beq         mtspr64_srr0
 301             cmpwi       r3,chud_ppc_srr1
 302             beq         mtspr64_srr1
 303             cmpwi       r3,chud_ppc_dar
 304             beq         mtspr64_dar
 305             cmpwi       r3,chud_ppc_sdr1
 306             beq         mtspr64_sdr1
 307             cmpwi       r3,chud_ppc_sprg0
 308             beq         mtspr64_sprg0
 309             cmpwi       r3,chud_ppc_sprg1
 310             beq         mtspr64_sprg1
 311             cmpwi       r3,chud_ppc_sprg2
 312             beq         mtspr64_sprg2
 313             cmpwi       r3,chud_ppc_sprg3
 314             beq         mtspr64_sprg3
 315             cmpwi       r3,chud_ppc64_asr
 316             beq         mtspr64_asr
 317             cmpwi       r3,chud_ppc_dabr
 318             beq         mtspr64_dabr
 319
 320             ;; GPUL specific 64-bit wide SPRs
 321             cmpwi       r3,chud_970_hid0
 322             beq         mtspr64_hid0
 323             cmpwi       r3,chud_970_hid1
 324             beq         mtspr64_hid1
 325             cmpwi       r3,chud_970_hid4
 326             beq         mtspr64_hid4
 327             cmpwi       r3,chud_970_hid5
 328             beq         mtspr64_hid5
 329             cmpwi       r3,chud_970_mmcr0
 330             beq         mtspr64_mmcr0
 331             cmpwi       r3,chud_970_mmcr1
 332             beq         mtspr64_mmcr1
 333             cmpwi       r3,chud_970_mmcra
 334             beq         mtspr64_mmcra
 335             cmpwi       r3,chud_970_siar
 336             beq         mtspr64_siar
 337             cmpwi       r3,chud_970_sdar
 338             beq         mtspr64_sdar
 339             cmpwi       r3,chud_970_imc
 340             beq         mtspr64_imc
 341             cmpwi       r3,chud_970_rmor
 342             beq         mtspr64_rmor
 343             cmpwi       r3,chud_970_hrmor
 344             beq         mtspr64_hrmor
 345             cmpwi       r3,chud_970_hior
 346             beq         mtspr64_hior
 347             cmpwi       r3,chud_970_lpidr
 348             beq         mtspr64_lpidr
 349             cmpwi       r3,chud_970_lpcr
 350             beq         mtspr64_lpcr
 351             cmpwi       r3,chud_970_dabrx
 352             beq         mtspr64_dabrx
 353             cmpwi       r3,chud_970_hsprg0
 354             beq         mtspr64_hsprg0
 355             cmpwi       r3,chud_970_hsprg1
 356             beq         mtspr64_hsprg1
 357             cmpwi       r3,chud_970_hsrr0
 358             beq         mtspr64_hsrr0
 359             cmpwi       r3,chud_970_hsrr1
 360             beq         mtspr64_hsrr1
 361             cmpwi       r3,chud_970_hdec
 362             beq         mtspr64_hdec
 363             cmpwi       r3,chud_970_trig0
 364             beq         mtspr64_trig0
 365             cmpwi       r3,chud_970_trig1
 366             beq         mtspr64_trig1
 367             cmpwi       r3,chud_970_trig2
 368             beq         mtspr64_trig2
 369             cmpwi       r3,chud_ppc64_accr
 370             beq         mtspr64_accr
 371             cmpwi       r3,chud_970_scomc
 372             beq         mtspr64_scomc
 373             cmpwi       r3,chud_970_scomd
 374             beq         mtspr64_scomd
 375
 376             b           mtspr64_failure
 377
 378 mtspr64_srr0:
 379             ld          r5,0(r4)
 380             mtspr       chud_ppc_srr0,r5
 381             b           mtspr64_success
 382 mtspr64_srr1:
 383             ld          r5,0(r4)
 384             mtspr       chud_ppc_srr1,r5
 385             b           mtspr64_success
 386 mtspr64_dar:
 387             ld          r5,0(r4)
 388             mtspr       chud_ppc_dar,r5
 389             b           mtspr64_success
 390 mtspr64_sdr1:
 391             ld          r5,0(r4)
 392             mtspr       chud_ppc_sdr1,r5
 393             b           mtspr64_success
 394 mtspr64_sprg0:
 395             ld          r5,0(r4)
 396             mtspr       chud_ppc_sprg0,r5
 397             b           mtspr64_success
 398 mtspr64_sprg1:
 399             ld          r5,0(r4)
 400             mtspr       chud_ppc_sprg1,r5
 401             b           mtspr64_success
 402 mtspr64_sprg2:
 403             ld          r5,0(r4)
 404             mtspr       chud_ppc_sprg2,r5
 405             b           mtspr64_success
 406 mtspr64_sprg3:
 407             ld          r5,0(r4)
 408             mtspr       chud_ppc_sprg3,r5
 409             b           mtspr64_success
 410 mtspr64_asr:
 411             ld          r5,0(r4)
 412             mtspr       chud_ppc64_asr,r5
 413             b           mtspr64_success
 414 mtspr64_dabr:
 415             ld          r5,0(r4)
 416             mtspr       chud_ppc_dabr,r5
 417             b           mtspr64_success
 418 mtspr64_hid0:
 419             ld          r5,0(r4)
 420             sync
 421             mtspr       chud_970_hid0,r5
 422             mfspr       r5,chud_970_hid0        /* syncronization requirements */
 423             mfspr       r5,chud_970_hid0
 424             mfspr       r5,chud_970_hid0
 425             mfspr       r5,chud_970_hid0
 426             mfspr       r5,chud_970_hid0
 427             mfspr       r5,chud_970_hid0
 428             b           mtspr64_success
 429 mtspr64_hid1:
 430             ld          r5,0(r4)
 431             mtspr       chud_970_hid1,r5        /* tell you twice */
 432             mtspr       chud_970_hid1,r5
 433             isync
 434             b           mtspr64_success
 435 mtspr64_hid4:
 436             ld          r5,0(r4)
 437             sync                                /* syncronization requirements */
 438             mtspr       chud_970_hid4,r5
 439             isync
 440             b           mtspr64_success
 441 mtspr64_hid5:
 442             ld          r5,0(r4)
 443             mtspr       chud_970_hid5,r5
 444             b           mtspr64_success
 445 mtspr64_mmcr0:
 446             ld          r5,0(r4)
 447             mtspr       chud_970_mmcr0,r5
 448             b           mtspr64_success
 449 mtspr64_mmcr1:
 450             ld          r5,0(r4)
 451             mtspr       chud_970_mmcr1,r5
 452             b           mtspr64_success
 453 mtspr64_mmcra:
 454             ld          r5,0(r4)
 455             mtspr       chud_970_mmcra,r5
 456             b           mtspr64_success
 457 mtspr64_siar:
 458             ld          r5,0(r4)
 459             mtspr       chud_970_siar,r5
 460             b           mtspr64_success
 461 mtspr64_sdar:
 462             ld          r5,0(r4)
 463             mtspr       chud_970_sdar,r5
 464             b           mtspr64_success
 465 mtspr64_imc:
 466             ld          r5,0(r4)
 467             mtspr       chud_970_imc,r5
 468             b           mtspr64_success
 469 mtspr64_rmor:
 470             ld          r5,0(r4)
 471             mtspr       chud_970_rmor,r5
 472             b           mtspr64_success
 473 mtspr64_hrmor:
 474             ld          r5,0(r4)
 475             mtspr       chud_970_hrmor,r5
 476             b           mtspr64_success
 477 mtspr64_hior:
 478             ld          r5,0(r4)
 479             mtspr       chud_970_hior,r5
 480             b           mtspr64_success
 481 mtspr64_lpidr:
 482             ld          r5,0(r4)
 483             mtspr       chud_970_lpidr,r5
 484             b           mtspr64_success
 485 mtspr64_lpcr:
 486             ld          r5,0(r4)
 487             mtspr       chud_970_lpcr,r5
 488             b           mtspr64_success
 489 mtspr64_dabrx:
 490             ld          r5,0(r4)
 491             mtspr       chud_970_dabrx,r5
 492             b           mtspr64_success
 493 mtspr64_hsprg0:
 494             ld          r5,0(r4)
 495             mtspr       chud_970_hsprg0,r5
 496             b           mtspr64_success
 497 mtspr64_hsprg1:
 498             ld          r5,0(r4)
 499             mtspr       chud_970_hsprg1,r5
 500             b           mtspr64_success
 501 mtspr64_hsrr0:
 502             ld          r5,0(r4)
 503             mtspr       chud_970_hsrr0,r5
 504             b           mtspr64_success
 505 mtspr64_hsrr1:
 506             ld          r5,0(r4)
 507             mtspr       chud_970_hsrr1,r5
 508             b           mtspr64_success
 509 mtspr64_hdec:
 510             ld          r5,0(r4)
 511             mtspr       chud_970_hdec,r5
 512             b           mtspr64_success
 513 mtspr64_trig0:
 514             ld          r5,0(r4)
 515             mtspr       chud_970_trig0,r5
 516             b           mtspr64_success
 517 mtspr64_trig1:
 518             ld          r5,0(r4)
 519             mtspr       chud_970_trig1,r5
 520             b           mtspr64_success
 521 mtspr64_trig2:
 522             ld          r5,0(r4)
 523             mtspr       chud_970_trig2,r5
 524             b           mtspr64_success
 525 mtspr64_accr:
 526             ld          r5,0(r4)
 527             mtspr       chud_ppc64_accr,r5
 528             b           mtspr64_success
 529 mtspr64_scomc:
 530             ld          r5,0(r4)
 531             mtspr       chud_970_scomc,r5
 532             b           mtspr64_success
 533 mtspr64_scomd:
 534             ld          r5,0(r4)
 535             mtspr       chud_970_scomd,r5
 536             b           mtspr64_success
 537
 538 mtspr64_failure:
 539             li          r3,KERN_FAILURE
 540             blr
 541
 542 mtspr64_success:
 543             li          r3,KERN_SUCCESS
 544             blr
 545
 546
 547 /*
 548  * kern_return_t mfmsr64(uint64_t *val);
 549  *
 550  * r3: address to store value in
 551  *
 552  */
 553
 554 ;           Force a line boundry here
 555             .align  5
 556             .globl  EXT(mfmsr64)
 557
 558 EXT(mfmsr64):
 559             mfmsr       r5
 560             std         r5,0(r3)
 561 mfmsr64_success:
 562             li          r3,KERN_SUCCESS
 563             blr
 564
 565 mfmsr64_failure:
 566             li          r3,KERN_FAILURE
 567             blr
 568
 569
 570 /*
 571  * kern_return_t mtmsr64(uint64_t *val);
 572  *
 573  * r3: address to load value from
 574  *
 575  */
 576
 577 ;           Force a line boundry here
 578             .align  5
 579             .globl  EXT(mtmsr64)
 580
 581 EXT(mtmsr64):
 582             ld          r5,0(r3)
 583             mtmsrd      r5
 584             b           mtmsr64_success
 585
 586 mtmsr64_success:
 587             li          r3,KERN_SUCCESS
 588             blr
 589
 590 mtmsr64_failure:
 591             li          r3,KERN_FAILURE
 592             blr
 593
 594 .L_end: