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[apple/xnu.git] / osfmk / i386 / cpuid.c
1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_COPYRIGHT@
24 */
25 #include <platforms.h>
26 #include <mach_kdb.h>
27 #include <pexpert/pexpert.h>
28
29 #include "cpuid.h"
30 #if MACH_KDB
31 #include <i386/db_machdep.h>
32 #include <ddb/db_aout.h>
33 #include <ddb/db_access.h>
34 #include <ddb/db_sym.h>
35 #include <ddb/db_variables.h>
36 #include <ddb/db_command.h>
37 #include <ddb/db_output.h>
38 #include <ddb/db_expr.h>
39 #endif
40
41 #define min(a,b) ((a) < (b) ? (a) : (b))
42 #define quad(hi,lo) (((uint64_t)(hi)) << 32 | (lo))
43
44 #define bit(n) (1UL << (n))
45 #define bitmask(h,l) ((bit(h)|(bit(h)-1)) & ~(bit(l)-1))
46 #define bitfield(x,h,l) (((x) & bitmask(h,l)) >> l)
47
48 /*
49 * CPU identification routines.
50 *
51 * Note that this code assumes a processor that supports the
52 * 'cpuid' instruction.
53 */
54
55 static unsigned int cpuid_maxcpuid;
56
57 static i386_cpu_info_t cpuid_cpu_info;
58
59 uint32_t cpuid_feature; /* XXX obsolescent for compat */
60
61 /*
62 * We only identify Intel CPUs here. Adding support
63 * for others would be straightforward.
64 */
65 static void set_cpu_generic(i386_cpu_info_t *);
66 static void set_cpu_intel(i386_cpu_info_t *);
67 static void set_cpu_amd(i386_cpu_info_t *);
68 static void set_cpu_nsc(i386_cpu_info_t *);
69 static void set_cpu_unknown(i386_cpu_info_t *);
70
71 struct {
72 const char *vendor;
73 void (* func)(i386_cpu_info_t *);
74 } cpu_vendors[] = {
75 {CPUID_VID_INTEL, set_cpu_intel},
76 {CPUID_VID_AMD, set_cpu_amd},
77 {CPUID_VID_NSC, set_cpu_nsc},
78 {0, set_cpu_unknown}
79 };
80
81 void
82 cpuid_get_info(i386_cpu_info_t *info_p)
83 {
84 uint32_t cpuid_result[4];
85 int i;
86
87 bzero((void *)info_p, sizeof(i386_cpu_info_t));
88
89 /* do cpuid 0 to get vendor */
90 do_cpuid(0, cpuid_result);
91 cpuid_maxcpuid = cpuid_result[eax];
92 bcopy((char *)&cpuid_result[ebx], &info_p->cpuid_vendor[0], 4); /* ug */
93 bcopy((char *)&cpuid_result[ecx], &info_p->cpuid_vendor[8], 4);
94 bcopy((char *)&cpuid_result[edx], &info_p->cpuid_vendor[4], 4);
95 info_p->cpuid_vendor[12] = 0;
96
97 /* look up vendor */
98 for (i = 0; ; i++) {
99 if ((cpu_vendors[i].vendor == 0) ||
100 (!strcmp(cpu_vendors[i].vendor, info_p->cpuid_vendor))) {
101 cpu_vendors[i].func(info_p);
102 break;
103 }
104 }
105 }
106
107 /*
108 * Cache descriptor table. Each row has the form:
109 * (descriptor_value, cache, size, linesize,
110 * description)
111 * Note: the CACHE_DESC macro does not expand description text in the kernel.
112 */
113 static cpuid_cache_desc_t cpuid_cache_desc_tab[] = {
114 CACHE_DESC(CPUID_CACHE_ITLB_4K, Lnone, 0, 0, \
115 "Instruction TLB, 4K, pages 4-way set associative, 64 entries"),
116 CACHE_DESC(CPUID_CACHE_ITLB_4M, Lnone, 0, 0, \
117 "Instruction TLB, 4M, pages 4-way set associative, 2 entries"),
118 CACHE_DESC(CPUID_CACHE_DTLB_4K, Lnone, 0, 0, \
119 "Data TLB, 4K pages, 4-way set associative, 64 entries"),
120 CACHE_DESC(CPUID_CACHE_DTLB_4M, Lnone, 0, 0, \
121 "Data TLB, 4M pages, 4-way set associative, 8 entries"),
122 CACHE_DESC(CPUID_CACHE_ITLB_64, Lnone, 0, 0, \
123 "Instruction TLB, 4K and 2M or 4M pages, 64 entries"),
124 CACHE_DESC(CPUID_CACHE_ITLB_128, Lnone, 0, 0, \
125 "Instruction TLB, 4K and 2M or 4M pages, 128 entries"),
126 CACHE_DESC(CPUID_CACHE_ITLB_256, Lnone, 0, 0, \
127 "Instruction TLB, 4K and 2M or 4M pages, 256 entries"),
128 CACHE_DESC(CPUID_CACHE_DTLB_64, Lnone, 0, 0, \
129 "Data TLB, 4K and 4M pages, 64 entries"),
130 CACHE_DESC(CPUID_CACHE_DTLB_128, Lnone, 0, 0, \
131 "Data TLB, 4K and 4M pages, 128 entries"),
132 CACHE_DESC(CPUID_CACHE_DTLB_256, Lnone, 0, 0, \
133 "Data TLB, 4K and 4M pages, 256 entries"),
134 CACHE_DESC(CPUID_CACHE_ITLB_128_4, Lnone, 0, 0, \
135 "Instruction TLB, 4K pages, 4-way set associative, 128 entries"),
136 CACHE_DESC(CPUID_CACHE_DTLB_128_4, Lnone, 0, 0, \
137 "Data TLB, 4K pages, 4-way set associative, 128 entries"),
138 CACHE_DESC(CPUID_CACHE_ICACHE_8K, L1I, 8*1024, 32, \
139 "Instruction L1 cache, 8K, 4-way set associative, 32byte line size"),
140 CACHE_DESC(CPUID_CACHE_DCACHE_8K, L1D, 8*1024, 32, \
141 "Data L1 cache, 8K, 2-way set associative, 32byte line size"),
142 CACHE_DESC(CPUID_CACHE_ICACHE_16K, L1I, 16*1024, 32, \
143 "Instruction L1 cache, 16K, 4-way set associative, 32byte line size"),
144 CACHE_DESC(CPUID_CACHE_DCACHE_16K, L1D, 16*1024, 32, \
145 "Data L1 cache, 16K, 4-way set associative, 32byte line size"),
146 CACHE_DESC(CPUID_CACHE_DCACHE_8K_64, L1D, 8*1024, 64, \
147 "Data L1 cache, 8K, 4-way set associative, 64byte line size"),
148 CACHE_DESC(CPUID_CACHE_DCACHE_16K_64, L1D, 16*1024, 64, \
149 "Data L1 cache, 16K, 4-way set associative, 64byte line size"),
150 CACHE_DESC(CPUID_CACHE_DCACHE_32K_64, L1D, 32*1024, 64, \
151 "Data L1 cache, 32K, 4-way set associative, 64byte line size"),
152 CACHE_DESC(CPUID_CACHE_DCACHE_32K, L1D, 32*1024, 64, \
153 "Data L1 cache, 32K, 8-way set assocative, 64byte line size"),
154 CACHE_DESC(CPUID_CACHE_ICACHE_32K, L1I, 32*1024, 64, \
155 "Instruction L1 cache, 32K, 8-way set associative, 64byte line size"),
156 CACHE_DESC(CPUID_CACHE_DCACHE_16K_8, L1D, 16*1024, 64, \
157 "Data L1 cache, 16K, 8-way set associative, 64byte line size"),
158 CACHE_DESC(CPUID_CACHE_TRACE_12K, L1I, 12*1024, 64, \
159 "Trace cache, 12K-uop, 8-way set associative"),
160 CACHE_DESC(CPUID_CACHE_TRACE_16K, L1I, 16*1024, 64, \
161 "Trace cache, 16K-uop, 8-way set associative"),
162 CACHE_DESC(CPUID_CACHE_TRACE_32K, L1I, 32*1024, 64, \
163 "Trace cache, 32K-uop, 8-way set associative"),
164 CACHE_DESC(CPUID_CACHE_UCACHE_128K, L2U, 128*1024, 32, \
165 "Unified L2 cache, 128K, 4-way set associative, 32byte line size"),
166 CACHE_DESC(CPUID_CACHE_UCACHE_256K, L2U, 128*1024, 32, \
167 "Unified L2 cache, 256K, 4-way set associative, 32byte line size"),
168 CACHE_DESC(CPUID_CACHE_UCACHE_512K, L2U, 512*1024, 32, \
169 "Unified L2 cache, 512K, 4-way set associative, 32byte line size"),
170 CACHE_DESC(CPUID_CACHE_UCACHE_1M, L2U, 1*1024*1024, 32, \
171 "Unified L2 cache, 1M, 4-way set associative, 32byte line size"),
172 CACHE_DESC(CPUID_CACHE_UCACHE_2M, L2U, 2*1024*1024, 32, \
173 "Unified L2 cache, 2M, 4-way set associative, 32byte line size"),
174 CACHE_DESC(CPUID_CACHE_UCACHE_4M, L2U, 4*1024*1024, 64, \
175 "Unified L2 cache, 4M, 16-way set associative, 64byte line size"),
176 CACHE_DESC(CPUID_CACHE_UCACHE_128K_64, L2U, 128*1024, 64, \
177 "Unified L2 cache, 128K, 8-way set associative, 64byte line size"),
178 CACHE_DESC(CPUID_CACHE_UCACHE_256K_64, L2U, 256*1024, 64, \
179 "Unified L2 cache, 256K, 8-way set associative, 64byte line size"),
180 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64, L2U, 512*1024, 64, \
181 "Unified L2 cache, 512K, 8-way set associative, 64byte line size"),
182 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64, L2U, 1*1024*1024, 64, \
183 "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
184 CACHE_DESC(CPUID_CACHE_UCACHE_256K_32, L2U, 256*1024, 32, \
185 "Unified L2 cache, 256K, 8-way set associative, 32byte line size"),
186 CACHE_DESC(CPUID_CACHE_UCACHE_512K_32, L2U, 512*1024, 32, \
187 "Unified L2 cache, 512K, 8-way set associative, 32byte line size"),
188 CACHE_DESC(CPUID_CACHE_UCACHE_1M_32, L2U, 1*1024*1024, 32, \
189 "Unified L2 cache, 1M, 8-way set associative, 32byte line size"),
190 CACHE_DESC(CPUID_CACHE_UCACHE_2M_32, L2U, 2*1024*1024, 32, \
191 "Unified L2 cache, 2M, 8-way set associative, 32byte line size"),
192 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_4, L2U, 1*1024*1024, 64, \
193 "Unified L2 cache, 1M, 4-way set associative, 64byte line size"),
194 CACHE_DESC(CPUID_CACHE_UCACHE_2M_64, L2U, 2*1024*1024, 64, \
195 "Unified L2 cache, 2M, 8-way set associative, 64byte line size"),
196 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_2,L2U, 512*1024, 64, \
197 "Unified L2 cache, 512K, 2-way set associative, 64byte line size"),
198 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_4,L2U, 512*1024, 64, \
199 "Unified L2 cache, 512K, 4-way set associative, 64byte line size"),
200 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_8, L2U, 1*1024*1024, 64, \
201 "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
202 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S4, L2U, 128*1024, 64, \
203 "Unified L2 sectored cache, 128K, 4-way set associative, 64byte line size"),
204 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S2, L2U, 128*1024, 64, \
205 "Unified L2 sectored cache, 128K, 2-way set associative, 64byte line size"),
206 CACHE_DESC(CPUID_CACHE_UCACHE_256K_S4, L2U, 256*1024, 64, \
207 "Unified L2 sectored cache, 256K, 4-way set associative, 64byte line size"),
208 CACHE_DESC(CPUID_CACHE_L3CACHE_512K, L3U, 512*1024, 64, \
209 "Unified L3 cache, 512K, 4-way set associative, 64byte line size"),
210 CACHE_DESC(CPUID_CACHE_L3CACHE_1M, L3U, 1*1024*1024, 64, \
211 "Unified L3 cache, 1M, 8-way set associative, 64byte line size"),
212 CACHE_DESC(CPUID_CACHE_L3CACHE_2M, L3U, 2*1024*1024, 64, \
213 "Unified L3 cache, 2M, 8-way set associative, 64byte line size"),
214 CACHE_DESC(CPUID_CACHE_L3CACHE_4M, L3U, 4*1024*1024, 64, \
215 "Unified L3 cache, 4M, 8-way set associative, 64byte line size"),
216 CACHE_DESC(CPUID_CACHE_PREFETCH_64, Lnone, 0, 0, \
217 "64-Byte Prefetching"),
218 CACHE_DESC(CPUID_CACHE_PREFETCH_128, Lnone, 0, 0, \
219 "128-Byte Prefetching"),
220 CACHE_DESC(CPUID_CACHE_NOCACHE, Lnone, 0, 0, \
221 "No L2 cache or, if valid L2 cache, no L3 cache"),
222 CACHE_DESC(CPUID_CACHE_NULL, Lnone, 0, 0, \
223 (char *)0),
224 };
225
226 static const char * get_intel_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype)
227 {
228 *type = CPU_TYPE_X86;
229 *subtype = CPU_SUBTYPE_X86_ARCH1;
230
231 /* check for brand id string */
232 switch(info_p->cpuid_brand) {
233 case CPUID_BRAND_UNSUPPORTED:
234 /* brand ID not supported; use alternate method. */
235 switch(info_p->cpuid_family) {
236 case CPUID_FAMILY_486:
237 return "Intel 486";
238 case CPUID_FAMILY_586:
239 return "Intel Pentium";
240 case CPUID_FAMILY_686:
241 switch(info_p->cpuid_model) {
242 case CPUID_MODEL_P6:
243 return "Intel Pentium Pro";
244 case CPUID_MODEL_PII:
245 return "Intel Pentium II";
246 case CPUID_MODEL_P65:
247 case CPUID_MODEL_P66:
248 return "Intel Celeron";
249 case CPUID_MODEL_P67:
250 case CPUID_MODEL_P68:
251 case CPUID_MODEL_P6A:
252 case CPUID_MODEL_P6B:
253 return "Intel Pentium III";
254 case CPUID_MODEL_PM9:
255 case CPUID_MODEL_PMD:
256 return "Intel Pentium M";
257 default:
258 return "Unknown Intel P6 Family";
259 }
260 case CPUID_FAMILY_EXTENDED:
261 switch (info_p->cpuid_extfamily) {
262 case CPUID_EXTFAMILY_PENTIUM4:
263 *subtype = CPU_SUBTYPE_PENTIUM_4;
264 return "Intel Pentium 4";
265 default:
266 return "Unknown Intel Extended Family";
267 }
268 default:
269 return "Unknown Intel Family";
270 }
271 break;
272 case CPUID_BRAND_CELERON_1:
273 case CPUID_BRAND_CELERON_A:
274 case CPUID_BRAND_CELERON_14:
275 return "Intel Celeron";
276 case CPUID_BRAND_PENTIUM_III_2:
277 case CPUID_BRAND_PENTIUM_III_4:
278 return "Pentium III";
279 case CPUID_BRAND_PIII_XEON:
280 if (info_p->cpuid_signature == 0x6B1) {
281 return "Intel Celeron";
282 } else {
283 return "Intel Pentium III Xeon";
284 }
285 case CPUID_BRAND_PENTIUM_III_M:
286 return "Mobile Intel Pentium III-M";
287 case CPUID_BRAND_M_CELERON_7:
288 case CPUID_BRAND_M_CELERON_F:
289 case CPUID_BRAND_M_CELERON_13:
290 case CPUID_BRAND_M_CELERON_17:
291 return "Mobile Intel Celeron";
292 case CPUID_BRAND_PENTIUM4_8:
293 case CPUID_BRAND_PENTIUM4_9:
294 *subtype = CPU_SUBTYPE_PENTIUM_4;
295 return "Intel Pentium 4";
296 case CPUID_BRAND_XEON:
297 return "Intel Xeon";
298 case CPUID_BRAND_XEON_MP:
299 return "Intel Xeon MP";
300 case CPUID_BRAND_PENTIUM4_M:
301 if (info_p->cpuid_signature == 0xF13) {
302 return "Intel Xeon";
303 } else {
304 *subtype = CPU_SUBTYPE_PENTIUM_4;
305 return "Mobile Intel Pentium 4";
306 }
307 case CPUID_BRAND_CELERON_M:
308 return "Intel Celeron M";
309 case CPUID_BRAND_PENTIUM_M:
310 return "Intel Pentium M";
311 case CPUID_BRAND_MOBILE_15:
312 case CPUID_BRAND_MOBILE_17:
313 return "Mobile Intel";
314 }
315 return "Unknown Intel";
316 }
317
318 static void set_intel_cache_info( i386_cpu_info_t * info_p )
319 {
320 uint32_t cpuid_result[4];
321 uint32_t l1d_cache_linesize = 0;
322 unsigned int i;
323 unsigned int j;
324
325 /* get processor cache descriptor info */
326 do_cpuid(2, cpuid_result);
327 for (j = 0; j < 4; j++) {
328 if ((cpuid_result[j] >> 31) == 1) /* bit31 is validity */
329 continue;
330 ((uint32_t *) info_p->cache_info)[j] = cpuid_result[j];
331 }
332 /* first byte gives number of cpuid calls to get all descriptors */
333 for (i = 1; i < info_p->cache_info[0]; i++) {
334 if (i*16 > sizeof(info_p->cache_info))
335 break;
336 do_cpuid(2, cpuid_result);
337 for (j = 0; j < 4; j++) {
338 if ((cpuid_result[j] >> 31) == 1)
339 continue;
340 ((uint32_t *) info_p->cache_info)[4*i+j] =
341 cpuid_result[j];
342 }
343 }
344
345 /* decode the descriptors looking for L1/L2/L3 size info */
346 for (i = 1; i < sizeof(info_p->cache_info); i++) {
347 cpuid_cache_desc_t *descp;
348 uint8_t desc = info_p->cache_info[i];
349
350 if (desc == CPUID_CACHE_NULL)
351 continue;
352 for (descp = cpuid_cache_desc_tab;
353 descp->value != CPUID_CACHE_NULL; descp++) {
354 if (descp->value != desc)
355 continue;
356 info_p->cache_size[descp->type] = descp->size;
357 if (descp->type == L2U)
358 info_p->cache_linesize = descp->linesize;
359 if (descp->type == L1D)
360 l1d_cache_linesize = descp->linesize;
361 break;
362 }
363 }
364 /* For P-IIIs, L2 could be 256k or 512k but we can't tell */
365 if (info_p->cache_size[L2U] == 0 &&
366 info_p->cpuid_family == 0x6 && info_p->cpuid_model == 0xb) {
367 info_p->cache_size[L2U] = 256*1024;
368 info_p->cache_linesize = 32;
369 }
370 /* If we have no L2 cache, use the L1 data cache line size */
371 if (info_p->cache_size[L2U] == 0)
372 info_p->cache_linesize = l1d_cache_linesize;
373
374 /*
375 * Get cache sharing info if available.
376 */
377 do_cpuid(0, cpuid_result);
378 if (cpuid_result[eax] >= 4) {
379 uint32_t reg[4];
380 uint32_t index;
381 for (index = 0;; index++) {
382 /*
383 * Scan making calls for cpuid with %eax = 4
384 * to get info about successive cache levels
385 * until a null type is returned.
386 */
387 cache_type_t type = Lnone;
388 uint32_t cache_type;
389 uint32_t cache_level;
390 uint32_t cache_sharing;
391
392 reg[eax] = 4; /* cpuid request 4 */
393 reg[ecx] = index; /* index starting at 0 */
394 cpuid(reg);
395 //kprintf("cpuid(4) index=%d eax=%p\n", index, reg[eax]);
396 cache_type = bitfield(reg[eax], 4, 0);
397 if (cache_type == 0)
398 break; /* done with cache info */
399 cache_level = bitfield(reg[eax], 7, 5);
400 cache_sharing = bitfield(reg[eax], 25, 14);
401 info_p->cpuid_cores_per_package =
402 bitfield(reg[eax], 31, 26) + 1;
403 switch (cache_level) {
404 case 1:
405 type = cache_type == 1 ? L1D :
406 cache_type == 2 ? L1I :
407 Lnone;
408 break;
409 case 2:
410 type = cache_type == 3 ? L2U :
411 Lnone;
412 break;
413 case 3:
414 type = cache_type == 3 ? L3U :
415 Lnone;
416 }
417 if (type != Lnone)
418 info_p->cache_sharing[type] = cache_sharing + 1;
419 }
420 }
421 }
422
423 static void set_cpu_intel( i386_cpu_info_t * info_p )
424 {
425 set_cpu_generic(info_p);
426 set_intel_cache_info(info_p);
427 info_p->cpuid_model_string = get_intel_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype);
428 }
429
430 static const char * get_amd_model_string( i386_cpu_info_t * info_p, cpu_type_t* type, cpu_subtype_t* subtype )
431 {
432 *type = CPU_TYPE_X86;
433 *subtype = CPU_SUBTYPE_X86_ARCH1;
434
435 /* check for brand id string */
436 switch (info_p->cpuid_family)
437 {
438 case CPUID_FAMILY_486:
439 switch (info_p->cpuid_model) {
440 case CPUID_MODEL_AM486_DX:
441 case CPUID_MODEL_AM486_DX2:
442 case CPUID_MODEL_AM486_DX2WB:
443 case CPUID_MODEL_AM486_DX4:
444 case CPUID_MODEL_AM486_DX4WB:
445 return "Am486";
446 case CPUID_MODEL_AM486_5X86:
447 case CPUID_MODEL_AM486_5X86WB:
448 return "Am5x86";
449 }
450 break;
451 case CPUID_FAMILY_586:
452 switch (info_p->cpuid_model) {
453 case CPUID_MODEL_K5M0:
454 case CPUID_MODEL_K5M1:
455 case CPUID_MODEL_K5M2:
456 case CPUID_MODEL_K5M3:
457 return "AMD-K5";
458 case CPUID_MODEL_K6M6:
459 case CPUID_MODEL_K6M7:
460 return "AMD-K6";
461 case CPUID_MODEL_K6_2:
462 return "AMD-K6-2";
463 case CPUID_MODEL_K6_III:
464 return "AMD-K6-III";
465 }
466 break;
467 case CPUID_FAMILY_686:
468 switch (info_p->cpuid_model) {
469 case CPUID_MODEL_ATHLON_M1:
470 case CPUID_MODEL_ATHLON_M2:
471 case CPUID_MODEL_ATHLON_M4:
472 case CPUID_MODEL_ATHLON_M6:
473 case CPUID_MODEL_ATHLON_M8:
474 case CPUID_MODEL_ATHLON_M10:
475 return "AMD Athlon";
476 case CPUID_MODEL_DURON_M3:
477 case CPUID_MODEL_DURON_M7:
478 return "AMD Duron";
479 default:
480 return "Unknown AMD Athlon";
481 }
482 case CPUID_FAMILY_EXTENDED:
483 switch (info_p->cpuid_model) {
484 case CPUID_MODEL_ATHLON64:
485 return "AMD Athlon 64";
486 case CPUID_MODEL_OPTERON:
487 return "AMD Opteron";
488 default:
489 return "Unknown AMD-64";
490 }
491 }
492 return "Unknown AMD";
493 }
494
495 static void set_amd_cache_info( i386_cpu_info_t * info_p )
496 {
497 uint32_t cpuid_result[4];
498
499 /* It would make sense to fill in info_p->cache_info with complete information
500 * on the TLBs and data cache associativity, lines, etc, either by mapping
501 * to the Intel tags (if possible), or replacing cache_info with a generic
502 * mechanism. But right now, nothing makes use of that information (that I know
503 * of).
504 */
505
506 /* L1 Cache and TLB Information */
507 do_cpuid(0x80000005, cpuid_result);
508
509 /* EAX: TLB Information for 2-Mbyte and 4-MByte Pages */
510 /* (ignore) */
511
512 /* EBX: TLB Information for 4-Kbyte Pages */
513 /* (ignore) */
514
515 /* ECX: L1 Data Cache Information */
516 info_p->cache_size[L1D] = ((cpuid_result[ecx] >> 24) & 0xFF) * 1024;
517 info_p->cache_linesize = (cpuid_result[ecx] & 0xFF);
518
519 /* EDX: L1 Instruction Cache Information */
520 info_p->cache_size[L1I] = ((cpuid_result[edx] >> 24) & 0xFF) * 1024;
521
522 /* L2 Cache Information */
523 do_cpuid(0x80000006, cpuid_result);
524
525 /* EAX: L2 TLB Information for 2-Mbyte and 4-Mbyte Pages */
526 /* (ignore) */
527
528 /* EBX: L2 TLB Information for 4-Kbyte Pages */
529 /* (ignore) */
530
531 /* ECX: L2 Cache Information */
532 info_p->cache_size[L2U] = ((cpuid_result[ecx] >> 16) & 0xFFFF) * 1024;
533 if (info_p->cache_size[L2U] > 0)
534 info_p->cache_linesize = cpuid_result[ecx] & 0xFF;
535 }
536
537 static void set_cpu_amd( i386_cpu_info_t * info_p )
538 {
539 set_cpu_generic(info_p);
540 set_amd_cache_info(info_p);
541 info_p->cpuid_model_string = get_amd_model_string(info_p, &info_p->cpuid_cpu_type, &info_p->cpuid_cpu_subtype);
542 }
543
544 static void set_cpu_nsc( i386_cpu_info_t * info_p )
545 {
546 set_cpu_generic(info_p);
547 set_amd_cache_info(info_p);
548
549 /* check for brand id string */
550 if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX1) {
551 info_p->cpuid_model_string = "AMD Geode GX1";
552 } else if (info_p->cpuid_family == CPUID_FAMILY_586 && info_p->cpuid_model == CPUID_MODEL_GX2) {
553 info_p->cpuid_model_string = "AMD Geode GX";
554 } else {
555 info_p->cpuid_model_string = "Unknown National Semiconductor";
556 }
557 info_p->cpuid_cpu_type = CPU_TYPE_X86;
558 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1;
559 }
560
561 static void
562 set_cpu_generic(i386_cpu_info_t *info_p)
563 {
564 uint32_t cpuid_result[4];
565 uint32_t max_extid;
566 char str[128], *p;
567
568 /* get extended cpuid results */
569 do_cpuid(0x80000000, cpuid_result);
570 max_extid = cpuid_result[eax];
571
572 /* check to see if we can get brand string */
573 if (max_extid >= 0x80000004) {
574 /*
575 * The brand string 48 bytes (max), guaranteed to
576 * be NUL terminated.
577 */
578 do_cpuid(0x80000002, cpuid_result);
579 bcopy((char *)cpuid_result, &str[0], 16);
580 do_cpuid(0x80000003, cpuid_result);
581 bcopy((char *)cpuid_result, &str[16], 16);
582 do_cpuid(0x80000004, cpuid_result);
583 bcopy((char *)cpuid_result, &str[32], 16);
584 for (p = str; *p != '\0'; p++) {
585 if (*p != ' ') break;
586 }
587 strncpy(info_p->cpuid_brand_string,
588 p, sizeof(info_p->cpuid_brand_string)-1);
589 info_p->cpuid_brand_string[sizeof(info_p->cpuid_brand_string)-1] = '\0';
590
591 if (!strcmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN)) {
592 /*
593 * This string means we have a BIOS-programmable brand string,
594 * and the BIOS couldn't figure out what sort of CPU we have.
595 */
596 info_p->cpuid_brand_string[0] = '\0';
597 }
598 }
599
600 /* get processor signature and decode */
601 do_cpuid(1, cpuid_result);
602 info_p->cpuid_signature = cpuid_result[eax];
603 info_p->cpuid_stepping = bitfield(cpuid_result[eax], 3, 0);
604 info_p->cpuid_model = bitfield(cpuid_result[eax], 7, 4);
605 info_p->cpuid_family = bitfield(cpuid_result[eax], 11, 8);
606 info_p->cpuid_type = bitfield(cpuid_result[eax], 13, 12);
607 info_p->cpuid_extmodel = bitfield(cpuid_result[eax], 19, 16);
608 info_p->cpuid_extfamily = bitfield(cpuid_result[eax], 27, 20);
609 info_p->cpuid_brand = bitfield(cpuid_result[ebx], 7, 0);
610 info_p->cpuid_logical_per_package =
611 bitfield(cpuid_result[ebx], 23, 16);
612 info_p->cpuid_features = quad(cpuid_result[ecx], cpuid_result[edx]);
613
614 if (max_extid >= 0x80000001) {
615 do_cpuid(0x80000001, cpuid_result);
616 info_p->cpuid_extfeatures =
617 quad(cpuid_result[ecx], cpuid_result[edx]);
618 }
619
620 return;
621 }
622
623 static void
624 set_cpu_unknown(__unused i386_cpu_info_t *info_p)
625 {
626 info_p->cpuid_model_string = "Unknown";
627 }
628
629
630 static struct {
631 uint64_t mask;
632 const char *name;
633 } feature_map[] = {
634 {CPUID_FEATURE_FPU, "FPU",},
635 {CPUID_FEATURE_VME, "VME",},
636 {CPUID_FEATURE_DE, "DE",},
637 {CPUID_FEATURE_PSE, "PSE",},
638 {CPUID_FEATURE_TSC, "TSC",},
639 {CPUID_FEATURE_MSR, "MSR",},
640 {CPUID_FEATURE_PAE, "PAE",},
641 {CPUID_FEATURE_MCE, "MCE",},
642 {CPUID_FEATURE_CX8, "CX8",},
643 {CPUID_FEATURE_APIC, "APIC",},
644 {CPUID_FEATURE_SEP, "SEP",},
645 {CPUID_FEATURE_MTRR, "MTRR",},
646 {CPUID_FEATURE_PGE, "PGE",},
647 {CPUID_FEATURE_MCA, "MCA",},
648 {CPUID_FEATURE_CMOV, "CMOV",},
649 {CPUID_FEATURE_PAT, "PAT",},
650 {CPUID_FEATURE_PSE36, "PSE36",},
651 {CPUID_FEATURE_PSN, "PSN",},
652 {CPUID_FEATURE_CLFSH, "CLFSH",},
653 {CPUID_FEATURE_DS, "DS",},
654 {CPUID_FEATURE_ACPI, "ACPI",},
655 {CPUID_FEATURE_MMX, "MMX",},
656 {CPUID_FEATURE_FXSR, "FXSR",},
657 {CPUID_FEATURE_SSE, "SSE",},
658 {CPUID_FEATURE_SSE2, "SSE2",},
659 {CPUID_FEATURE_SS, "SS",},
660 {CPUID_FEATURE_HTT, "HTT",},
661 {CPUID_FEATURE_TM, "TM",},
662 {CPUID_FEATURE_SSE3, "SSE3"},
663 {CPUID_FEATURE_MONITOR, "MON"},
664 {CPUID_FEATURE_DSCPL, "DSCPL"},
665 {CPUID_FEATURE_VMX, "VMX"},
666 {CPUID_FEATURE_SMX, "SMX"},
667 {CPUID_FEATURE_EST, "EST"},
668 {CPUID_FEATURE_TM2, "TM2"},
669 {CPUID_FEATURE_MNI, "MNI"},
670 {CPUID_FEATURE_CID, "CID"},
671 {CPUID_FEATURE_CX16, "CX16"},
672 {CPUID_FEATURE_xTPR, "TPR"},
673 {0, 0}
674 },
675 extfeature_map[] = {
676 {CPUID_EXTFEATURE_SYSCALL, "SYSCALL"},
677 {CPUID_EXTFEATURE_XD, "XD"},
678 {CPUID_EXTFEATURE_EM64T, "EM64T"},
679 {CPUID_EXTFEATURE_LAHF, "LAHF"},
680 {0, 0}
681 };
682
683 char *
684 cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len)
685 {
686 int len = -1;
687 char *p = buf;
688 int i;
689
690 for (i = 0; feature_map[i].mask != 0; i++) {
691 if ((features & feature_map[i].mask) == 0)
692 continue;
693 if (len > 0)
694 *p++ = ' ';
695 len = min(strlen(feature_map[i].name), (buf_len-1) - (p-buf));
696 if (len == 0)
697 break;
698 bcopy(feature_map[i].name, p, len);
699 p += len;
700 }
701 *p = '\0';
702 return buf;
703 }
704
705 char *
706 cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len)
707 {
708 int len = -1;
709 char *p = buf;
710 int i;
711
712 for (i = 0; extfeature_map[i].mask != 0; i++) {
713 if ((extfeatures & extfeature_map[i].mask) == 0)
714 continue;
715 if (len > 0)
716 *p++ = ' ';
717 len = min(strlen(extfeature_map[i].name), (buf_len-1)-(p-buf));
718 if (len == 0)
719 break;
720 bcopy(extfeature_map[i].name, p, len);
721 p += len;
722 }
723 *p = '\0';
724 return buf;
725 }
726
727 void
728 cpuid_feature_display(
729 const char *header)
730 {
731 char buf[256];
732
733 kprintf("%s: %s\n", header,
734 cpuid_get_feature_names(cpuid_features(),
735 buf, sizeof(buf)));
736 if (cpuid_features() & CPUID_FEATURE_HTT) {
737 #define s_if_plural(n) ((n > 1) ? "s" : "")
738 kprintf(" HTT: %d core%s per package;"
739 " %d logical cpu%s per package\n",
740 cpuid_cpu_info.cpuid_cores_per_package,
741 s_if_plural(cpuid_cpu_info.cpuid_cores_per_package),
742 cpuid_cpu_info.cpuid_logical_per_package,
743 s_if_plural(cpuid_cpu_info.cpuid_logical_per_package));
744 }
745 }
746
747 void
748 cpuid_extfeature_display(
749 const char *header)
750 {
751 char buf[256];
752
753 kprintf("%s: %s\n", header,
754 cpuid_get_extfeature_names(cpuid_extfeatures(),
755 buf, sizeof(buf)));
756 }
757
758 void
759 cpuid_cpu_display(
760 const char *header)
761 {
762 if (cpuid_cpu_info.cpuid_brand_string[0] != '\0') {
763 kprintf("%s: %s\n", header, cpuid_cpu_info.cpuid_brand_string);
764 }
765 }
766
767 unsigned int
768 cpuid_family(void)
769 {
770 return cpuid_cpu_info.cpuid_family;
771 }
772
773 cpu_type_t
774 cpuid_cputype(void)
775 {
776 return cpuid_cpu_info.cpuid_cpu_type;
777 }
778
779 cpu_subtype_t
780 cpuid_cpusubtype(void)
781 {
782 return cpuid_cpu_info.cpuid_cpu_subtype;
783 }
784
785 uint64_t
786 cpuid_features(void)
787 {
788 static int checked = 0;
789 char fpu_arg[16] = { 0 };
790 if (!checked) {
791 /* check for boot-time fpu limitations */
792 if (PE_parse_boot_arg("_fpu", &fpu_arg[0])) {
793 printf("limiting fpu features to: %s\n", fpu_arg);
794 if (!strncmp("387", fpu_arg, sizeof "387") || !strncmp("mmx", fpu_arg, sizeof "mmx")) {
795 printf("no sse or sse2\n");
796 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR);
797 } else if (!strncmp("sse", fpu_arg, sizeof "sse")) {
798 printf("no sse2\n");
799 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE2);
800 }
801 }
802 checked = 1;
803 }
804 return cpuid_cpu_info.cpuid_features;
805 }
806
807 uint64_t
808 cpuid_extfeatures(void)
809 {
810 return cpuid_cpu_info.cpuid_extfeatures;
811 }
812
813 i386_cpu_info_t *
814 cpuid_info(void)
815 {
816 return &cpuid_cpu_info;
817 }
818
819 void
820 cpuid_set_info(void)
821 {
822 cpuid_get_info(&cpuid_cpu_info);
823 }
824
825 #if MACH_KDB
826
827 /*
828 * Display the cpuid
829 * *
830 * cp
831 */
832 void
833 db_cpuid(__unused db_expr_t addr,
834 __unused int have_addr,
835 __unused db_expr_t count,
836 __unused char *modif)
837 {
838
839 uint32_t i, mid;
840 uint32_t cpid[4];
841
842 do_cpuid(0, cpid); /* Get the first cpuid which is the number of
843 * basic ids */
844 db_printf("%08X - %08X %08X %08X %08X\n",
845 0, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
846
847 mid = cpid[eax]; /* Set the number */
848 for (i = 1; i <= mid; i++) { /* Dump 'em out */
849 do_cpuid(i, cpid); /* Get the next */
850 db_printf("%08X - %08X %08X %08X %08X\n",
851 i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
852 }
853 db_printf("\n");
854
855 do_cpuid(0x80000000, cpid); /* Get the first extended cpuid which
856 * is the number of extended ids */
857 db_printf("%08X - %08X %08X %08X %08X\n",
858 0x80000000, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
859
860 mid = cpid[eax]; /* Set the number */
861 for (i = 0x80000001; i <= mid; i++) { /* Dump 'em out */
862 do_cpuid(i, cpid); /* Get the next */
863 db_printf("%08X - %08X %08X %08X %08X\n",
864 i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
865 }
866 }
867
868 #endif
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