osfmk/i386/AT386/mp/mp_v1_1.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
   7  *
   8  * This file contains Original Code and/or Modifications of Original Code
   9  * as defined in and that are subject to the Apple Public Source License
  10  * Version 2.0 (the 'License'). You may not use this file except in
  11  * compliance with the License. Please obtain a copy of the License at
  12  * http://www.opensource.apple.com/apsl/ and read it before using this
  13  * file.
  14  *
  15  * The Original Code and all software distributed under the License are
  16  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  17  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  18  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  20  * Please see the License for the specific language governing rights and
  21  * limitations under the License.
  22  *
  23  * @APPLE_LICENSE_HEADER_END@
  24  */
  25 /*
  26  * @OSF_COPYRIGHT@
  27  */
  28
  29 #ifndef _MP_MP_V1_1_H_
  30 #define _MP_MP_V1_1_H_
  31
  32 #include <mach/mach_types.h>
  33 #include <i386/apic.h>
  34 #include <kern/lock.h>
  35
  36 struct MP_Config_EntryP {
  37         unsigned char   Entry_Type;
  38         unsigned char   Local_Apic_Id;
  39         unsigned char   Local_Apic_Version;
  40         unsigned char   CPU_Flags;
  41         unsigned int    CPU_Signature;
  42         unsigned int    Feature_Flags;
  43         unsigned int    Reserved[2];
  44 };
  45
  46 /* Entry types */
  47
  48 #define MP_CPU_ENTRY            0       /* Processor entry */
  49 #define MP_BUS_ENTRY            1       /* bus entry */
  50 #define MP_IO_APIC_ENTRY        2       /* I/O APIC entry */
  51 #define MP_IO_INT_ENTRY         3       /* I/O Interrupt assignment */
  52 #define MP_LOC_INT_ENTRY        4       /* Local Interrupt assignment */
  53
  54 struct MP_Config_EntryB {
  55         unsigned char   Entry_Type;
  56         unsigned char   Bus_Id;
  57         char            Ident[6];
  58 };
  59
  60 struct MP_Config_EntryA {
  61         unsigned char   Entry_Type;
  62         unsigned char   IO_Apic_Id;
  63         unsigned char   IO_Apic_Version;
  64         unsigned char   IO_Apic_Flags;
  65         vm_offset_t     IO_Apic_Address;
  66 };
  67
  68 struct MP_Config_EntryI {
  69         unsigned char   Entry_Type;
  70         unsigned char   Int_Type;
  71         unsigned short  Int_Flag;
  72         unsigned char   Source_Bus;
  73         unsigned char   Source_IRQ;
  74         unsigned char   Dest_IO_Apic;
  75         unsigned char   Dest_INTIN;
  76 };
  77 struct MP_Config_EntryL {
  78         unsigned char   Entry_Type;
  79         unsigned char   Int_Type;
  80         unsigned short  Int_Flag;
  81         unsigned char   Source_Bus;
  82         unsigned char   Source_IRQ;
  83         unsigned char   Dest_Local_Apic;
  84         unsigned char   Dest_INTIN;
  85 };
  86
  87 struct MP_FPS_struct {
  88         unsigned int    Signature;
  89         vm_offset_t     Config_Ptr;
  90         unsigned char   Length;
  91         unsigned char   Spec_Rev;
  92         unsigned char   CheckSum;
  93         unsigned char   Feature[5];
  94 };
  95
  96 struct MP_Config_Table {
  97         unsigned int    Signature;
  98         unsigned short  Length;
  99         unsigned char   Spec_Rev;
 100         unsigned char   CheckSum;
 101         char            OEM[8];
 102         char            PROD[12];
 103         vm_offset_t     OEM_Ptr;
 104         unsigned short  OEM_Size;
 105         unsigned short  Entries;
 106         vm_offset_t     Local_Apic;
 107         unsigned int    Reserved;
 108 };
 109
 110 #define IMCR_ADDRESS            0x22
 111 #define IMCR_DATA               0x23
 112 #define IMCR_SELECT             0x70
 113 #define IMCR_APIC_ENABLE        0x01
 114
 115 #if 0
 116 extern  boolean_t       mp_v1_1_take_irq(int    pic,
 117                                          int    unit,
 118                                          int    spl,
 119                                          i386_intr_t    intr);
 120
 121 extern  boolean_t       mp_v1_1_reset_irq(int           pic,
 122                                           int           *unit,
 123                                           int           *spl,
 124                                           i386_intr_t   *intr);
 125
 126 #endif
 127
 128 void mp_v1_1_init(void);
 129 boolean_t mp_v1_1_io_lock(int, struct processor **);
 130 void mp_v1_1_io_unlock(struct processor *);
 131
 132 /* Intel default Configurations */
 133
 134 #define MP_PROPRIETARY_CONF     0
 135 #define MP_ISA_CONF             1
 136 #define MP_EISA_1_CONF          2
 137 #define MP_EISA_2_CONF          3
 138 #define MP_MCA_CONF             4
 139 #define MP_ISA_PCI_CONF         5
 140 #define MP_EISA_PCI_CONF        6
 141 #define MP_MCA_PCI_CONF         7
 142
 143 #if     NCPUS > 1
 144 #define at386_io_lock_state()   panic("at386_io_lock_state called")
 145 #define at386_io_lock(x)        panic("at386_io_lock called");
 146 #define at386_io_unlock()       panic("at386_io_unlock")
 147 #endif  /* NCPUS > 1 */
 148
 149 #endif  /* _MP_MP_V1_1_H_ */