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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * Copyright (c) 1999-2003 Apple Computer, Inc. All Rights Reserved.
7 *
8 * This file contains Original Code and/or Modifications of Original Code
9 * as defined in and that are subject to the Apple Public Source License
10 * Version 2.0 (the 'License'). You may not use this file except in
11 * compliance with the License. Please obtain a copy of the License at
12 * http://www.opensource.apple.com/apsl/ and read it before using this
13 * file.
14 *
15 * The Original Code and all software distributed under the License are
16 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
17 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
18 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
20 * Please see the License for the specific language governing rights and
21 * limitations under the License.
22 *
23 * @APPLE_LICENSE_HEADER_END@
24 */
25 /*
26 * @OSF_COPYRIGHT@
27 */
28
29 /* Miscellaneous constants and structures used by the exception
30 * handlers
31 */
32
33 #ifndef _PPC_EXCEPTION_H_
34 #define _PPC_EXCEPTION_H_
35
36 #include <ppc/savearea.h>
37
38 #ifndef ASSEMBLER
39
40 #include <cpus.h>
41 #include <mach_kdb.h>
42 #include <mach_kdp.h>
43
44 #include <mach/machine/vm_types.h>
45 #include <mach/boolean.h>
46 #include <kern/cpu_data.h>
47 #include <pexpert/pexpert.h>
48 #include <IOKit/IOInterrupts.h>
49 #include <ppc/machine_routines.h>
50
51 /* Per processor CPU features */
52 #pragma pack(4) /* Make sure the structure stays as we defined it */
53 struct procFeatures {
54 unsigned int Available; /* 0x000 */
55 #define pfFloat 0x80000000
56 #define pfFloatb 0
57 #define pfAltivec 0x40000000
58 #define pfAltivecb 1
59 #define pfAvJava 0x20000000
60 #define pfAvJavab 2
61 #define pfSMPcap 0x10000000
62 #define pfSMPcapb 3
63 #define pfCanSleep 0x08000000
64 #define pfCanSleepb 4
65 #define pfCanNap 0x04000000
66 #define pfCanNapb 5
67 #define pfCanDoze 0x02000000
68 #define pfCanDozeb 6
69 #define pfThermal 0x01000000
70 #define pfThermalb 7
71 #define pfThermInt 0x00800000
72 #define pfThermIntb 8
73 #define pfSlowNap 0x00400000
74 #define pfSlowNapb 9
75 #define pfNoMuMMCK 0x00200000
76 #define pfNoMuMMCKb 10
77 #define pfNoL2PFNap 0x00100000
78 #define pfNoL2PFNapb 11
79 #define pfSCOMFixUp 0x00080000
80 #define pfSCOMFixUpb 12
81 #define pfHasDcba 0x00040000
82 #define pfHasDcbab 13
83 #define pfL1fa 0x00010000
84 #define pfL1fab 15
85 #define pfL2 0x00008000
86 #define pfL2b 16
87 #define pfL2fa 0x00004000
88 #define pfL2fab 17
89 #define pfL2i 0x00002000
90 #define pfL2ib 18
91 #define pfLClck 0x00001000
92 #define pfLClckb 19
93 #define pfWillNap 0x00000800
94 #define pfWillNapb 20
95 #define pfNoMSRir 0x00000400
96 #define pfNoMSRirb 21
97 #define pfL3pdet 0x00000200
98 #define pfL3pdetb 22
99 #define pf128Byte 0x00000080
100 #define pf128Byteb 24
101 #define pf32Byte 0x00000020
102 #define pf32Byteb 26
103 #define pf64Bit 0x00000010
104 #define pf64Bitb 27
105 #define pfL3 0x00000004
106 #define pfL3b 29
107 #define pfL3fa 0x00000002
108 #define pfL3fab 30
109 #define pfValid 0x00000001
110 #define pfValidb 31
111 unsigned short rptdProc; /* 0x004 */
112 unsigned short lineSize; /* 0x006 */
113 unsigned int l1iSize; /* 0x008 */
114 unsigned int l1dSize; /* 0x00C */
115 unsigned int l2cr; /* 0x010 */
116 unsigned int l2Size; /* 0x014 */
117 unsigned int l3cr; /* 0x018 */
118 unsigned int l3Size; /* 0x01C */
119 unsigned int pfMSSCR0; /* 0x020 */
120 unsigned int pfMSSCR1; /* 0x024 */
121 unsigned int pfICTRL; /* 0x028 */
122 unsigned int pfLDSTCR; /* 0x02C */
123 unsigned int pfLDSTDB; /* 0x030 */
124 unsigned int pfMaxVAddr; /* 0x034 */
125 unsigned int pfMaxPAddr; /* 0x038 */
126 unsigned int pfPTEG; /* 0x03C */
127 uint64_t pfHID0; /* 0x040 */
128 uint64_t pfHID1; /* 0x048 */
129 uint64_t pfHID2; /* 0x050 */
130 uint64_t pfHID3; /* 0x058 */
131 uint64_t pfHID4; /* 0x060 */
132 uint64_t pfHID5; /* 0x068 */
133 unsigned int l2crOriginal; /* 0x070 */
134 unsigned int l3crOriginal; /* 0x074 */
135 unsigned int pfBootConfig; /* 0x07C */
136 unsigned int reserved[1]; /* 0x80 */
137 };
138 #pragma pack()
139
140 typedef struct procFeatures procFeatures;
141
142 #pragma pack(4) /* Make sure the structure stays as we defined it */
143 struct thrmControl {
144 unsigned int maxTemp; /* Maximum temprature before damage */
145 unsigned int throttleTemp; /* Temprature at which to throttle down */
146 unsigned int lowTemp; /* Interrupt when temprature drops below */
147 unsigned int highTemp; /* Interrupt when temprature exceeds this */
148 unsigned int thrm3val; /* Value for thrm3 register */
149 unsigned int rsvd[3]; /* Pad to cache line */
150 };
151 #pragma pack()
152
153 typedef struct thrmControl thrmControl;
154
155 /*
156 *
157 * Various performance counters
158 */
159 #pragma pack(4) /* Make sure the structure stays as we defined it */
160 struct hwCtrs {
161
162 unsigned int hwInVains; /* In vain */
163 unsigned int hwResets; /* Reset */
164 unsigned int hwMachineChecks; /* Machine check */
165 unsigned int hwDSIs; /* DSIs */
166 unsigned int hwISIs; /* ISIs */
167 unsigned int hwExternals; /* Externals */
168 unsigned int hwAlignments; /* Alignment */
169 unsigned int hwPrograms; /* Program */
170 unsigned int hwFloatPointUnavailable; /* Floating point */
171 unsigned int hwDecrementers; /* Decrementer */
172 unsigned int hwIOErrors; /* I/O error */
173 unsigned int hwrsvd0; /* Reserved */
174 unsigned int hwSystemCalls; /* System call */
175 unsigned int hwTraces; /* Trace */
176 unsigned int hwFloatingPointAssists; /* Floating point assist */
177 unsigned int hwPerformanceMonitors; /* Performance monitor */
178 unsigned int hwAltivecs; /* VMX */
179 unsigned int hwrsvd1; /* Reserved */
180 unsigned int hwrsvd2; /* Reserved */
181 unsigned int hwrsvd3; /* Reserved */
182 unsigned int hwInstBreakpoints; /* Instruction breakpoint */
183 unsigned int hwSystemManagements; /* System management */
184 unsigned int hwAltivecAssists; /* Altivec Assist */
185 unsigned int hwThermal; /* Thermals */
186 unsigned int hwrsvd5; /* Reserved */
187 unsigned int hwrsvd6; /* Reserved */
188 unsigned int hwrsvd7; /* Reserved */
189 unsigned int hwrsvd8; /* Reserved */
190 unsigned int hwrsvd9; /* Reserved */
191 unsigned int hwrsvd10; /* Reserved */
192 unsigned int hwrsvd11; /* Reserved */
193 unsigned int hwrsvd12; /* Reserved */
194 unsigned int hwrsvd13; /* Reserved */
195 unsigned int hwTrace601; /* Trace */
196 unsigned int hwSIGPs; /* SIGP */
197 unsigned int hwPreemptions; /* Preemption */
198 unsigned int hwContextSwitchs; /* Context switch */
199 unsigned int hwShutdowns; /* Shutdowns */
200 unsigned int hwChokes; /* System ABENDs */
201 unsigned int hwDataSegments; /* Data Segment Interruptions */
202 unsigned int hwInstructionSegments; /* Instruction Segment Interruptions */
203 unsigned int hwSoftPatches; /* Soft Patch interruptions */
204 unsigned int hwMaintenances; /* Maintenance interruptions */
205 unsigned int hwInstrumentations; /* Instrumentation interruptions */
206 unsigned int hwrsvd14; /* Reswerved */
207 /* 0x0B4 */
208
209 unsigned int hwspare0[17]; /* Reserved */
210 unsigned int hwRedrives; /* Number of redriven interrupts */
211 unsigned int hwSteals; /* PTE Steals */
212 /* 0x100 */
213
214 unsigned int hwMckHang; /* ? */
215 unsigned int hwMckSLBPE; /* ? */
216 unsigned int hwMckTLBPE; /* ? */
217 unsigned int hwMckERCPE; /* ? */
218 unsigned int hwMckL1DPE; /* ? */
219 unsigned int hwMckL1TPE; /* ? */
220 unsigned int hwMckUE; /* ? */
221 unsigned int hwMckIUE; /* ? */
222 unsigned int hwMckIUEr; /* ? */
223 unsigned int hwMckDUE; /* ? */
224 unsigned int hwMckDTW; /* ? */
225 unsigned int hwMckUnk; /* ? */
226 unsigned int hwMckExt; /* ? */
227 unsigned int hwMckICachePE; /* ? */
228 unsigned int hwMckITagPE; /* ? */
229 unsigned int hwMckIEratPE; /* ? */
230 unsigned int hwMckDEratPE; /* ? */
231 unsigned int hwspare2[15]; /* Pad to next 128 bndry */
232 /* 0x180 */
233
234 unsigned int napStamp[2]; /* Time base when we napped */
235 unsigned int napTotal[2]; /* Total nap time in ticks */
236 unsigned int numSIGPast; /* Number of SIGP asts recieved */
237 unsigned int numSIGPcpureq; /* Number of SIGP cpu requests recieved */
238 unsigned int numSIGPdebug; /* Number of SIGP debugs recieved */
239 unsigned int numSIGPwake; /* Number of SIGP wakes recieved */
240 unsigned int numSIGPtimo; /* Number of SIGP send timeouts */
241 unsigned int numSIGPmast; /* Number of SIGPast messages merged */
242 unsigned int numSIGPmwake; /* Number of SIGPwake messages merged */
243
244 unsigned int hwspare3[21]; /* Pad to 512 */
245
246 };
247 #pragma pack()
248
249 typedef struct hwCtrs hwCtrs;
250
251 struct patch_entry {
252 unsigned int *addr;
253 unsigned int data;
254 unsigned int type;
255 unsigned int value;
256 };
257
258 typedef struct patch_entry patch_entry_t;
259
260 #define PATCH_INVALID 0
261 #define PATCH_PROCESSOR 1
262 #define PATCH_FEATURE 2
263
264 #define PATCH_TABLE_SIZE 12
265
266 #define PatchExt32 0x80000000
267 #define PatchExt32b 0
268 #define PatchLwsync 0x40000000
269 #define PatchLwsyncb 1
270
271 /* When an exception is taken, this info is accessed via sprg0 */
272 /* We should always have this one on a cache line boundary */
273
274 #pragma pack(4) /* Make sure the structure stays as we defined it */
275 struct per_proc_info {
276 unsigned short cpu_number;
277 unsigned short cpu_flags; /* Various low-level flags */
278 vm_offset_t istackptr;
279 vm_offset_t intstack_top_ss;
280
281 vm_offset_t debstackptr;
282 vm_offset_t debstack_top_ss;
283
284 unsigned int spcFlags; /* Special thread flags */
285 unsigned int Uassist; /* User Assist Word */
286 unsigned int old_thread;
287
288 /* PPC cache line boundary here - 020 */
289
290 unsigned int active_kloaded; /* pointer to active_kloaded[CPU_NO] */
291 unsigned int active_stacks; /* pointer to active_stacks[CPU_NO] */
292 unsigned int need_ast; /* pointer to need_ast[CPU_NO] */
293 /*
294 * Note: the following two pairs of words need to stay in order and each pair must
295 * be in the same reservation (line) granule
296 */
297 struct facility_context *FPU_owner; /* Owner of the FPU on this cpu */
298 unsigned int liveVRSave; /* VRSave assiciated with live vector registers */
299 struct facility_context *VMX_owner; /* Owner of the VMX on this cpu */
300 unsigned int holdQFret; /* Hold off releasing quickfret list */
301 unsigned int rsrvd03C[1];
302
303 /* PPC cache line boundary here - 040 */
304 addr64_t quickfret; /* List of saveareas to release */
305 addr64_t lclfree; /* Pointer to local savearea list */
306 unsigned int lclfreecnt; /* Entries in local savearea list */
307 unsigned int spcTRc; /* Special trace count */
308 unsigned int spcTRp; /* Special trace buffer pointer */
309 unsigned int ppbbTaskEnv; /* BlueBox Task Environment */
310
311 /* PPC cache line boundary here - 060 */
312 boolean_t interrupts_enabled;
313 IOInterruptHandler interrupt_handler;
314 void * interrupt_nub;
315 unsigned int interrupt_source;
316 void * interrupt_target;
317 void * interrupt_refCon;
318 uint64_t next_savearea; /* pointer to the next savearea */
319
320 /* PPC cache line boundary here - 080 */
321 unsigned int MPsigpStat; /* Signal Processor status (interlocked update for this one) */
322 #define MPsigpMsgp 0xC0000000 /* Message pending (busy + pass ) */
323 #define MPsigpBusy 0x80000000 /* Processor area busy, i.e., locked */
324 #define MPsigpPass 0x40000000 /* Busy lock passed to receiving processor */
325 #define MPsigpAck 0x20000000 /* Ack Busy lock passed to receiving processor */
326 #define MPsigpSrc 0x000000FF /* Processor that owns busy, i.e., the ID of */
327 /* whomever set busy. When a busy is passed, */
328 /* this is the requestor of the function. */
329 #define MPsigpFunc 0x0000FF00 /* Current function */
330 #define MPsigpIdle 0x00 /* No function pending */
331 #define MPsigpSigp 0x04 /* Signal a processor */
332 #define SIGPast 0 /* Requests an ast on target processor */
333 #define SIGPcpureq 1 /* Requests CPU specific function */
334 #define SIGPdebug 2 /* Requests a debugger entry */
335 #define SIGPwake 3 /* Wake up a sleeping processor */
336 #define CPRQtemp 0 /* Get temprature of processor */
337 #define CPRQtimebase 1 /* Get timebase of processor */
338 #define CPRQscom 2 /* SCOM */
339 unsigned int MPsigpParm0; /* SIGP parm 0 */
340 unsigned int MPsigpParm1; /* SIGP parm 1 */
341 unsigned int MPsigpParm2; /* SIGP parm 2 */
342 cpu_id_t cpu_id;
343 vm_offset_t start_paddr;
344 unsigned int ruptStamp[2]; /* Timebase at last interruption */
345
346 /* PPC cache line boundary here - 0A0 */
347 procFeatures pf; /* Processor features */
348
349 /* PPC cache line boundary here - 120 */
350 thrmControl thrm; /* Thermal controls */
351
352 /* PPC cache line boundary here - 140 */
353 unsigned int ppRsvd140[8]; /* Reserved */
354
355 /* PPC cache line boundary here - 160 */
356 time_base_enable_t time_base_enable;
357 unsigned int ppRsvd164[3]; /* Reserved */
358 cpu_data_t pp_cpu_data; /* cpu data info */
359
360 /* PPC cache line boundary here - 180 */
361 unsigned int ppRsvd180[2]; /* Reserved */
362 uint64_t validSegs; /* Valid SR/STB slots */
363 addr64_t ppUserPmap; /* Current user state pmap (physical address) */
364 unsigned int ppUserPmapVirt; /* Current user state pmap (virtual address) */
365 unsigned int ppMapFlags; /* Mapping flags */
366
367 /* PPC cache line boundary here - 1A0 */
368 unsigned short ppInvSeg; /* Forces complete invalidate of SRs/SLB (this must stay with ppInvSeg) */
369 unsigned short ppCurSeg; /* Set to 1 if user segments, 0 if kernel (this must stay with ppInvSeg) */
370 unsigned int ppSegSteal; /* Count of segment slot steals */
371 ppnum_t VMMareaPhys; /* vmm state page physical addr */
372 unsigned int VMMXAFlgs; /* vmm extended flags */
373 unsigned int FAMintercept; /* vmm FAM Exceptions to intercept */
374 unsigned int rsrvd1B4[3]; /* Reserved slots */
375
376 /* PPC cache line boundary here - 1C0 */
377 unsigned int ppCIOmp[16]; /* Linkage mapping for copyin/out - 64 bytes */
378
379 /* PPC cache line boundary here - 200 */
380 uint64_t tempr0; /* temporary savearea */
381 uint64_t tempr1;
382 uint64_t tempr2;
383 uint64_t tempr3;
384
385 uint64_t tempr4;
386 uint64_t tempr5;
387 uint64_t tempr6;
388 uint64_t tempr7;
389
390 uint64_t tempr8;
391 uint64_t tempr9;
392 uint64_t tempr10;
393 uint64_t tempr11;
394
395 uint64_t tempr12;
396 uint64_t tempr13;
397 uint64_t tempr14;
398 uint64_t tempr15;
399
400 uint64_t tempr16;
401 uint64_t tempr17;
402 uint64_t tempr18;
403 uint64_t tempr19;
404
405 uint64_t tempr20;
406 uint64_t tempr21;
407 uint64_t tempr22;
408 uint64_t tempr23;
409
410 uint64_t tempr24;
411 uint64_t tempr25;
412 uint64_t tempr26;
413 uint64_t tempr27;
414
415 uint64_t tempr28;
416 uint64_t tempr29;
417 uint64_t tempr30;
418 uint64_t tempr31;
419
420
421 /* PPC cache line boundary here - 300 */
422 double emfp0; /* Copies of floating point registers */
423 double emfp1; /* Used for emulation purposes */
424 double emfp2;
425 double emfp3;
426
427 double emfp4;
428 double emfp5;
429 double emfp6;
430 double emfp7;
431
432 double emfp8;
433 double emfp9;
434 double emfp10;
435 double emfp11;
436
437 double emfp12;
438 double emfp13;
439 double emfp14;
440 double emfp15;
441
442 double emfp16;
443 double emfp17;
444 double emfp18;
445 double emfp19;
446
447 double emfp20;
448 double emfp21;
449 double emfp22;
450 double emfp23;
451
452 double emfp24;
453 double emfp25;
454 double emfp26;
455 double emfp27;
456
457 double emfp28;
458 double emfp29;
459 double emfp30;
460 double emfp31;
461
462 /* - 400 */
463 unsigned int emfpscr_pad;
464 unsigned int emfpscr;
465 unsigned int empadfp[6];
466
467 /* - 420 */
468 unsigned int emvr0[4]; /* Copies of vector registers used both */
469 unsigned int emvr1[4]; /* for full vector emulation or */
470 unsigned int emvr2[4]; /* as saveareas while assisting denorms */
471 unsigned int emvr3[4];
472 unsigned int emvr4[4];
473 unsigned int emvr5[4];
474 unsigned int emvr6[4];
475 unsigned int emvr7[4];
476 unsigned int emvr8[4];
477 unsigned int emvr9[4];
478 unsigned int emvr10[4];
479 unsigned int emvr11[4];
480 unsigned int emvr12[4];
481 unsigned int emvr13[4];
482 unsigned int emvr14[4];
483 unsigned int emvr15[4];
484 unsigned int emvr16[4];
485 unsigned int emvr17[4];
486 unsigned int emvr18[4];
487 unsigned int emvr19[4];
488 unsigned int emvr20[4];
489 unsigned int emvr21[4];
490 unsigned int emvr22[4];
491 unsigned int emvr23[4];
492 unsigned int emvr24[4];
493 unsigned int emvr25[4];
494 unsigned int emvr26[4];
495 unsigned int emvr27[4];
496 unsigned int emvr28[4];
497 unsigned int emvr29[4];
498 unsigned int emvr30[4];
499 unsigned int emvr31[4];
500 unsigned int emvscr[4];
501 unsigned int empadvr[4];
502 /* - 640 */
503 /* note implicit dependence on kSkipListMaxLists, which must be <= 28 */
504 addr64_t skipListPrev[28]; /* prev ptrs saved as side effect of calling mapSearchFull() */
505
506 /* - 720 */
507
508 unsigned int patcharea[56];
509 /* - 800 */
510
511 hwCtrs hwCtr; /* Hardware exception counters */
512 /* - A00 */
513
514 unsigned int pppadpage[384]; /* Pad to end of page */
515 /* - 1000 */
516
517
518 };
519
520 #define pp_active_thread pp_cpu_data.active_thread
521 #define pp_preemption_count pp_cpu_data.preemption_level
522 #define pp_simple_lock_count pp_cpu_data.simple_lock_count
523 #define pp_interrupt_level pp_cpu_data.interrupt_level
524
525 #pragma pack()
526
527
528 extern struct per_proc_info per_proc_info[NCPUS];
529
530
531 extern char *trap_type[];
532
533 #endif /* ndef ASSEMBLER */ /* with this savearea should be redriven */
534
535 /* cpu_flags defs */
536 #define SIGPactive 0x8000
537 #define needSRload 0x4000
538 #define turnEEon 0x2000
539 #define traceBE 0x1000 /* user mode BE tracing in enabled */
540 #define traceBEb 3 /* bit number for traceBE */
541 #define BootDone 0x0100
542 #define SignalReady 0x0200
543 #define loadMSR 0x7FF4
544
545 #define T_VECTOR_SIZE 4 /* function pointer size */
546
547 /* Hardware exceptions */
548
549 #define T_IN_VAIN (0x00 * T_VECTOR_SIZE)
550 #define T_RESET (0x01 * T_VECTOR_SIZE)
551 #define T_MACHINE_CHECK (0x02 * T_VECTOR_SIZE)
552 #define T_DATA_ACCESS (0x03 * T_VECTOR_SIZE)
553 #define T_INSTRUCTION_ACCESS (0x04 * T_VECTOR_SIZE)
554 #define T_INTERRUPT (0x05 * T_VECTOR_SIZE)
555 #define T_ALIGNMENT (0x06 * T_VECTOR_SIZE)
556 #define T_PROGRAM (0x07 * T_VECTOR_SIZE)
557 #define T_FP_UNAVAILABLE (0x08 * T_VECTOR_SIZE)
558 #define T_DECREMENTER (0x09 * T_VECTOR_SIZE)
559 #define T_IO_ERROR (0x0a * T_VECTOR_SIZE)
560 #define T_RESERVED (0x0b * T_VECTOR_SIZE)
561 #define T_SYSTEM_CALL (0x0c * T_VECTOR_SIZE)
562 #define T_TRACE (0x0d * T_VECTOR_SIZE)
563 #define T_FP_ASSIST (0x0e * T_VECTOR_SIZE)
564 #define T_PERF_MON (0x0f * T_VECTOR_SIZE)
565 #define T_VMX (0x10 * T_VECTOR_SIZE)
566 #define T_INVALID_EXCP0 (0x11 * T_VECTOR_SIZE)
567 #define T_INVALID_EXCP1 (0x12 * T_VECTOR_SIZE)
568 #define T_INVALID_EXCP2 (0x13 * T_VECTOR_SIZE)
569 #define T_INSTRUCTION_BKPT (0x14 * T_VECTOR_SIZE)
570 #define T_SYSTEM_MANAGEMENT (0x15 * T_VECTOR_SIZE)
571 #define T_ALTIVEC_ASSIST (0x16 * T_VECTOR_SIZE)
572 #define T_THERMAL (0x17 * T_VECTOR_SIZE)
573 #define T_INVALID_EXCP5 (0x18 * T_VECTOR_SIZE)
574 #define T_INVALID_EXCP6 (0x19 * T_VECTOR_SIZE)
575 #define T_INVALID_EXCP7 (0x1A * T_VECTOR_SIZE)
576 #define T_INVALID_EXCP8 (0x1B * T_VECTOR_SIZE)
577 #define T_INVALID_EXCP9 (0x1C * T_VECTOR_SIZE)
578 #define T_INVALID_EXCP10 (0x1D * T_VECTOR_SIZE)
579 #define T_INVALID_EXCP11 (0x1E * T_VECTOR_SIZE)
580 #define T_INVALID_EXCP12 (0x1F * T_VECTOR_SIZE)
581 #define T_EMULATE (0x20 * T_VECTOR_SIZE)
582
583 #define T_RUNMODE_TRACE (0x21 * T_VECTOR_SIZE) /* 601 only */
584
585 #define T_SIGP (0x22 * T_VECTOR_SIZE)
586 #define T_PREEMPT (0x23 * T_VECTOR_SIZE)
587 #define T_CSWITCH (0x24 * T_VECTOR_SIZE)
588 #define T_SHUTDOWN (0x25 * T_VECTOR_SIZE)
589 #define T_CHOKE (0x26 * T_VECTOR_SIZE)
590
591 #define T_DATA_SEGMENT (0x27 * T_VECTOR_SIZE)
592 #define T_INSTRUCTION_SEGMENT (0x28 * T_VECTOR_SIZE)
593
594 #define T_SOFT_PATCH (0x29 * T_VECTOR_SIZE)
595 #define T_MAINTENANCE (0x2A * T_VECTOR_SIZE)
596 #define T_INSTRUMENTATION (0x2B * T_VECTOR_SIZE)
597 #define T_ARCHDEP0 (0x2C * T_VECTOR_SIZE)
598
599 #define T_AST (0x100 * T_VECTOR_SIZE)
600 #define T_MAX T_CHOKE /* Maximum exception no */
601
602 #define T_FAM 0x00004000
603
604 #define EXCEPTION_VECTOR(exception) (exception * 0x100 / T_VECTOR_SIZE )
605
606 /*
607 * System choke (failure) codes
608 */
609
610 #define failDebug 0
611 #define failStack 1
612 #define failMapping 2
613 #define failContext 3
614 #define failNoSavearea 4
615 #define failSaveareaCorr 5
616 #define failBadLiveContext 6
617 #define failSkipLists 7
618 #define failUnalignedStk 8
619
620 /* Always must be last - update failNames table in model_dep.c as well */
621 #define failUnknown 9
622
623 #ifndef ASSEMBLER
624
625 #pragma pack(4) /* Make sure the structure stays as we defined it */
626 typedef struct resethandler {
627 unsigned int type;
628 vm_offset_t call_paddr;
629 vm_offset_t arg__paddr;
630 } resethandler_t;
631 #pragma pack()
632
633 extern resethandler_t ResetHandler;
634
635 #endif
636
637 #define RESET_HANDLER_NULL 0x0
638 #define RESET_HANDLER_START 0x1
639 #define RESET_HANDLER_BUPOR 0x2
640 #define RESET_HANDLER_IGNORE 0x3
641
642 #endif /* _PPC_EXCEPTION_H_ */
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