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1 /*
2 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 #include <platforms.h>
32 #include <mach_kdb.h>
33 #include <vm/vm_page.h>
34 #include <pexpert/pexpert.h>
35
36 #include <i386/cpuid.h>
37 #if MACH_KDB
38 #include <machine/db_machdep.h>
39 #include <ddb/db_aout.h>
40 #include <ddb/db_access.h>
41 #include <ddb/db_sym.h>
42 #include <ddb/db_variables.h>
43 #include <ddb/db_command.h>
44 #include <ddb/db_output.h>
45 #include <ddb/db_expr.h>
46 #endif
47
48 static boolean_t cpuid_dbg
49 #if DEBUG
50 = TRUE;
51 #else
52 = FALSE;
53 #endif
54 #define DBG(x...) \
55 do { \
56 if (cpuid_dbg) \
57 kprintf(x); \
58 } while (0) \
59
60 #define min(a,b) ((a) < (b) ? (a) : (b))
61 #define quad(hi,lo) (((uint64_t)(hi)) << 32 | (lo))
62
63 /* Only for 32bit values */
64 #define bit32(n) (1U << (n))
65 #define bitmask32(h,l) ((bit32(h)|(bit32(h)-1)) & ~(bit32(l)-1))
66 #define bitfield32(x,h,l) ((((x) & bitmask32(h,l)) >> l))
67
68 /*
69 * Leaf 2 cache descriptor encodings.
70 */
71 typedef enum {
72 _NULL_, /* NULL (empty) descriptor */
73 CACHE, /* Cache */
74 TLB, /* TLB */
75 STLB, /* Shared second-level unified TLB */
76 PREFETCH /* Prefetch size */
77 } cpuid_leaf2_desc_type_t;
78
79 typedef enum {
80 NA, /* Not Applicable */
81 FULLY, /* Fully-associative */
82 TRACE, /* Trace Cache (P4 only) */
83 INST, /* Instruction TLB */
84 DATA, /* Data TLB */
85 DATA0, /* Data TLB, 1st level */
86 DATA1, /* Data TLB, 2nd level */
87 L1, /* L1 (unified) cache */
88 L1_INST, /* L1 Instruction cache */
89 L1_DATA, /* L1 Data cache */
90 L2, /* L2 (unified) cache */
91 L3, /* L3 (unified) cache */
92 L2_2LINESECTOR, /* L2 (unified) cache with 2 lines per sector */
93 L3_2LINESECTOR, /* L3(unified) cache with 2 lines per sector */
94 SMALL, /* Small page TLB */
95 LARGE, /* Large page TLB */
96 BOTH /* Small and Large page TLB */
97 } cpuid_leaf2_qualifier_t;
98
99 typedef struct cpuid_cache_descriptor {
100 uint8_t value; /* descriptor code */
101 uint8_t type; /* cpuid_leaf2_desc_type_t */
102 uint8_t level; /* level of cache/TLB hierachy */
103 uint8_t ways; /* wayness of cache */
104 uint16_t size; /* cachesize or TLB pagesize */
105 uint16_t entries; /* number of TLB entries or linesize */
106 } cpuid_cache_descriptor_t;
107
108 /*
109 * These multipliers are used to encode 1*K .. 64*M in a 16 bit size field
110 */
111 #define K (1)
112 #define M (1024)
113
114 /*
115 * Intel cache descriptor table:
116 */
117 static cpuid_cache_descriptor_t intel_cpuid_leaf2_descriptor_table[] = {
118 // -------------------------------------------------------
119 // value type level ways size entries
120 // -------------------------------------------------------
121 { 0x00, _NULL_, NA, NA, NA, NA },
122 { 0x01, TLB, INST, 4, SMALL, 32 },
123 { 0x02, TLB, INST, FULLY, LARGE, 2 },
124 { 0x03, TLB, DATA, 4, SMALL, 64 },
125 { 0x04, TLB, DATA, 4, LARGE, 8 },
126 { 0x05, TLB, DATA1, 4, LARGE, 32 },
127 { 0x06, CACHE, L1_INST, 4, 8*K, 32 },
128 { 0x08, CACHE, L1_INST, 4, 16*K, 32 },
129 { 0x09, CACHE, L1_INST, 4, 32*K, 64 },
130 { 0x0A, CACHE, L1_DATA, 2, 8*K, 32 },
131 { 0x0B, TLB, INST, 4, LARGE, 4 },
132 { 0x0C, CACHE, L1_DATA, 4, 16*K, 32 },
133 { 0x0D, CACHE, L1_DATA, 4, 16*K, 64 },
134 { 0x0E, CACHE, L1_DATA, 6, 24*K, 64 },
135 { 0x21, CACHE, L2, 8, 256*K, 64 },
136 { 0x22, CACHE, L3_2LINESECTOR, 4, 512*K, 64 },
137 { 0x23, CACHE, L3_2LINESECTOR, 8, 1*M, 64 },
138 { 0x25, CACHE, L3_2LINESECTOR, 8, 2*M, 64 },
139 { 0x29, CACHE, L3_2LINESECTOR, 8, 4*M, 64 },
140 { 0x2C, CACHE, L1_DATA, 8, 32*K, 64 },
141 { 0x30, CACHE, L1_INST, 8, 32*K, 64 },
142 { 0x40, CACHE, L2, NA, 0, NA },
143 { 0x41, CACHE, L2, 4, 128*K, 32 },
144 { 0x42, CACHE, L2, 4, 256*K, 32 },
145 { 0x43, CACHE, L2, 4, 512*K, 32 },
146 { 0x44, CACHE, L2, 4, 1*M, 32 },
147 { 0x45, CACHE, L2, 4, 2*M, 32 },
148 { 0x46, CACHE, L3, 4, 4*M, 64 },
149 { 0x47, CACHE, L3, 8, 8*M, 64 },
150 { 0x48, CACHE, L2, 12, 3*M, 64 },
151 { 0x49, CACHE, L2, 16, 4*M, 64 },
152 { 0x4A, CACHE, L3, 12, 6*M, 64 },
153 { 0x4B, CACHE, L3, 16, 8*M, 64 },
154 { 0x4C, CACHE, L3, 12, 12*M, 64 },
155 { 0x4D, CACHE, L3, 16, 16*M, 64 },
156 { 0x4E, CACHE, L2, 24, 6*M, 64 },
157 { 0x4F, TLB, INST, NA, SMALL, 32 },
158 { 0x50, TLB, INST, NA, BOTH, 64 },
159 { 0x51, TLB, INST, NA, BOTH, 128 },
160 { 0x52, TLB, INST, NA, BOTH, 256 },
161 { 0x55, TLB, INST, FULLY, BOTH, 7 },
162 { 0x56, TLB, DATA0, 4, LARGE, 16 },
163 { 0x57, TLB, DATA0, 4, SMALL, 16 },
164 { 0x59, TLB, DATA0, FULLY, SMALL, 16 },
165 { 0x5A, TLB, DATA0, 4, LARGE, 32 },
166 { 0x5B, TLB, DATA, NA, BOTH, 64 },
167 { 0x5C, TLB, DATA, NA, BOTH, 128 },
168 { 0x5D, TLB, DATA, NA, BOTH, 256 },
169 { 0x60, CACHE, L1, 16*K, 8, 64 },
170 { 0x61, CACHE, L1, 4, 8*K, 64 },
171 { 0x62, CACHE, L1, 4, 16*K, 64 },
172 { 0x63, CACHE, L1, 4, 32*K, 64 },
173 { 0x70, CACHE, TRACE, 8, 12*K, NA },
174 { 0x71, CACHE, TRACE, 8, 16*K, NA },
175 { 0x72, CACHE, TRACE, 8, 32*K, NA },
176 { 0x78, CACHE, L2, 4, 1*M, 64 },
177 { 0x79, CACHE, L2_2LINESECTOR, 8, 128*K, 64 },
178 { 0x7A, CACHE, L2_2LINESECTOR, 8, 256*K, 64 },
179 { 0x7B, CACHE, L2_2LINESECTOR, 8, 512*K, 64 },
180 { 0x7C, CACHE, L2_2LINESECTOR, 8, 1*M, 64 },
181 { 0x7D, CACHE, L2, 8, 2*M, 64 },
182 { 0x7F, CACHE, L2, 2, 512*K, 64 },
183 { 0x80, CACHE, L2, 8, 512*K, 64 },
184 { 0x82, CACHE, L2, 8, 256*K, 32 },
185 { 0x83, CACHE, L2, 8, 512*K, 32 },
186 { 0x84, CACHE, L2, 8, 1*M, 32 },
187 { 0x85, CACHE, L2, 8, 2*M, 32 },
188 { 0x86, CACHE, L2, 4, 512*K, 64 },
189 { 0x87, CACHE, L2, 8, 1*M, 64 },
190 { 0xB0, TLB, INST, 4, SMALL, 128 },
191 { 0xB1, TLB, INST, 4, LARGE, 8 },
192 { 0xB2, TLB, INST, 4, SMALL, 64 },
193 { 0xB3, TLB, DATA, 4, SMALL, 128 },
194 { 0xB4, TLB, DATA1, 4, SMALL, 256 },
195 { 0xBA, TLB, DATA1, 4, BOTH, 64 },
196 { 0xCA, STLB, DATA1, 4, BOTH, 512 },
197 { 0xD0, CACHE, L3, 4, 512*K, 64 },
198 { 0xD1, CACHE, L3, 4, 1*M, 64 },
199 { 0xD2, CACHE, L3, 4, 2*M, 64 },
200 { 0xD3, CACHE, L3, 4, 4*M, 64 },
201 { 0xD4, CACHE, L3, 4, 8*M, 64 },
202 { 0xD6, CACHE, L3, 8, 1*M, 64 },
203 { 0xD7, CACHE, L3, 8, 2*M, 64 },
204 { 0xD8, CACHE, L3, 8, 4*M, 64 },
205 { 0xD9, CACHE, L3, 8, 8*M, 64 },
206 { 0xDA, CACHE, L3, 8, 12*M, 64 },
207 { 0xDC, CACHE, L3, 12, 1536*K, 64 },
208 { 0xDD, CACHE, L3, 12, 3*M, 64 },
209 { 0xDE, CACHE, L3, 12, 6*M, 64 },
210 { 0xDF, CACHE, L3, 12, 12*M, 64 },
211 { 0xE0, CACHE, L3, 12, 18*M, 64 },
212 { 0xE2, CACHE, L3, 16, 2*M, 64 },
213 { 0xE3, CACHE, L3, 16, 4*M, 64 },
214 { 0xE4, CACHE, L3, 16, 8*M, 64 },
215 { 0xE5, CACHE, L3, 16, 16*M, 64 },
216 { 0xE6, CACHE, L3, 16, 24*M, 64 },
217 { 0xF0, PREFETCH, NA, NA, 64, NA },
218 { 0xF1, PREFETCH, NA, NA, 128, NA },
219 { 0xFF, CACHE, NA, NA, 0, NA }
220 };
221 #define INTEL_LEAF2_DESC_NUM (sizeof(intel_cpuid_leaf2_descriptor_table) / \
222 sizeof(cpuid_cache_descriptor_t))
223
224 static inline cpuid_cache_descriptor_t *
225 cpuid_leaf2_find(uint8_t value)
226 {
227 unsigned int i;
228
229 for (i = 0; i < INTEL_LEAF2_DESC_NUM; i++)
230 if (intel_cpuid_leaf2_descriptor_table[i].value == value)
231 return &intel_cpuid_leaf2_descriptor_table[i];
232 return NULL;
233 }
234
235 /*
236 * CPU identification routines.
237 */
238
239 static i386_cpu_info_t *cpuid_cpu_infop = NULL;
240 static i386_cpu_info_t cpuid_cpu_info;
241
242 #if defined(__x86_64__)
243 static void cpuid_fn(uint32_t selector, uint32_t *result)
244 {
245 do_cpuid(selector, result);
246 DBG("cpuid_fn(0x%08x) eax:0x%08x ebx:0x%08x ecx:0x%08x edx:0x%08x\n",
247 selector, result[0], result[1], result[2], result[3]);
248 }
249 #else
250 static void cpuid_fn(uint32_t selector, uint32_t *result)
251 {
252 if (get_is64bit()) {
253 asm("call _cpuid64"
254 : "=a" (result[0]),
255 "=b" (result[1]),
256 "=c" (result[2]),
257 "=d" (result[3])
258 : "a"(selector),
259 "b" (0),
260 "c" (0),
261 "d" (0));
262 } else {
263 do_cpuid(selector, result);
264 }
265 DBG("cpuid_fn(0x%08x) eax:0x%08x ebx:0x%08x ecx:0x%08x edx:0x%08x\n",
266 selector, result[0], result[1], result[2], result[3]);
267 }
268 #endif
269
270 static const char *cache_type_str[LCACHE_MAX] = {
271 "Lnone", "L1I", "L1D", "L2U", "L3U"
272 };
273
274 /* this function is Intel-specific */
275 static void
276 cpuid_set_cache_info( i386_cpu_info_t * info_p )
277 {
278 uint32_t cpuid_result[4];
279 uint32_t reg[4];
280 uint32_t index;
281 uint32_t linesizes[LCACHE_MAX];
282 unsigned int i;
283 unsigned int j;
284 boolean_t cpuid_deterministic_supported = FALSE;
285
286 DBG("cpuid_set_cache_info(%p)\n", info_p);
287
288 bzero( linesizes, sizeof(linesizes) );
289
290 /* Get processor cache descriptor info using leaf 2. We don't use
291 * this internally, but must publish it for KEXTs.
292 */
293 cpuid_fn(2, cpuid_result);
294 for (j = 0; j < 4; j++) {
295 if ((cpuid_result[j] >> 31) == 1) /* bit31 is validity */
296 continue;
297 ((uint32_t *) info_p->cache_info)[j] = cpuid_result[j];
298 }
299 /* first byte gives number of cpuid calls to get all descriptors */
300 for (i = 1; i < info_p->cache_info[0]; i++) {
301 if (i*16 > sizeof(info_p->cache_info))
302 break;
303 cpuid_fn(2, cpuid_result);
304 for (j = 0; j < 4; j++) {
305 if ((cpuid_result[j] >> 31) == 1)
306 continue;
307 ((uint32_t *) info_p->cache_info)[4*i+j] =
308 cpuid_result[j];
309 }
310 }
311
312 /*
313 * Get cache info using leaf 4, the "deterministic cache parameters."
314 * Most processors Mac OS X supports implement this flavor of CPUID.
315 * Loop over each cache on the processor.
316 */
317 cpuid_fn(0, cpuid_result);
318 if (cpuid_result[eax] >= 4)
319 cpuid_deterministic_supported = TRUE;
320
321 for (index = 0; cpuid_deterministic_supported; index++) {
322 cache_type_t type = Lnone;
323 uint32_t cache_type;
324 uint32_t cache_level;
325 uint32_t cache_sharing;
326 uint32_t cache_linesize;
327 uint32_t cache_sets;
328 uint32_t cache_associativity;
329 uint32_t cache_size;
330 uint32_t cache_partitions;
331 uint32_t colors;
332
333 reg[eax] = 4; /* cpuid request 4 */
334 reg[ecx] = index; /* index starting at 0 */
335 cpuid(reg);
336 DBG("cpuid(4) index=%d eax=0x%x\n", index, reg[eax]);
337 cache_type = bitfield32(reg[eax], 4, 0);
338 if (cache_type == 0)
339 break; /* no more caches */
340 cache_level = bitfield32(reg[eax], 7, 5);
341 cache_sharing = bitfield32(reg[eax], 25, 14) + 1;
342 info_p->cpuid_cores_per_package
343 = bitfield32(reg[eax], 31, 26) + 1;
344 cache_linesize = bitfield32(reg[ebx], 11, 0) + 1;
345 cache_partitions = bitfield32(reg[ebx], 21, 12) + 1;
346 cache_associativity = bitfield32(reg[ebx], 31, 22) + 1;
347 cache_sets = bitfield32(reg[ecx], 31, 0) + 1;
348
349 /* Map type/levels returned by CPUID into cache_type_t */
350 switch (cache_level) {
351 case 1:
352 type = cache_type == 1 ? L1D :
353 cache_type == 2 ? L1I :
354 Lnone;
355 break;
356 case 2:
357 type = cache_type == 3 ? L2U :
358 Lnone;
359 break;
360 case 3:
361 type = cache_type == 3 ? L3U :
362 Lnone;
363 break;
364 default:
365 type = Lnone;
366 }
367
368 /* The total size of a cache is:
369 * ( linesize * sets * associativity * partitions )
370 */
371 if (type != Lnone) {
372 cache_size = cache_linesize * cache_sets *
373 cache_associativity * cache_partitions;
374 info_p->cache_size[type] = cache_size;
375 info_p->cache_sharing[type] = cache_sharing;
376 info_p->cache_partitions[type] = cache_partitions;
377 linesizes[type] = cache_linesize;
378
379 DBG(" cache_size[%s] : %d\n",
380 cache_type_str[type], cache_size);
381 DBG(" cache_sharing[%s] : %d\n",
382 cache_type_str[type], cache_sharing);
383 DBG(" cache_partitions[%s]: %d\n",
384 cache_type_str[type], cache_partitions);
385
386 /*
387 * Overwrite associativity determined via
388 * CPUID.0x80000006 -- this leaf is more
389 * accurate
390 */
391 if (type == L2U)
392 info_p->cpuid_cache_L2_associativity = cache_associativity;
393
394 /* Compute the number of page colors for this cache,
395 * which is:
396 * ( linesize * sets ) / page_size
397 *
398 * To help visualize this, consider two views of a
399 * physical address. To the cache, it is composed
400 * of a line offset, a set selector, and a tag.
401 * To VM, it is composed of a page offset, a page
402 * color, and other bits in the pageframe number:
403 *
404 * +-----------------+---------+--------+
405 * cache: | tag | set | offset |
406 * +-----------------+---------+--------+
407 *
408 * +-----------------+-------+----------+
409 * VM: | don't care | color | pg offset|
410 * +-----------------+-------+----------+
411 *
412 * The color is those bits in (set+offset) not covered
413 * by the page offset.
414 */
415 colors = ( cache_linesize * cache_sets ) >> 12;
416
417 if ( colors > vm_cache_geometry_colors )
418 vm_cache_geometry_colors = colors;
419 }
420 }
421 DBG(" vm_cache_geometry_colors: %d\n", vm_cache_geometry_colors);
422
423 /*
424 * If deterministic cache parameters are not available, use
425 * something else
426 */
427 if (info_p->cpuid_cores_per_package == 0) {
428 info_p->cpuid_cores_per_package = 1;
429
430 /* cpuid define in 1024 quantities */
431 info_p->cache_size[L2U] = info_p->cpuid_cache_size * 1024;
432 info_p->cache_sharing[L2U] = 1;
433 info_p->cache_partitions[L2U] = 1;
434
435 linesizes[L2U] = info_p->cpuid_cache_linesize;
436
437 DBG(" cache_size[L2U] : %d\n",
438 info_p->cache_size[L2U]);
439 DBG(" cache_sharing[L2U] : 1\n");
440 DBG(" cache_partitions[L2U]: 1\n");
441 DBG(" linesizes[L2U] : %d\n",
442 info_p->cpuid_cache_linesize);
443 }
444
445 /*
446 * What linesize to publish? We use the L2 linesize if any,
447 * else the L1D.
448 */
449 if ( linesizes[L2U] )
450 info_p->cache_linesize = linesizes[L2U];
451 else if (linesizes[L1D])
452 info_p->cache_linesize = linesizes[L1D];
453 else panic("no linesize");
454 DBG(" cache_linesize : %d\n", info_p->cache_linesize);
455
456 /*
457 * Extract and publish TLB information from Leaf 2 descriptors.
458 */
459 DBG(" %ld leaf2 descriptors:\n", sizeof(info_p->cache_info));
460 for (i = 1; i < sizeof(info_p->cache_info); i++) {
461 cpuid_cache_descriptor_t *descp;
462 int id;
463 int level;
464 int page;
465
466 DBG(" 0x%02x", info_p->cache_info[i]);
467 descp = cpuid_leaf2_find(info_p->cache_info[i]);
468 if (descp == NULL)
469 continue;
470
471 switch (descp->type) {
472 case TLB:
473 page = (descp->size == SMALL) ? TLB_SMALL : TLB_LARGE;
474 /* determine I or D: */
475 switch (descp->level) {
476 case INST:
477 id = TLB_INST;
478 break;
479 case DATA:
480 case DATA0:
481 case DATA1:
482 id = TLB_DATA;
483 break;
484 default:
485 continue;
486 }
487 /* determine level: */
488 switch (descp->level) {
489 case DATA1:
490 level = 1;
491 break;
492 default:
493 level = 0;
494 }
495 info_p->cpuid_tlb[id][page][level] = descp->entries;
496 break;
497 case STLB:
498 info_p->cpuid_stlb = descp->entries;
499 }
500 }
501 DBG("\n");
502 }
503
504 static void
505 cpuid_set_generic_info(i386_cpu_info_t *info_p)
506 {
507 uint32_t reg[4];
508 char str[128], *p;
509
510 DBG("cpuid_set_generic_info(%p)\n", info_p);
511
512 /* do cpuid 0 to get vendor */
513 cpuid_fn(0, reg);
514 info_p->cpuid_max_basic = reg[eax];
515 bcopy((char *)&reg[ebx], &info_p->cpuid_vendor[0], 4); /* ug */
516 bcopy((char *)&reg[ecx], &info_p->cpuid_vendor[8], 4);
517 bcopy((char *)&reg[edx], &info_p->cpuid_vendor[4], 4);
518 info_p->cpuid_vendor[12] = 0;
519
520 /* get extended cpuid results */
521 cpuid_fn(0x80000000, reg);
522 info_p->cpuid_max_ext = reg[eax];
523
524 /* check to see if we can get brand string */
525 if (info_p->cpuid_max_ext >= 0x80000004) {
526 /*
527 * The brand string 48 bytes (max), guaranteed to
528 * be NUL terminated.
529 */
530 cpuid_fn(0x80000002, reg);
531 bcopy((char *)reg, &str[0], 16);
532 cpuid_fn(0x80000003, reg);
533 bcopy((char *)reg, &str[16], 16);
534 cpuid_fn(0x80000004, reg);
535 bcopy((char *)reg, &str[32], 16);
536 for (p = str; *p != '\0'; p++) {
537 if (*p != ' ') break;
538 }
539 strlcpy(info_p->cpuid_brand_string,
540 p, sizeof(info_p->cpuid_brand_string));
541
542 if (!strncmp(info_p->cpuid_brand_string, CPUID_STRING_UNKNOWN,
543 min(sizeof(info_p->cpuid_brand_string),
544 strlen(CPUID_STRING_UNKNOWN) + 1))) {
545 /*
546 * This string means we have a firmware-programmable brand string,
547 * and the firmware couldn't figure out what sort of CPU we have.
548 */
549 info_p->cpuid_brand_string[0] = '\0';
550 }
551 }
552
553 /* Get cache and addressing info. */
554 if (info_p->cpuid_max_ext >= 0x80000006) {
555 uint32_t assoc;
556 cpuid_fn(0x80000006, reg);
557 info_p->cpuid_cache_linesize = bitfield32(reg[ecx], 7, 0);
558 assoc = bitfield32(reg[ecx],15,12);
559 /*
560 * L2 associativity is encoded, though in an insufficiently
561 * descriptive fashion, e.g. 24-way is mapped to 16-way.
562 * Represent a fully associative cache as 0xFFFF.
563 * Overwritten by associativity as determined via CPUID.4
564 * if available.
565 */
566 if (assoc == 6)
567 assoc = 8;
568 else if (assoc == 8)
569 assoc = 16;
570 else if (assoc == 0xF)
571 assoc = 0xFFFF;
572 info_p->cpuid_cache_L2_associativity = assoc;
573 info_p->cpuid_cache_size = bitfield32(reg[ecx],31,16);
574 cpuid_fn(0x80000008, reg);
575 info_p->cpuid_address_bits_physical =
576 bitfield32(reg[eax], 7, 0);
577 info_p->cpuid_address_bits_virtual =
578 bitfield32(reg[eax],15, 8);
579 }
580
581 /*
582 * Get processor signature and decode
583 * and bracket this with the approved procedure for reading the
584 * the microcode version number a.k.a. signature a.k.a. BIOS ID
585 */
586 wrmsr64(MSR_IA32_BIOS_SIGN_ID, 0);
587 cpuid_fn(1, reg);
588 info_p->cpuid_microcode_version =
589 (uint32_t) (rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);
590 info_p->cpuid_signature = reg[eax];
591 info_p->cpuid_stepping = bitfield32(reg[eax], 3, 0);
592 info_p->cpuid_model = bitfield32(reg[eax], 7, 4);
593 info_p->cpuid_family = bitfield32(reg[eax], 11, 8);
594 info_p->cpuid_type = bitfield32(reg[eax], 13, 12);
595 info_p->cpuid_extmodel = bitfield32(reg[eax], 19, 16);
596 info_p->cpuid_extfamily = bitfield32(reg[eax], 27, 20);
597 info_p->cpuid_brand = bitfield32(reg[ebx], 7, 0);
598 info_p->cpuid_features = quad(reg[ecx], reg[edx]);
599
600 /* Get "processor flag"; necessary for microcode update matching */
601 info_p->cpuid_processor_flag = (rdmsr64(MSR_IA32_PLATFORM_ID)>> 50) & 3;
602
603 /* Fold extensions into family/model */
604 if (info_p->cpuid_family == 0x0f)
605 info_p->cpuid_family += info_p->cpuid_extfamily;
606 if (info_p->cpuid_family == 0x0f || info_p->cpuid_family == 0x06)
607 info_p->cpuid_model += (info_p->cpuid_extmodel << 4);
608
609 if (info_p->cpuid_features & CPUID_FEATURE_HTT)
610 info_p->cpuid_logical_per_package =
611 bitfield32(reg[ebx], 23, 16);
612 else
613 info_p->cpuid_logical_per_package = 1;
614
615 if (info_p->cpuid_max_ext >= 0x80000001) {
616 cpuid_fn(0x80000001, reg);
617 info_p->cpuid_extfeatures =
618 quad(reg[ecx], reg[edx]);
619 }
620
621 DBG(" max_basic : %d\n", info_p->cpuid_max_basic);
622 DBG(" max_ext : 0x%08x\n", info_p->cpuid_max_ext);
623 DBG(" vendor : %s\n", info_p->cpuid_vendor);
624 DBG(" brand_string : %s\n", info_p->cpuid_brand_string);
625 DBG(" signature : 0x%08x\n", info_p->cpuid_signature);
626 DBG(" stepping : %d\n", info_p->cpuid_stepping);
627 DBG(" model : %d\n", info_p->cpuid_model);
628 DBG(" family : %d\n", info_p->cpuid_family);
629 DBG(" type : %d\n", info_p->cpuid_type);
630 DBG(" extmodel : %d\n", info_p->cpuid_extmodel);
631 DBG(" extfamily : %d\n", info_p->cpuid_extfamily);
632 DBG(" brand : %d\n", info_p->cpuid_brand);
633 DBG(" features : 0x%016llx\n", info_p->cpuid_features);
634 DBG(" extfeatures : 0x%016llx\n", info_p->cpuid_extfeatures);
635 DBG(" logical_per_package : %d\n", info_p->cpuid_logical_per_package);
636 DBG(" microcode_version : 0x%08x\n", info_p->cpuid_microcode_version);
637
638 /* Fold in the Invariant TSC feature bit, if present */
639 if (info_p->cpuid_max_ext >= 0x80000007) {
640 cpuid_fn(0x80000007, reg);
641 info_p->cpuid_extfeatures |=
642 reg[edx] & (uint32_t)CPUID_EXTFEATURE_TSCI;
643 DBG(" extfeatures : 0x%016llx\n",
644 info_p->cpuid_extfeatures);
645 }
646
647 if (info_p->cpuid_max_basic >= 0x5) {
648 cpuid_mwait_leaf_t *cmp = &info_p->cpuid_mwait_leaf;
649
650 /*
651 * Extract the Monitor/Mwait Leaf info:
652 */
653 cpuid_fn(5, reg);
654 cmp->linesize_min = reg[eax];
655 cmp->linesize_max = reg[ebx];
656 cmp->extensions = reg[ecx];
657 cmp->sub_Cstates = reg[edx];
658 info_p->cpuid_mwait_leafp = cmp;
659
660 DBG(" Monitor/Mwait Leaf:\n");
661 DBG(" linesize_min : %d\n", cmp->linesize_min);
662 DBG(" linesize_max : %d\n", cmp->linesize_max);
663 DBG(" extensions : %d\n", cmp->extensions);
664 DBG(" sub_Cstates : 0x%08x\n", cmp->sub_Cstates);
665 }
666
667 if (info_p->cpuid_max_basic >= 0x6) {
668 cpuid_thermal_leaf_t *ctp = &info_p->cpuid_thermal_leaf;
669
670 /*
671 * The thermal and Power Leaf:
672 */
673 cpuid_fn(6, reg);
674 ctp->sensor = bitfield32(reg[eax], 0, 0);
675 ctp->dynamic_acceleration = bitfield32(reg[eax], 1, 1);
676 ctp->invariant_APIC_timer = bitfield32(reg[eax], 2, 2);
677 ctp->core_power_limits = bitfield32(reg[eax], 3, 3);
678 ctp->fine_grain_clock_mod = bitfield32(reg[eax], 4, 4);
679 ctp->package_thermal_intr = bitfield32(reg[eax], 5, 5);
680 ctp->thresholds = bitfield32(reg[ebx], 3, 0);
681 ctp->ACNT_MCNT = bitfield32(reg[ecx], 0, 0);
682 ctp->hardware_feedback = bitfield32(reg[ecx], 1, 1);
683 ctp->energy_policy = bitfield32(reg[ecx], 2, 2);
684 info_p->cpuid_thermal_leafp = ctp;
685
686 DBG(" Thermal/Power Leaf:\n");
687 DBG(" sensor : %d\n", ctp->sensor);
688 DBG(" dynamic_acceleration : %d\n", ctp->dynamic_acceleration);
689 DBG(" invariant_APIC_timer : %d\n", ctp->invariant_APIC_timer);
690 DBG(" core_power_limits : %d\n", ctp->core_power_limits);
691 DBG(" fine_grain_clock_mod : %d\n", ctp->fine_grain_clock_mod);
692 DBG(" package_thermal_intr : %d\n", ctp->package_thermal_intr);
693 DBG(" thresholds : %d\n", ctp->thresholds);
694 DBG(" ACNT_MCNT : %d\n", ctp->ACNT_MCNT);
695 DBG(" hardware_feedback : %d\n", ctp->hardware_feedback);
696 DBG(" energy_policy : %d\n", ctp->energy_policy);
697 }
698
699 if (info_p->cpuid_max_basic >= 0xa) {
700 cpuid_arch_perf_leaf_t *capp = &info_p->cpuid_arch_perf_leaf;
701
702 /*
703 * Architectural Performance Monitoring Leaf:
704 */
705 cpuid_fn(0xa, reg);
706 capp->version = bitfield32(reg[eax], 7, 0);
707 capp->number = bitfield32(reg[eax], 15, 8);
708 capp->width = bitfield32(reg[eax], 23, 16);
709 capp->events_number = bitfield32(reg[eax], 31, 24);
710 capp->events = reg[ebx];
711 capp->fixed_number = bitfield32(reg[edx], 4, 0);
712 capp->fixed_width = bitfield32(reg[edx], 12, 5);
713 info_p->cpuid_arch_perf_leafp = capp;
714
715 DBG(" Architectural Performance Monitoring Leaf:\n");
716 DBG(" version : %d\n", capp->version);
717 DBG(" number : %d\n", capp->number);
718 DBG(" width : %d\n", capp->width);
719 DBG(" events_number : %d\n", capp->events_number);
720 DBG(" events : %d\n", capp->events);
721 DBG(" fixed_number : %d\n", capp->fixed_number);
722 DBG(" fixed_width : %d\n", capp->fixed_width);
723 }
724
725 if (info_p->cpuid_max_basic >= 0xd) {
726 cpuid_xsave_leaf_t *xsp = &info_p->cpuid_xsave_leaf;
727 /*
728 * XSAVE Features:
729 */
730 cpuid_fn(0xd, info_p->cpuid_xsave_leaf.extended_state);
731 info_p->cpuid_xsave_leafp = xsp;
732
733 DBG(" XSAVE Leaf:\n");
734 DBG(" EAX : 0x%x\n", xsp->extended_state[eax]);
735 DBG(" EBX : 0x%x\n", xsp->extended_state[ebx]);
736 DBG(" ECX : 0x%x\n", xsp->extended_state[ecx]);
737 DBG(" EDX : 0x%x\n", xsp->extended_state[edx]);
738 }
739
740 if (info_p->cpuid_model == CPUID_MODEL_IVYBRIDGE) {
741 /*
742 * XSAVE Features:
743 */
744 cpuid_fn(0x7, reg);
745 info_p->cpuid_leaf7_features = reg[ebx];
746
747 DBG(" Feature Leaf7:\n");
748 DBG(" EBX : 0x%x\n", reg[ebx]);
749 }
750
751 return;
752 }
753
754 static uint32_t
755 cpuid_set_cpufamily(i386_cpu_info_t *info_p)
756 {
757 uint32_t cpufamily = CPUFAMILY_UNKNOWN;
758
759 switch (info_p->cpuid_family) {
760 case 6:
761 switch (info_p->cpuid_model) {
762 #if CONFIG_YONAH
763 case 14:
764 cpufamily = CPUFAMILY_INTEL_YONAH;
765 break;
766 #endif
767 case 15:
768 cpufamily = CPUFAMILY_INTEL_MEROM;
769 break;
770 case 23:
771 cpufamily = CPUFAMILY_INTEL_PENRYN;
772 break;
773 case CPUID_MODEL_NEHALEM:
774 case CPUID_MODEL_FIELDS:
775 case CPUID_MODEL_DALES:
776 case CPUID_MODEL_NEHALEM_EX:
777 cpufamily = CPUFAMILY_INTEL_NEHALEM;
778 break;
779 case CPUID_MODEL_DALES_32NM:
780 case CPUID_MODEL_WESTMERE:
781 case CPUID_MODEL_WESTMERE_EX:
782 cpufamily = CPUFAMILY_INTEL_WESTMERE;
783 break;
784 case CPUID_MODEL_SANDYBRIDGE:
785 case CPUID_MODEL_JAKETOWN:
786 cpufamily = CPUFAMILY_INTEL_SANDYBRIDGE;
787 break;
788 case CPUID_MODEL_IVYBRIDGE:
789 cpufamily = CPUFAMILY_INTEL_IVYBRIDGE;
790 break;
791 }
792 break;
793 }
794
795 info_p->cpuid_cpufamily = cpufamily;
796 DBG("cpuid_set_cpufamily(%p) returning 0x%x\n", info_p, cpufamily);
797 return cpufamily;
798 }
799 /*
800 * Must be invoked either when executing single threaded, or with
801 * independent synchronization.
802 */
803 void
804 cpuid_set_info(void)
805 {
806 i386_cpu_info_t *info_p = &cpuid_cpu_info;
807
808 PE_parse_boot_argn("-cpuid", &cpuid_dbg, sizeof(cpuid_dbg));
809
810 bzero((void *)info_p, sizeof(cpuid_cpu_info));
811
812 cpuid_set_generic_info(info_p);
813
814 /* verify we are running on a supported CPU */
815 if ((strncmp(CPUID_VID_INTEL, info_p->cpuid_vendor,
816 min(strlen(CPUID_STRING_UNKNOWN) + 1,
817 sizeof(info_p->cpuid_vendor)))) ||
818 (cpuid_set_cpufamily(info_p) == CPUFAMILY_UNKNOWN))
819 panic("Unsupported CPU");
820
821 info_p->cpuid_cpu_type = CPU_TYPE_X86;
822 info_p->cpuid_cpu_subtype = CPU_SUBTYPE_X86_ARCH1;
823 /* Must be invoked after set_generic_info */
824 cpuid_set_cache_info(&cpuid_cpu_info);
825
826 /*
827 * Find the number of enabled cores and threads
828 * (which determines whether SMT/Hyperthreading is active).
829 */
830 switch (info_p->cpuid_cpufamily) {
831 case CPUFAMILY_INTEL_WESTMERE: {
832 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
833 info_p->core_count = bitfield32((uint32_t)msr, 19, 16);
834 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0);
835 break;
836 }
837 case CPUFAMILY_INTEL_IVYBRIDGE:
838 case CPUFAMILY_INTEL_SANDYBRIDGE:
839 case CPUFAMILY_INTEL_NEHALEM: {
840 uint64_t msr = rdmsr64(MSR_CORE_THREAD_COUNT);
841 info_p->core_count = bitfield32((uint32_t)msr, 31, 16);
842 info_p->thread_count = bitfield32((uint32_t)msr, 15, 0);
843 break;
844 }
845 }
846 if (info_p->core_count == 0) {
847 info_p->core_count = info_p->cpuid_cores_per_package;
848 info_p->thread_count = info_p->cpuid_logical_per_package;
849 }
850 DBG("cpuid_set_info():\n");
851 DBG(" core_count : %d\n", info_p->core_count);
852 DBG(" thread_count : %d\n", info_p->thread_count);
853
854 cpuid_cpu_info.cpuid_model_string = ""; /* deprecated */
855 }
856
857 static struct table {
858 uint64_t mask;
859 const char *name;
860 } feature_map[] = {
861 {CPUID_FEATURE_FPU, "FPU"},
862 {CPUID_FEATURE_VME, "VME"},
863 {CPUID_FEATURE_DE, "DE"},
864 {CPUID_FEATURE_PSE, "PSE"},
865 {CPUID_FEATURE_TSC, "TSC"},
866 {CPUID_FEATURE_MSR, "MSR"},
867 {CPUID_FEATURE_PAE, "PAE"},
868 {CPUID_FEATURE_MCE, "MCE"},
869 {CPUID_FEATURE_CX8, "CX8"},
870 {CPUID_FEATURE_APIC, "APIC"},
871 {CPUID_FEATURE_SEP, "SEP"},
872 {CPUID_FEATURE_MTRR, "MTRR"},
873 {CPUID_FEATURE_PGE, "PGE"},
874 {CPUID_FEATURE_MCA, "MCA"},
875 {CPUID_FEATURE_CMOV, "CMOV"},
876 {CPUID_FEATURE_PAT, "PAT"},
877 {CPUID_FEATURE_PSE36, "PSE36"},
878 {CPUID_FEATURE_PSN, "PSN"},
879 {CPUID_FEATURE_CLFSH, "CLFSH"},
880 {CPUID_FEATURE_DS, "DS"},
881 {CPUID_FEATURE_ACPI, "ACPI"},
882 {CPUID_FEATURE_MMX, "MMX"},
883 {CPUID_FEATURE_FXSR, "FXSR"},
884 {CPUID_FEATURE_SSE, "SSE"},
885 {CPUID_FEATURE_SSE2, "SSE2"},
886 {CPUID_FEATURE_SS, "SS"},
887 {CPUID_FEATURE_HTT, "HTT"},
888 {CPUID_FEATURE_TM, "TM"},
889 {CPUID_FEATURE_PBE, "PBE"},
890 {CPUID_FEATURE_SSE3, "SSE3"},
891 {CPUID_FEATURE_PCLMULQDQ, "PCLMULQDQ"},
892 {CPUID_FEATURE_DTES64, "DTES64"},
893 {CPUID_FEATURE_MONITOR, "MON"},
894 {CPUID_FEATURE_DSCPL, "DSCPL"},
895 {CPUID_FEATURE_VMX, "VMX"},
896 {CPUID_FEATURE_SMX, "SMX"},
897 {CPUID_FEATURE_EST, "EST"},
898 {CPUID_FEATURE_TM2, "TM2"},
899 {CPUID_FEATURE_SSSE3, "SSSE3"},
900 {CPUID_FEATURE_CID, "CID"},
901 {CPUID_FEATURE_CX16, "CX16"},
902 {CPUID_FEATURE_xTPR, "TPR"},
903 {CPUID_FEATURE_PDCM, "PDCM"},
904 {CPUID_FEATURE_SSE4_1, "SSE4.1"},
905 {CPUID_FEATURE_SSE4_2, "SSE4.2"},
906 {CPUID_FEATURE_xAPIC, "xAPIC"},
907 {CPUID_FEATURE_MOVBE, "MOVBE"},
908 {CPUID_FEATURE_POPCNT, "POPCNT"},
909 {CPUID_FEATURE_AES, "AES"},
910 {CPUID_FEATURE_VMM, "VMM"},
911 {CPUID_FEATURE_PCID, "PCID"},
912 {CPUID_FEATURE_XSAVE, "XSAVE"},
913 {CPUID_FEATURE_OSXSAVE, "OSXSAVE"},
914 {CPUID_FEATURE_SEGLIM64, "SEGLIM64"},
915 {CPUID_FEATURE_TSCTMR, "TSCTMR"},
916 {CPUID_FEATURE_AVX1_0, "AVX1.0"},
917 {CPUID_FEATURE_RDRAND, "RDRAND"},
918 {CPUID_FEATURE_F16C, "F16C"},
919 {0, 0}
920 },
921 extfeature_map[] = {
922 {CPUID_EXTFEATURE_SYSCALL, "SYSCALL"},
923 {CPUID_EXTFEATURE_XD, "XD"},
924 {CPUID_EXTFEATURE_1GBPAGE, "1GBPAGE"},
925 {CPUID_EXTFEATURE_EM64T, "EM64T"},
926 {CPUID_EXTFEATURE_LAHF, "LAHF"},
927 {CPUID_EXTFEATURE_RDTSCP, "RDTSCP"},
928 {CPUID_EXTFEATURE_TSCI, "TSCI"},
929 {0, 0}
930
931 },
932 leaf7_feature_map[] = {
933 {CPUID_LEAF7_FEATURE_RDWRFSGS, "RDWRFSGS"},
934 {CPUID_LEAF7_FEATURE_SMEP, "SMEP"},
935 {CPUID_LEAF7_FEATURE_ENFSTRG, "ENFSTRG"},
936 {0, 0}
937 };
938
939 static char *
940 cpuid_get_names(struct table *map, uint64_t bits, char *buf, unsigned buf_len)
941 {
942 size_t len = 0;
943 char *p = buf;
944 int i;
945
946 for (i = 0; map[i].mask != 0; i++) {
947 if ((bits & map[i].mask) == 0)
948 continue;
949 if (len && ((size_t) (p - buf) < (buf_len - 1)))
950 *p++ = ' ';
951 len = min(strlen(map[i].name), (size_t)((buf_len-1)-(p-buf)));
952 if (len == 0)
953 break;
954 bcopy(map[i].name, p, len);
955 p += len;
956 }
957 *p = '\0';
958 return buf;
959 }
960
961 i386_cpu_info_t *
962 cpuid_info(void)
963 {
964 /* Set-up the cpuid_info stucture lazily */
965 if (cpuid_cpu_infop == NULL) {
966 cpuid_set_info();
967 cpuid_cpu_infop = &cpuid_cpu_info;
968 }
969 return cpuid_cpu_infop;
970 }
971
972 char *
973 cpuid_get_feature_names(uint64_t features, char *buf, unsigned buf_len)
974 {
975 return cpuid_get_names(feature_map, features, buf, buf_len);
976 }
977
978 char *
979 cpuid_get_extfeature_names(uint64_t extfeatures, char *buf, unsigned buf_len)
980 {
981 return cpuid_get_names(extfeature_map, extfeatures, buf, buf_len);
982 }
983
984 char *
985 cpuid_get_leaf7_feature_names(uint64_t features, char *buf, unsigned buf_len)
986 {
987 return cpuid_get_names(leaf7_feature_map, features, buf, buf_len);
988 }
989
990 void
991 cpuid_feature_display(
992 const char *header)
993 {
994 char buf[256];
995
996 kprintf("%s: %s", header,
997 cpuid_get_feature_names(cpuid_features(), buf, sizeof(buf)));
998 if (cpuid_leaf7_features())
999 kprintf(" %s", cpuid_get_leaf7_feature_names(
1000 cpuid_leaf7_features(), buf, sizeof(buf)));
1001 kprintf("\n");
1002 if (cpuid_features() & CPUID_FEATURE_HTT) {
1003 #define s_if_plural(n) ((n > 1) ? "s" : "")
1004 kprintf(" HTT: %d core%s per package;"
1005 " %d logical cpu%s per package\n",
1006 cpuid_cpu_info.cpuid_cores_per_package,
1007 s_if_plural(cpuid_cpu_info.cpuid_cores_per_package),
1008 cpuid_cpu_info.cpuid_logical_per_package,
1009 s_if_plural(cpuid_cpu_info.cpuid_logical_per_package));
1010 }
1011 }
1012
1013 void
1014 cpuid_extfeature_display(
1015 const char *header)
1016 {
1017 char buf[256];
1018
1019 kprintf("%s: %s\n", header,
1020 cpuid_get_extfeature_names(cpuid_extfeatures(),
1021 buf, sizeof(buf)));
1022 }
1023
1024 void
1025 cpuid_cpu_display(
1026 const char *header)
1027 {
1028 if (cpuid_cpu_info.cpuid_brand_string[0] != '\0') {
1029 kprintf("%s: %s\n", header, cpuid_cpu_info.cpuid_brand_string);
1030 }
1031 }
1032
1033 unsigned int
1034 cpuid_family(void)
1035 {
1036 return cpuid_info()->cpuid_family;
1037 }
1038
1039 uint32_t
1040 cpuid_cpufamily(void)
1041 {
1042 return cpuid_info()->cpuid_cpufamily;
1043 }
1044
1045 cpu_type_t
1046 cpuid_cputype(void)
1047 {
1048 return cpuid_info()->cpuid_cpu_type;
1049 }
1050
1051 cpu_subtype_t
1052 cpuid_cpusubtype(void)
1053 {
1054 return cpuid_info()->cpuid_cpu_subtype;
1055 }
1056
1057 uint64_t
1058 cpuid_features(void)
1059 {
1060 static int checked = 0;
1061 char fpu_arg[20] = { 0 };
1062
1063 (void) cpuid_info();
1064 if (!checked) {
1065 /* check for boot-time fpu limitations */
1066 if (PE_parse_boot_argn("_fpu", &fpu_arg[0], sizeof (fpu_arg))) {
1067 printf("limiting fpu features to: %s\n", fpu_arg);
1068 if (!strncmp("387", fpu_arg, sizeof("387")) || !strncmp("mmx", fpu_arg, sizeof("mmx"))) {
1069 printf("no sse or sse2\n");
1070 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE | CPUID_FEATURE_SSE2 | CPUID_FEATURE_FXSR);
1071 } else if (!strncmp("sse", fpu_arg, sizeof("sse"))) {
1072 printf("no sse2\n");
1073 cpuid_cpu_info.cpuid_features &= ~(CPUID_FEATURE_SSE2);
1074 }
1075 }
1076 checked = 1;
1077 }
1078 return cpuid_cpu_info.cpuid_features;
1079 }
1080
1081 uint64_t
1082 cpuid_extfeatures(void)
1083 {
1084 return cpuid_info()->cpuid_extfeatures;
1085 }
1086
1087 uint64_t
1088 cpuid_leaf7_features(void)
1089 {
1090 return cpuid_info()->cpuid_leaf7_features;
1091 }
1092
1093
1094 #if MACH_KDB
1095
1096 /*
1097 * Display the cpuid
1098 * *
1099 * cp
1100 */
1101 void
1102 db_cpuid(__unused db_expr_t addr,
1103 __unused int have_addr,
1104 __unused db_expr_t count,
1105 __unused char *modif)
1106 {
1107
1108 uint32_t i, mid;
1109 uint32_t cpid[4];
1110
1111 do_cpuid(0, cpid); /* Get the first cpuid which is the number of
1112 * basic ids */
1113 db_printf("%08X - %08X %08X %08X %08X\n",
1114 0, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
1115
1116 mid = cpid[eax]; /* Set the number */
1117 for (i = 1; i <= mid; i++) { /* Dump 'em out */
1118 do_cpuid(i, cpid); /* Get the next */
1119 db_printf("%08X - %08X %08X %08X %08X\n",
1120 i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
1121 }
1122 db_printf("\n");
1123
1124 do_cpuid(0x80000000, cpid); /* Get the first extended cpuid which
1125 * is the number of extended ids */
1126 db_printf("%08X - %08X %08X %08X %08X\n",
1127 0x80000000, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
1128
1129 mid = cpid[eax]; /* Set the number */
1130 for (i = 0x80000001; i <= mid; i++) { /* Dump 'em out */
1131 do_cpuid(i, cpid); /* Get the next */
1132 db_printf("%08X - %08X %08X %08X %08X\n",
1133 i, cpid[eax], cpid[ebx], cpid[ecx], cpid[edx]);
1134 }
1135 }
1136
1137 #endif
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