iokit/Drivers/ata/drvAppleUltra33ATA/AppleUltra33ATARegs.h

   1 /*
   2  * Copyright (c) 1998-2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 /*
  23  *      PCI Control registers for Cmd646X chipset
  24  *
  25  */
  26 enum Ultra646RegsValues
  27 {
  28     kUltra646CFR                                = 0x50,         /* Configuration */
  29     kUltra646CFR_DSA1                           = 0x40,
  30     kUltra646CFR_IDEIntPRI                      = 0x04,
  31
  32     kUltra646CNTRL                              = 0x51,         /* Drive 0/1 Control Register */
  33     kUltra646CNTRL_Drive1ReadAhead              = 0x80,
  34     kUltra646CNTRL_Drive0ReadAhead              = 0x40,
  35     kUltra646CNTRL_EnableSDY                    = 0x08,
  36     kUltra646CNTRL_EnablePRI                    = 0x04,
  37
  38     kUltra646CMDTIM                             = 0x52,         /* Task file timing (all drives) */
  39     kUltra646CMDTIM_Drive01CmdActive            = 0xF0,
  40     kUltra646CMDTIM_Drive01CmdRecovery          = 0x0F,
  41
  42     kUltra646ARTTIM0                            = 0x53,         /* Drive 0 Address Setup */
  43     kUltra646ARTTIM0_Drive0AddrSetup            = 0xC0,
  44
  45     kUltra646DRWTIM0                            = 0x54,         /* Drive 0 Data Read/Write - DACK Time  */
  46     kUltra646DRWTIM0_Drive0DataActive           = 0xF0,
  47     kUltra646DRWTIM0_Drive0DataRecovery         = 0x0F,
  48
  49     kUltra646ARTTIM1                            = 0x55,         /* Drive 1 Address Setup */
  50     kUltra646ARTTIM1_Drive1AddrSetup            = 0xC0,
  51
  52     kUltra646DRWTIM1                            = 0x56,         /* Drive 1 Data Read/Write - DACK Time */
  53     kUltra646DRWTIM1_Drive1DataActive           = 0xF0,
  54     kUltra646DRWTIM1_Drive1DataRecover          = 0x0F,
  55
  56     kUltra646ARTTIM23                           = 0x57,         /* Drive 2/3 Control/Status */
  57     kUltra646ARTTIM23_AddrSetup                 = 0xC0,
  58     kUltra646ARTTIM23_IDEIntSDY                 = 0x10,
  59     kUltra646ARTTIM23_Drive3ReadAhead           = 0x08,
  60     kUltra646ARTTIM23_Drive2ReadAhead           = 0x04,
  61
  62     kUltra646DRWTIM2                            = 0x58,         /* Drive 2 Read/Write - DACK Time */
  63     kUltra646DRWTIM2_Drive2DataActive           = 0xF0,
  64     kUltra646DRWTIM2_Drive2DataRecovery         = 0x0F,
  65
  66     kUltra646BRST                               = 0x59,         /* Read Ahead Count */
  67
  68     kUltra646DRWTIM3                            = 0x5B,         /* Drive 3 Read/Write - DACK Time */
  69     kUltra646DRWTIM3_Drive3DataActive           = 0xF0,
  70     kUltra646DRWTIM3_Drive3DataRecover          = 0x0F,
  71
  72     kUltra646BMIDECR0                           = 0x70,         /* BusMaster Command Register - Primary */
  73     kUltra646BMIDECR0_PCIWritePRI               = 0x08,
  74     kUltra646BMIDECR0_StartDMAPRI               = 0x01,
  75
  76     kUltra646MRDMODE                            = 0x71,         /* DMA Master Read Mode Select */
  77     kUltra646MRDMODE_PCIReadMask                = 0x03,
  78     kUltra646MRDMODE_PCIRead                    = 0x00,
  79     kUltra646MRDMODE_PCIReadMultiple            = 0x01,
  80     kUltra646MRDMODE_IDEIntPRI                  = 0x04,
  81     kUltra646MRDMODE_IDEIntSDY                  = 0x08,
  82     kUltra646MRDMODE_IntEnablePRI               = 0x10,
  83     kUltra646MRDMODE_IntEnableSDY               = 0x20,
  84     kUltra646MRDMODE_ResetAll                   = 0x40,
  85
  86     kUltra646BMIDESR0                           = 0x72,         /* BusMaster Status Register - Primary */
  87     kUltra646BMIDESR0_Simplex                   = 0x80,
  88     kUltra646BMIDESR0_Drive1DMACap              = 0x40,
  89     kUltra646BMIDESR0_Drive0DMACap              = 0x20,
  90     kUltra646BMIDESR0_DMAIntPRI                 = 0x04,
  91     kUltra646BMIDESR0_DMAErrorPRI               = 0x02,
  92     kUltra646BMIDESR0_DMAActivePRI              = 0x01,
  93
  94     kUltra646UDIDETCR0                          = 0x73,         /* Ultra DMA Timing Control Register - Primary */
  95     kUltra646UDIDETCR0_Drive1UDMACycleTime      = 0xC0,
  96     kUltra646UDIDETCR0_Drive0UDMACycleTime      = 0x30,
  97     kUltra646UDIDETCR0_Drive1UDMAEnable         = 0x02,
  98     kUltra646UDIDETCR0_Drive0UDMAEnable         = 0x01,
  99
 100     kUltra646DTPR0                              = 0x74,         /* Descriptor Table Pointer - Primary */
 101
 102     kUltra646BMIDECR1                           = 0x78,         /* BusMaster Command Register - Secondary */
 103     kUltra646BMIDECR1_PCIWriteSDY               = 0x08,
 104     kUltra646BMIDECR1_StartDMASDY               = 0x01,
 105
 106     kUltra646BMIDESR1                           = 0x7A,         /* BusMaster Status Register - Secondary */
 107     kUltra646BMIDESR1_Simplex                   = 0x80,
 108     kUltra646BMIDESR1_Drive3DMACap              = 0x40,
 109     kUltra646BMIDESR1_Drive2DMACap              = 0x20,
 110     kUltra646BMIDESR1_DMAIntSDY                 = 0x04,
 111     kUltra646BMIDESR1_DMAErrorSDY               = 0x02,
 112     kUltra646BMIDESR1_DMAActiveSDY              = 0x01,
 113
 114     kUltra646UDIDETCR1                          = 0x7B,         /* Ultra DMA Timing Control Register - Secondary */
 115     kUltra646UDIDETCR1_Drive3UDMACycleTime      = 0xC0,
 116     kUltra646UDIDETCR1_Drive2UDMACycleTime      = 0x30,
 117     kUltra646UDIDETCR1_Drive3UDMAEnable         = 0x02,
 118     kUltra646UDIDETCR1_Drive2UDMAEnable         = 0x01,
 119
 120     kUltra646DTPR1                              = 0x7C,         /* Descriptor Table Pointer - Secondary */
 121 };
 122
 123 typedef struct
 124 {
 125     UInt32              cntrlReg;
 126     UInt32              arttimReg;
 127     UInt32              cmdtimReg;
 128     UInt32              drwtimRegPIO;
 129     UInt32              drwtimRegDMA;
 130     UInt32              udidetcrReg;
 131 } Ultra646Regs;
 132
 133
 134 typedef struct
 135 {
 136     UInt32              start;
 137     UInt32              length;
 138 } Ultra646Descriptor;
 139
 140
 141 #define IDE_SYSCLK_NS           30