osfmk/arm64/tunables/tunables_h12.s

   1 /*
   2  * Copyright (c) 2019 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
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  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 .macro APPLY_TUNABLES
  29         /***** Tunables that apply to all cores, all revisions *****/
  30         /* N/A */
  31
  32         /***** Tunables that apply to all P cores, all revisions *****/
  33         /* N/A */
  34
  35         /***** Tunables that apply to all E cores, all revisions *****/
  36         /* N/A */
  37
  38         /***** Tunables that apply to specific cores, all revisions *****/
  39         EXEC_COREEQ_REVALL MIDR_CEBU_LIGHTNING, $0, $1
  40         // rdar://53907283 ([Cebu ACC Errata] Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules.)
  41         HID_SET_BITS ARM64_REG_HID5, ARM64_REG_HID5_DisFill2cMerge, $1
  42
  43         // rdar://problem/54615539: [Cebu ACC Tunable]Cross-beat Crypto(AES/PMUL) ICache fusion is not disabled for branch uncondtional recoded instruction.
  44         HID_SET_BITS ARM64_REG_HID0, ARM64_REG_HID0_CacheFusionDisable, $1
  45
  46         // rdar://problem/50664291: [Cebu B0/B1 Tunables][PerfVerif][LSU] Post-silicon tuning of STNT widget contiguous counter threshold
  47         HID_INSERT_BITS ARM64_REG_HID4, ARM64_REG_HID4_CnfCntrThresh_mask, ARM64_REG_HID4_CnfCntrThresh_VALUE, $1
  48
  49         // rdar://problem/47744434: Barrier Load Ordering property is not satisfied for x64-loads
  50         HID_SET_BITS ARM64_REG_HID9, ARM64_REG_HID9_EnableFixBug47221499, $1
  51
  52         // rdar://problem/50664291: [Cebu B0/B1 Tunables][PerfVerif][LSU] Post-silicon tuning of STNT widget contiguous counter threshold
  53         HID_SET_BITS ARM64_REG_HID9, ARM64_REG_HID9_DisSTNTWidgetForUnalign, $1
  54
  55         // rdar://problem/47865629: RF bank and Multipass conflict forward progress widget does not handle 3+ cycle livelock
  56         HID_SET_BITS ARM64_REG_HID16, ARM64_REG_HID16_EnRs4Sec, $1
  57         HID_CLEAR_BITS ARM64_REG_HID16, ARM64_REG_HID16_DisxPickRs45, $1
  58         HID_SET_BITS ARM64_REG_HID16, ARM64_REG_HID16_EnMPxPick45, $1
  59         HID_SET_BITS ARM64_REG_HID16, ARM64_REG_HID16_EnMPCyc7, $1
  60
  61         // Prevent ordered loads from being dispatched from LSU until all prior loads have completed.
  62         // rdar://problem/34095873: AF2 ordering rules allow ARM device ordering violations
  63         HID_SET_BITS ARM64_REG_HID4, ARM64_REG_HID4_ForceNsOrdLdReqNoOlderLd, $1
  64
  65         // rdar://problem/51690962: Disable Store-Non-Temporal downgrade widget
  66         HID_SET_BITS ARM64_REG_HID4, ARM64_REG_HID4_DisSTNTWidget, $1
  67
  68         // rdar://problem/41056604: disable faster launches of uncacheable unaligned stores to workaround load/load ordering violation
  69         HID_SET_BITS ARM64_REG_HID11, ARM64_REG_HID11_DisX64NTLnchOpt, $1
  70
  71         // rdar://problem/45024523: enable aggressive LEQ throttling to work around LEQ credit leak
  72         HID_SET_BITS ARM64_REG_HID16, ARM64_REG_HID16_leqThrottleAggr, $1
  73
  74         // rdar://problem/41029832: configure dummy cycles to work around incorrect temp sensor readings on NEX power gating
  75         HID_INSERT_BITS ARM64_REG_HID13, ARM64_REG_HID13_PreCyc_mask, ARM64_REG_HID13_PreCyc_VALUE, $1
  76         EXEC_END
  77
  78         EXEC_COREEQ_REVALL MIDR_CEBU_THUNDER, $0, $1
  79         // rdar://53907283 ([Cebu ACC Errata] Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules.)
  80         HID_SET_BITS ARM64_REG_HID5, ARM64_REG_HID5_DisFill2cMerge, $1
  81
  82         // rdar://problem/48476033: Prevent store-to-load forwarding for UC memory to avoid barrier ordering violation
  83         HID_SET_BITS ARM64_REG_EHID10, ARM64_REG_EHID10_ForceWStDrainUc, $1
  84
  85         // Prevent ordered loads from being dispatched from LSU until all prior loads have completed.
  86         // rdar://problem/34095873: AF2 ordering rules allow ARM device ordering violations
  87         HID_SET_BITS ARM64_REG_EHID4, ARM64_REG_HID4_ForceNsOrdLdReqNoOlderLd, $1
  88
  89         // rdar://problem/37949166: Disable the extension of prefetcher training pipe clock gating, revert to default gating
  90         HID_SET_BITS ARM64_REG_EHID10, ARM64_REG_EHID10_rccDisPwrSavePrfClkOff, $1
  91         EXEC_END
  92
  93         EXEC_COREEQ_REVALL MIDR_TURKS, $0, $1
  94         // rdar://problem/53506680: [MP_CHECKER] Load STLFs from a completed UC/NC/NT store causing barrier ordering violation
  95         HID_SET_BITS ARM64_REG_EHID10, ARM64_REG_EHID10_ForceWStDrainUc, $1
  96         EXEC_END
  97
  98         /***** Tunables that apply to specific cores and revisions *****/
  99         /* N/A */
 100 .endmacro