pexpert/pexpert/arm64/arm64_common.h

   1 /*
   2  * Copyright (c) 2012-2015 Apple Inc. All rights reserved.
   3  */
   4
   5 #ifndef _PEXPERT_ARM64_COMMON_H
   6 #define _PEXPERT_ARM64_COMMON_H
   7
   8 #ifdef APPLE_ARM64_ARCH_FAMILY
   9
  10 #define ARM64_REG_HID0                                          S3_0_c15_c0_0
  11 #define ARM64_REG_HID0_LoopBuffDisb                             (1<<20)
  12 #define ARM64_REG_HID0_ICPrefLimitOneBrn                        (1<<25)
  13 #define ARM64_REG_HID0_PMULLFuseDisable                         (1ULL<<33)
  14 #define ARM64_REG_HID0_ICPrefDepth_bshift                       60
  15 #define ARM64_REG_HID0_ICPrefDepth_bmsk                         (7ULL <<ARM64_REG_HID0_ICPrefDepth_bshift)
  16
  17 #define ARM64_REG_EHID0                                         S3_0_c15_c0_1
  18 #define ARM64_REG_EHID0_nfpRetFwdDisb                           (1ULL<<45)
  19
  20 #define ARM64_REG_HID1                                          S3_0_c15_c1_0
  21 #define ARM64_REG_HID1_disCmpBrFusion                           (1<<14)
  22 #define ARM64_REG_HID1_rccDisStallInactiveIexCtl                (1<<24)
  23 #define ARM64_REG_HID1_disLspFlushWithContextSwitch             (1<<25)
  24 #define ARM64_REG_HID1_disAESFuseAcrossGrp                      (1<<44)
  25
  26 #define ARM64_REG_HID2                                          S3_0_c15_c2_0
  27 #define ARM64_REG_HID2_disMMUmtlbPrefetch                       (1<<13)
  28
  29 #define ARM64_REG_HID3                                          S3_0_c15_c3_0
  30 #define ARM64_REG_HID3_DisDcZvaCmdOnly                  (1<<25)
  31 #define ARM64_REG_HID3_DisXmonSnpEvictTriggerL2StarvationMode   (1<<54)
  32
  33 #define ARM64_REG_EHID3                                         S3_0_c15_c3_1
  34 #define ARM64_REG_EHID3_DisDcZvaCmdOnly                 (1<<25)
  35
  36 #define ARM64_REG_HID4                                          S3_0_c15_c4_0
  37 #define ARM64_REG_EHID4                                         S3_0_c15_c4_1
  38
  39 #define ARM64_REG_HID4_DisDcMVAOps                              (1<<11)
  40 #define ARM64_REG_HID4_DisSpecLnchRead                  (1<<33)
  41 #define ARM64_REG_HID4_ForceNsOrdLdReqNoOlderLd                 (1<<39)
  42 #define ARM64_REG_HID4_DisDcSWL2Ops                             (1<<44)
  43
  44 #define ARM64_REG_HID5                                          S3_0_c15_c5_0
  45 #define ARM64_REG_HID5_DisHwpLd                                 (1<<44)
  46 #define ARM64_REG_HID5_DisHwpSt                                 (1<<45)
  47 #define ARM64_REG_HID5_DisFullLineWr                            (1ULL << 57)
  48 #define ARM64_REG_HID5_CrdEdbSnpRsvd_mask                       (3ULL << 14)
  49 #define ARM64_REG_HID5_CrdEdbSnpRsvd_VALUE                      (2ULL << 14)
  50
  51 #define ARM64_REG_EHID5                                         S3_0_c15_c5_1
  52 #define ARM64_REG_EHID5_DisFillByp                      (1 << 35)
  53
  54 #define ARM64_REG_HID6                                          S3_0_c15_c6_0
  55 #define ARM64_REG_HID6_DisClkDivGating                          (1ULL << 55)
  56
  57 #define ARM64_REG_HID7                                          S3_0_c15_c7_0
  58 #define ARM64_REG_HID7_disNexFastFmul                           (1 << 10)
  59 #define ARM64_REG_HID7_disCrossPick2                            (1ULL << 7)
  60
  61 #define ARM64_REG_HID8                                          S3_0_c15_c8_0
  62 #define ARM64_REG_HID8_DataSetID0_VALUE                         (0xF << 4)
  63 #define ARM64_REG_HID8_DataSetID1_VALUE                         (0xF << 8)
  64 #define ARM64_REG_HID8_WkeForceStrictOrder                      (0x1ULL << 35)
  65 #define ARM64_REG_HID8_DataSetID2_VALUE                         (0xF << 56)
  66 #define ARM64_REG_HID8_DataSetID3_VALUE                         (0xF << 60)
  67
  68 #define ARM64_REG_HID9                                          S3_0_c15_c9_0
  69
  70 #define ARM64_REG_HID10                                         S3_0_c15_c10_0
  71 #define ARM64_REG_HID10_DisHwpGups                              (1ULL << 0)
  72
  73 #if defined(APPLECYCLONE) || defined(APPLETYPHOON) || defined(APPLETWISTER)
  74 #define ARM64_REG_HID11                                         S3_0_c15_c13_0
  75 #else
  76 #define ARM64_REG_HID11                                         S3_0_c15_c11_0
  77 #endif
  78 #define ARM64_REG_HID11_DisFillC1BubOpt                         (1<<7)
  79 #define ARM64_REG_HID11_DisFastDrainOpt                         (1ULL << 23)
  80
  81 #define ARM64_REG_EHID11                                        S3_0_c15_c11_1
  82 #define ARM64_REG_EHID11_SmbDrainThresh_mask                    (3ULL << 40)
  83
  84 #if defined(APPLECYCLONE) || defined(APPLETYPHOON) || defined(APPLETWISTER)
  85 #define ARM64_REG_CYC_CFG                                       S3_5_c15_c4_0
  86 #define ARM64_REG_CYC_CFG_skipInit                              (1ULL<<30)
  87 #define ARM64_REG_CYC_CFG_deepSleep                             (1ULL<<24)
  88 #else
  89 #define ARM64_REG_ACC_OVRD                                      S3_5_c15_c6_0
  90 #define ARM64_REG_ACC_OVRD_enDeepSleep                          (1ULL << 34)
  91
  92
  93 #define ARM64_REG_ACC_OVRD_dsblClkDtr                           (1ULL << 29)
  94 #define ARM64_REG_ACC_OVRD_cpmWakeUp_mask                       (3ULL << 27)
  95 #define ARM64_REG_ACC_OVRD_cpmWakeUp_force                      (3ULL << 27)
  96 #define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_mask                     (3ULL << 25)
  97 #define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_deny                     (2ULL << 25)
  98 #define ARM64_REG_ACC_OVRD_ok2PwrDnCPM_deepsleep                (3ULL << 25)
  99 #define ARM64_REG_ACC_OVRD_ok2TrDnLnk_mask                      (3ULL << 17)
 100 #define ARM64_REG_ACC_OVRD_ok2TrDnLnk_deepsleep                 (3ULL << 17)
 101 #define ARM64_REG_ACC_OVRD_disL2Flush4AccSlp_mask               (3ULL << 15)
 102 #define ARM64_REG_ACC_OVRD_disL2Flush4AccSlp_deepsleep          (2ULL << 15)
 103 #define ARM64_REG_ACC_OVRD_ok2PwrDnSRM_mask                     (3ULL << 13)
 104 #define ARM64_REG_ACC_OVRD_ok2PwrDnSRM_deepsleep                (3ULL << 13)
 105 #endif
 106
 107 #define ARM64_REG_CYC_OVRD                                      S3_5_c15_c5_0
 108 #define ARM64_REG_CYC_OVRD_ok2pwrdn_force_up                    (2<<24)
 109 #define ARM64_REG_CYC_OVRD_ok2pwrdn_force_down                  (3<<24)
 110
 111
 112 #define ARM64_REG_LSU_ERR_STS                           S3_3_c15_c0_0
 113 #define ARM64_REG_LSU_ERR_STS_L1DTlbMultiHitEN  (1ULL<<54)
 114
 115 #define ARM64_REG_E_LSU_ERR_STS                         S3_3_c15_c2_0
 116
 117 #define ARM64_REG_LSU_ERR_CTL                           S3_3_c15_c1_0
 118 #define ARM64_REG_LSU_ERR_CTL_L1DTlbMultiHitEN  (1ULL<<3)
 119
 120 #define ARM64_REG_FED_ERR_STS                           S3_4_C15_C0_0
 121
 122 #define ARM64_REG_E_FED_ERR_STS                         S3_4_C15_C0_2
 123
 124 #define ARM64_REG_MMU_ERR_STS                           S3_6_c15_c0_0
 125
 126 #define ARM64_REG_E_MMU_ERR_STS                         s3_6_c15_c2_0
 127
 128 #define ARM64_REG_L2C_ERR_STS                           S3_3_c15_c8_0
 129
 130 #define ARM64_REG_L2C_ERR_ADR                           S3_3_c15_c9_0
 131
 132 #define ARM64_REG_L2C_ERR_INF                           S3_3_c15_c10_0
 133
 134 #define ARM64_REG_MIGSTS_EL1                            S3_4_c15_c0_4
 135
 136 #if defined(HAS_KTRR)
 137
 138 #ifdef ASSEMBLER
 139 #define ARM64_REG_KTRR_LOWER_EL1                        S3_4_c15_c2_3
 140 #define ARM64_REG_KTRR_UPPER_EL1                        S3_4_c15_c2_4
 141 #define ARM64_REG_KTRR_LOCK_EL1                         S3_4_c15_c2_2
 142 #else
 143 #define ARM64_REG_KTRR_LOWER_EL1                        "S3_4_c15_c2_3"
 144 #define ARM64_REG_KTRR_UPPER_EL1                        "S3_4_c15_c2_4"
 145 #define ARM64_REG_KTRR_LOCK_EL1                         "S3_4_c15_c2_2"
 146 #endif /* ASSEMBLER */
 147
 148 #endif /* defined (HAS_KTRR) */
 149
 150
 151
 152
 153 #endif  /* APPLE_ARM64_ARCH_FAMILY */
 154
 155
 156
 157
 158
 159 #define MPIDR_PNE_SHIFT                16       // pcore not ecore
 160 #define MPIDR_PNE                      (1 << MPIDR_PNE_SHIFT)
 161
 162 #ifdef ASSEMBLER
 163
 164 /*
 165  *  arg0: register in which to store result
 166  *       0=>not a p-core, non-zero=>p-core
 167  */
 168 .macro ARM64_IS_PCORE
 169 .endmacro
 170
 171 /*
 172  * reads a special purpose register, using a different msr for e- vs. p-cores
 173  * arg0: register indicating the current core type, see ARM64_IS_PCORE
 174  * arg1: register in which to store the result of the read
 175  * arg2: SPR to use for e-core
 176  * arg3: SPR to use for p-core or non-AMP architecture
 177  */
 178 .macro ARM64_READ_EP_SPR
 179         mrs             $1, $3
 180 2:
 181 .endmacro
 182
 183 /*
 184  * writes a special purpose register, using a different msr for e- vs. p-cores
 185  * arg0: register indicating the current core type, see ARM64_IS_PCORE
 186  * arg1: register containing the value to write
 187  * arg2: SPR to use for e-core
 188  * arg3: SPR to use for p-core or non-AMP architecture
 189  */
 190 .macro ARM64_WRITE_EP_SPR
 191         msr             $3, $1
 192 2:
 193 .endmacro
 194
 195 #endif /* ASSEMBLER */
 196
 197 #endif /* ! _PEXPERT_ARM_ARM64_H */