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1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23 /*
24 * clock_speed_asm.s - Uses the Via timer, decrementer, and counter
25 * to determine the clock and bus rates.
26 *
27 * (c) Apple Computer, Inc. 1998-9
28 *
29 * Writen by: Josh de Cesare
30 *
31 */
32
33 #include <ppc/asm.h>
34
35 // constants for the via
36 #define CountLow 0x800
37 #define CountHigh 0xa00
38 #define LatchLow 0xc00
39 #define LatchHigh 0xe00
40
41
42 // void pe_run_clock_test(clock_test_data *data)
43 //
44 // data points to the base address of the via and two longs
45 // for storing the via and dec results.
46 //
47 // The basic idea is this...
48 // Use the counter register to execute a loop that will take
49 // 10,000,000 processor clocks. Time it using both the via counter
50 // and the time base. Return the number of ticks for both so the
51 // raw values for processor and bus speed can be calculated.
52 ENTRY(pe_run_clock_test, TAG_NO_FRAME_USED)
53
54 li r4, 1 ; flag for cache load
55 li r5, 1 ; Only once through this time
56 lwz r9, 0(r3) ; r9 is the via addr
57
58 L_again:
59 mtctr r5 ; set the count
60 li r5, 0xff ; Start the counter at 0xffff
61 stb r5, CountLow(r9) ; clear the via counter
62 eieio
63 stb r5, CountHigh(r9)
64 eieio
65 mftb r10 ; save starting value of the time base
66 isync
67
68 L_loop:
69 addi r5, r5, 1 ; 8 adds for 8 cycles
70 addi r5, r5, 2 ; the bdnz should be 0 cycles
71 addi r5, r5, 3
72 addi r5, r5, 4
73 addi r5, r5, 5
74 addi r5, r5, 6
75 addi r5, r5, 7
76 addi r5, r5, 8
77 bdnz L_loop
78
79 sync
80 mftb r5 ; save the raw time base value
81 lbz r6, CountHigh(r9) ; get the via counter values
82 eieio
83 lbz r7, CountLow(r9)
84 eieio
85 lbz r8, CountHigh(r9)
86 eieio
87
88 cmpi cr0, r4, 1 ; see if the was the cache run
89 bne L_finish_up ; nope, we are done.
90
91 li r4, 0 ; set flag for the real test
92 li r5, 0x12d0 ; set the initial count to 1.25e+6
93 oris r5, r5, 0x13
94 b L_again
95
96 L_finish_up:
97 cmpi cr0, r7, 0 ; if L1 is zero then H1 is good.
98 beq L_use_H1 ; else H2 will be good.
99
100 mr r6, r8 ; use H2 instead.
101
102 L_use_H1:
103 rlwimi r7, r6, 8, 16, 23
104 not r6, r7 ; neg - 1 is not
105 andi. r6, r6, 0xffff
106 stw r6, 4(r3) ; save via ticks
107
108 sub r5, r5, r10 ; r5 is the number of time base ticks
109 stw r5, 8(r3) ; save time base ticks
110
111 blr