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29 #include <i386/machine_routines.h>
30 #include <i386/io_map_entries.h>
31 #include <i386/cpuid.h>
33 #include <mach/processor.h>
34 #include <kern/processor.h>
35 #include <kern/machine.h>
36 #include <kern/cpu_data.h>
37 #include <kern/cpu_number.h>
38 #include <kern/thread.h>
39 #include <i386/machine_cpu.h>
40 #include <i386/lapic.h>
41 #include <i386/lock.h>
42 #include <i386/mp_events.h>
43 #include <i386/pmCPU.h>
44 #include <i386/trap.h>
46 #include <i386/cpu_threads.h>
47 #include <i386/proc_reg.h>
48 #include <mach/vm_param.h>
49 #include <i386/pmap.h>
50 #include <i386/pmap_internal.h>
51 #include <i386/misc_protos.h>
54 #define DBG(x...) kprintf("DBG: " x)
59 extern void wakeup(void *);
61 static int max_cpus_initialized
= 0;
63 unsigned int LockTimeOut
;
64 unsigned int LockTimeOutTSC
;
65 unsigned int MutexSpin
;
66 uint64_t LastDebuggerEntryAllowance
;
67 uint64_t delay_spin_threshold
;
69 extern uint64_t panic_restart_timeout
;
71 boolean_t virtualized
= FALSE
;
73 #define MAX_CPUS_SET 0x1
74 #define MAX_CPUS_WAIT 0x2
76 /* IO memory map services */
78 /* Map memory map IO space */
79 vm_offset_t
ml_io_map(
80 vm_offset_t phys_addr
,
83 return(io_map(phys_addr
,size
,VM_WIMG_IO
));
86 /* boot memory allocation */
87 vm_offset_t
ml_static_malloc(
88 __unused vm_size_t size
)
90 return((vm_offset_t
)NULL
);
94 void ml_get_bouncepool_info(vm_offset_t
*phys_addr
, vm_size_t
*size
)
105 #if defined(__x86_64__)
106 return (vm_offset_t
)(((unsigned long) paddr
) | VM_MIN_KERNEL_ADDRESS
);
108 return (vm_offset_t
)((paddr
) | LINEAR_KERNEL_ADDRESS
);
114 * Routine: ml_static_mfree
124 uint32_t freed_pages
= 0;
125 assert(vaddr
>= VM_MIN_KERNEL_ADDRESS
);
127 assert((vaddr
& (PAGE_SIZE
-1)) == 0); /* must be page aligned */
129 for (vaddr_cur
= vaddr
;
130 vaddr_cur
< round_page_64(vaddr
+size
);
131 vaddr_cur
+= PAGE_SIZE
) {
132 ppn
= pmap_find_phys(kernel_pmap
, vaddr_cur
);
133 if (ppn
!= (vm_offset_t
)NULL
) {
134 kernel_pmap
->stats
.resident_count
++;
135 if (kernel_pmap
->stats
.resident_count
>
136 kernel_pmap
->stats
.resident_max
) {
137 kernel_pmap
->stats
.resident_max
=
138 kernel_pmap
->stats
.resident_count
;
140 pmap_remove(kernel_pmap
, vaddr_cur
, vaddr_cur
+PAGE_SIZE
);
141 assert(pmap_valid_page(ppn
));
143 if (IS_MANAGED_PAGE(ppn
)) {
144 vm_page_create(ppn
,(ppn
+1));
145 vm_page_wire_count
--;
151 kprintf("ml_static_mfree: Released 0x%x pages at VA %p, size:0x%llx, last ppn: 0x%x\n", freed_pages
, (void *)vaddr
, (uint64_t)size
, ppn
);
156 /* virtual to physical on wired pages */
157 vm_offset_t
ml_vtophys(
160 return (vm_offset_t
)kvtophys(vaddr
);
164 * Routine: ml_nofault_copy
165 * Function: Perform a physical mode copy if the source and
166 * destination have valid translations in the kernel pmap.
167 * If translations are present, they are assumed to
168 * be wired; i.e. no attempt is made to guarantee that the
169 * translations obtained remained valid for
170 * the duration of the copy process.
173 vm_size_t
ml_nofault_copy(
174 vm_offset_t virtsrc
, vm_offset_t virtdst
, vm_size_t size
)
176 addr64_t cur_phys_dst
, cur_phys_src
;
177 uint32_t count
, nbytes
= 0;
180 if (!(cur_phys_src
= kvtophys(virtsrc
)))
182 if (!(cur_phys_dst
= kvtophys(virtdst
)))
184 if (!pmap_valid_page(i386_btop(cur_phys_dst
)) || !pmap_valid_page(i386_btop(cur_phys_src
)))
186 count
= (uint32_t)(PAGE_SIZE
- (cur_phys_src
& PAGE_MASK
));
187 if (count
> (PAGE_SIZE
- (cur_phys_dst
& PAGE_MASK
)))
188 count
= (uint32_t)(PAGE_SIZE
- (cur_phys_dst
& PAGE_MASK
));
190 count
= (uint32_t)size
;
192 bcopy_phys(cur_phys_src
, cur_phys_dst
, count
);
203 /* Interrupt handling */
205 /* Initialize Interrupts */
206 void ml_init_interrupt(void)
208 (void) ml_set_interrupts_enabled(TRUE
);
212 /* Get Interrupts Enabled */
213 boolean_t
ml_get_interrupts_enabled(void)
217 __asm__
volatile("pushf; pop %0" : "=r" (flags
));
218 return (flags
& EFL_IF
) != 0;
221 /* Set Interrupts Enabled */
222 boolean_t
ml_set_interrupts_enabled(boolean_t enable
)
227 __asm__
volatile("pushf; pop %0" : "=r" (flags
));
229 istate
= ((flags
& EFL_IF
) != 0);
232 __asm__
volatile("sti;nop");
234 if ((get_preemption_level() == 0) && (*ast_pending() & AST_URGENT
))
235 __asm__
volatile ("int $0xff");
239 __asm__
volatile("cli");
245 /* Check if running at interrupt context */
246 boolean_t
ml_at_interrupt_context(void)
248 return get_interrupt_level() != 0;
251 void ml_get_power_state(boolean_t
*icp
, boolean_t
*pidlep
) {
252 *icp
= (get_interrupt_level() != 0);
253 /* These will be technically inaccurate for interrupts that occur
254 * successively within a single "idle exit" event, but shouldn't
255 * matter statistically.
257 *pidlep
= (current_cpu_datap()->lcpu
.package
->num_idle
== topoParms
.nLThreadsPerPackage
);
260 /* Generate a fake interrupt */
261 void ml_cause_interrupt(void)
263 panic("ml_cause_interrupt not defined yet on Intel");
266 void ml_thread_policy(
268 __unused
unsigned policy_id
,
269 unsigned policy_info
)
271 if (policy_info
& MACHINE_NETWORK_WORKLOOP
) {
272 spl_t s
= splsched();
276 set_priority(thread
, thread
->priority
+ 1);
278 thread_unlock(thread
);
283 /* Initialize Interrupts */
284 void ml_install_interrupt_handler(
288 IOInterruptHandler handler
,
291 boolean_t current_state
;
293 current_state
= ml_get_interrupts_enabled();
295 PE_install_interrupt_handler(nub
, source
, target
,
296 (IOInterruptHandler
) handler
, refCon
);
298 (void) ml_set_interrupts_enabled(current_state
);
300 initialize_screen(NULL
, kPEAcquireScreen
);
306 processor_t processor
)
308 cpu_interrupt(processor
->cpu_id
);
314 processor_t
*processor_out
,
318 cpu_data_t
*this_cpu_datap
;
320 this_cpu_datap
= cpu_data_alloc(boot_cpu
);
321 if (this_cpu_datap
== NULL
) {
324 target_cpu
= this_cpu_datap
->cpu_number
;
325 assert((boot_cpu
&& (target_cpu
== 0)) ||
326 (!boot_cpu
&& (target_cpu
!= 0)));
328 lapic_cpu_map(lapic_id
, target_cpu
);
330 /* The cpu_id is not known at registration phase. Just do
333 this_cpu_datap
->cpu_phys_number
= lapic_id
;
335 this_cpu_datap
->cpu_console_buf
= console_cpu_alloc(boot_cpu
);
336 if (this_cpu_datap
->cpu_console_buf
== NULL
)
339 this_cpu_datap
->cpu_chud
= chudxnu_cpu_alloc(boot_cpu
);
340 if (this_cpu_datap
->cpu_chud
== NULL
)
344 cpu_thread_alloc(this_cpu_datap
->cpu_number
);
345 if (this_cpu_datap
->lcpu
.core
== NULL
)
348 #if NCOPY_WINDOWS > 0
349 this_cpu_datap
->cpu_pmap
= pmap_cpu_alloc(boot_cpu
);
350 if (this_cpu_datap
->cpu_pmap
== NULL
)
354 this_cpu_datap
->cpu_processor
= cpu_processor_alloc(boot_cpu
);
355 if (this_cpu_datap
->cpu_processor
== NULL
)
358 * processor_init() deferred to topology start
359 * because "slot numbers" a.k.a. logical processor numbers
360 * are not yet finalized.
364 *processor_out
= this_cpu_datap
->cpu_processor
;
369 cpu_processor_free(this_cpu_datap
->cpu_processor
);
370 #if NCOPY_WINDOWS > 0
371 pmap_cpu_free(this_cpu_datap
->cpu_pmap
);
373 chudxnu_cpu_free(this_cpu_datap
->cpu_chud
);
374 console_cpu_free(this_cpu_datap
->cpu_console_buf
);
380 ml_processor_register(
383 processor_t
*processor_out
,
387 static boolean_t done_topo_sort
= FALSE
;
388 static uint32_t num_registered
= 0;
390 /* Register all CPUs first, and track max */
395 DBG( "registering CPU lapic id %d\n", lapic_id
);
397 return register_cpu( lapic_id
, processor_out
, boot_cpu
);
400 /* Sort by topology before we start anything */
401 if( !done_topo_sort
)
403 DBG( "about to start CPUs. %d registered\n", num_registered
);
405 cpu_topology_sort( num_registered
);
406 done_topo_sort
= TRUE
;
409 /* Assign the cpu ID */
410 uint32_t cpunum
= -1;
411 cpu_data_t
*this_cpu_datap
= NULL
;
413 /* find cpu num and pointer */
414 cpunum
= ml_get_cpuid( lapic_id
);
416 if( cpunum
== 0xFFFFFFFF ) /* never heard of it? */
417 panic( "trying to start invalid/unregistered CPU %d\n", lapic_id
);
419 this_cpu_datap
= cpu_datap(cpunum
);
422 this_cpu_datap
->cpu_id
= cpu_id
;
425 *processor_out
= this_cpu_datap
->cpu_processor
;
427 /* OK, try and start this CPU */
428 return cpu_topology_start_cpu( cpunum
);
433 ml_cpu_get_info(ml_cpu_info_t
*cpu_infop
)
435 boolean_t os_supports_sse
;
436 i386_cpu_info_t
*cpuid_infop
;
438 if (cpu_infop
== NULL
)
442 * Are we supporting MMX/SSE/SSE2/SSE3?
443 * As distinct from whether the cpu has these capabilities.
445 os_supports_sse
= !!(get_cr4() & CR4_OSXMM
);
447 if (ml_fpu_avx_enabled())
448 cpu_infop
->vector_unit
= 9;
449 else if ((cpuid_features() & CPUID_FEATURE_SSE4_2
) && os_supports_sse
)
450 cpu_infop
->vector_unit
= 8;
451 else if ((cpuid_features() & CPUID_FEATURE_SSE4_1
) && os_supports_sse
)
452 cpu_infop
->vector_unit
= 7;
453 else if ((cpuid_features() & CPUID_FEATURE_SSSE3
) && os_supports_sse
)
454 cpu_infop
->vector_unit
= 6;
455 else if ((cpuid_features() & CPUID_FEATURE_SSE3
) && os_supports_sse
)
456 cpu_infop
->vector_unit
= 5;
457 else if ((cpuid_features() & CPUID_FEATURE_SSE2
) && os_supports_sse
)
458 cpu_infop
->vector_unit
= 4;
459 else if ((cpuid_features() & CPUID_FEATURE_SSE
) && os_supports_sse
)
460 cpu_infop
->vector_unit
= 3;
461 else if (cpuid_features() & CPUID_FEATURE_MMX
)
462 cpu_infop
->vector_unit
= 2;
464 cpu_infop
->vector_unit
= 0;
466 cpuid_infop
= cpuid_info();
468 cpu_infop
->cache_line_size
= cpuid_infop
->cache_linesize
;
470 cpu_infop
->l1_icache_size
= cpuid_infop
->cache_size
[L1I
];
471 cpu_infop
->l1_dcache_size
= cpuid_infop
->cache_size
[L1D
];
473 if (cpuid_infop
->cache_size
[L2U
] > 0) {
474 cpu_infop
->l2_settings
= 1;
475 cpu_infop
->l2_cache_size
= cpuid_infop
->cache_size
[L2U
];
477 cpu_infop
->l2_settings
= 0;
478 cpu_infop
->l2_cache_size
= 0xFFFFFFFF;
481 if (cpuid_infop
->cache_size
[L3U
] > 0) {
482 cpu_infop
->l3_settings
= 1;
483 cpu_infop
->l3_cache_size
= cpuid_infop
->cache_size
[L3U
];
485 cpu_infop
->l3_settings
= 0;
486 cpu_infop
->l3_cache_size
= 0xFFFFFFFF;
491 ml_init_max_cpus(unsigned long max_cpus
)
493 boolean_t current_state
;
495 current_state
= ml_set_interrupts_enabled(FALSE
);
496 if (max_cpus_initialized
!= MAX_CPUS_SET
) {
497 if (max_cpus
> 0 && max_cpus
<= MAX_CPUS
) {
499 * Note: max_cpus is the number of enabled processors
500 * that ACPI found; max_ncpus is the maximum number
501 * that the kernel supports or that the "cpus="
502 * boot-arg has set. Here we take int minimum.
504 machine_info
.max_cpus
= (integer_t
)MIN(max_cpus
, max_ncpus
);
506 if (max_cpus_initialized
== MAX_CPUS_WAIT
)
507 wakeup((event_t
)&max_cpus_initialized
);
508 max_cpus_initialized
= MAX_CPUS_SET
;
510 (void) ml_set_interrupts_enabled(current_state
);
514 ml_get_max_cpus(void)
516 boolean_t current_state
;
518 current_state
= ml_set_interrupts_enabled(FALSE
);
519 if (max_cpus_initialized
!= MAX_CPUS_SET
) {
520 max_cpus_initialized
= MAX_CPUS_WAIT
;
521 assert_wait((event_t
)&max_cpus_initialized
, THREAD_UNINT
);
522 (void)thread_block(THREAD_CONTINUE_NULL
);
524 (void) ml_set_interrupts_enabled(current_state
);
525 return(machine_info
.max_cpus
);
529 * Routine: ml_init_lock_timeout
533 ml_init_lock_timeout(void)
537 uint64_t default_timeout_ns
= NSEC_PER_SEC
>>2;
541 if (PE_parse_boot_argn("slto_us", &slto
, sizeof (slto
)))
542 default_timeout_ns
= slto
* NSEC_PER_USEC
;
544 /* LockTimeOut is absolutetime, LockTimeOutTSC is in TSC ticks */
545 nanoseconds_to_absolutetime(default_timeout_ns
, &abstime
);
546 LockTimeOut
= (uint32_t) abstime
;
547 LockTimeOutTSC
= (uint32_t) tmrCvt(abstime
, tscFCvtn2t
);
549 if (PE_parse_boot_argn("mtxspin", &mtxspin
, sizeof (mtxspin
))) {
550 if (mtxspin
> USEC_PER_SEC
>>4)
551 mtxspin
= USEC_PER_SEC
>>4;
552 nanoseconds_to_absolutetime(mtxspin
*NSEC_PER_USEC
, &abstime
);
554 nanoseconds_to_absolutetime(10*NSEC_PER_USEC
, &abstime
);
556 MutexSpin
= (unsigned int)abstime
;
558 nanoseconds_to_absolutetime(4ULL * NSEC_PER_SEC
, &LastDebuggerEntryAllowance
);
559 if (PE_parse_boot_argn("panic_restart_timeout", &prt
, sizeof (prt
)))
560 nanoseconds_to_absolutetime(prt
* NSEC_PER_SEC
, &panic_restart_timeout
);
561 virtualized
= ((cpuid_features() & CPUID_FEATURE_VMM
) != 0);
562 interrupt_latency_tracker_setup();
566 * Threshold above which we should attempt to block
567 * instead of spinning for clock_delay_until().
570 ml_init_delay_spin_threshold(int threshold_us
)
572 nanoseconds_to_absolutetime(threshold_us
* NSEC_PER_USEC
, &delay_spin_threshold
);
576 ml_delay_should_spin(uint64_t interval
)
578 return (interval
< delay_spin_threshold
) ? TRUE
: FALSE
;
582 * This is called from the machine-independent layer
583 * to perform machine-dependent info updates. Defer to cpu_thread_init().
592 * This is called from the machine-independent layer
593 * to perform machine-dependent info updates.
598 i386_deactivate_cpu();
604 * The following are required for parts of the kernel
605 * that cannot resolve these functions as inlines:
607 extern thread_t
current_act(void);
611 return(current_thread_fast());
614 #undef current_thread
615 extern thread_t
current_thread(void);
619 return(current_thread_fast());
623 boolean_t
ml_is64bit(void) {
625 return (cpu_mode_is64bit());
629 boolean_t
ml_thread_is64bit(thread_t thread
) {
631 return (thread_is_64bit(thread
));
635 boolean_t
ml_state_is64bit(void *saved_state
) {
637 return is_saved_state64(saved_state
);
640 void ml_cpu_set_ldt(int selector
)
643 * Avoid loading the LDT
644 * if we're setting the KERNEL LDT and it's already set.
646 if (selector
== KERNEL_LDT
&&
647 current_cpu_datap()->cpu_ldt
== KERNEL_LDT
)
650 #if defined(__i386__)
652 * If 64bit this requires a mode switch (and back).
654 if (cpu_mode_is64bit())
655 ml_64bit_lldt(selector
);
661 current_cpu_datap()->cpu_ldt
= selector
;
664 void ml_fp_setvalid(boolean_t value
)
669 uint64_t ml_cpu_int_event_time(void)
671 return current_cpu_datap()->cpu_int_event_time
;
674 vm_offset_t
ml_stack_remaining(void)
676 uintptr_t local
= (uintptr_t) &local
;
678 if (ml_at_interrupt_context() != 0) {
679 return (local
- (current_cpu_datap()->cpu_int_stack_top
- INTSTACK_SIZE
));
681 return (local
- current_thread()->kernel_stack
);
686 kernel_preempt_check(void)
691 assert(get_preemption_level() == 0);
693 __asm__
volatile("pushf; pop %0" : "=r" (flags
));
695 intr
= ((flags
& EFL_IF
) != 0);
697 if ((*ast_pending() & AST_URGENT
) && intr
== TRUE
) {
699 * can handle interrupts and preemptions
704 * now cause the PRE-EMPTION trap
706 __asm__
volatile ("int %0" :: "N" (T_PREEMPT
));
710 boolean_t
machine_timeout_suspended(void) {
711 return (virtualized
|| pmap_tlb_flush_timeout
|| spinlock_timed_out
|| panic_active() || mp_recent_debugger_activity());