osfmk/ppc/POWERMAC/scc_8530.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * Copyright (c) 1999-2003 Apple Computer, Inc.  All Rights Reserved.
   7  *
   8  * This file contains Original Code and/or Modifications of Original Code
   9  * as defined in and that are subject to the Apple Public Source License
  10  * Version 2.0 (the 'License'). You may not use this file except in
  11  * compliance with the License. Please obtain a copy of the License at
  12  * http://www.opensource.apple.com/apsl/ and read it before using this
  13  * file.
  14  *
  15  * The Original Code and all software distributed under the License are
  16  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  17  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  18  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  20  * Please see the License for the specific language governing rights and
  21  * limitations under the License.
  22  *
  23  * @APPLE_LICENSE_HEADER_END@
  24  */
  25 /*
  26  * @OSF_COPYRIGHT@
  27  */
  28 /*
  29  * @APPLE_FREE_COPYRIGHT@
  30  */
  31 /*
  32  * Mach Operating System
  33  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
  34  * All Rights Reserved.
  35  *
  36  * Permission to use, copy, modify and distribute this software and its
  37  * documentation is hereby granted, provided that both the copyright
  38  * notice and this permission notice appear in all copies of the
  39  * software, derivative works or modified versions, and any portions
  40  * thereof, and that both notices appear in supporting documentation.
  41  *
  42  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
  43  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
  44  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
  45  *
  46  * Carnegie Mellon requests users of this software to return to
  47  *
  48  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
  49  *  School of Computer Science
  50  *  Carnegie Mellon University
  51  *  Pittsburgh PA 15213-3890
  52  *
  53  * any improvements or extensions that they make and grant Carnegie Mellon
  54  * the rights to redistribute these changes.
  55  */
  56 /*
  57  */
  58 /*
  59  *      File: scc_8530.h
  60  *      Author: Alessandro Forin, Carnegie Mellon University
  61  *      Date:   6/91
  62  *
  63  *      Definitions for the Zilog Z8530 SCC serial line chip
  64  */
  65
  66 #ifndef _SCC_8530_H_
  67 #define _SCC_8530_H_
  68
  69 /*
  70  * Register map, needs definition of the alignment
  71  * used on the specific machine.
  72  * #define the 'scc_register_t' data type before
  73  * including this header file.  For restrictions on
  74  * access modes define the set/get_datum macros.
  75  * We provide defaults ifnot.
  76  */
  77
  78
  79 #define SCC_CHANNEL_A   1
  80 #define SCC_CHANNEL_B   0
  81
  82 #define SCC_MODEM       SCC_CHANNEL_A
  83 #define SCC_PRINTER     SCC_CHANNEL_B
  84
  85 #define SCC_DATA_OFFSET 4
  86
  87 typedef unsigned char *scc_regmap_t;
  88
  89 extern void     powermac_scc_set_datum(scc_regmap_t regs, unsigned int offset, unsigned char value);
  90 extern unsigned char powermac_scc_get_datum(scc_regmap_t regs, unsigned int offset);
  91
  92 #define scc_set_datum(regs, d, v)       powermac_scc_set_datum(regs, (d), (v))
  93 #define scc_get_datum(regs, d,v)        (v)  = powermac_scc_get_datum(regs, (d));
  94
  95 #define scc_init_reg(regs,chan)         { \
  96                 char tmp; \
  97                 scc_get_datum(regs, ((chan)<<1),tmp); \
  98                 scc_get_datum(regs, ((chan)<<1),tmp); \
  99         }
 100
 101 #define scc_read_reg(regs,chan,reg,val) { \
 102                 scc_set_datum(regs, ((chan)<<1),reg); \
 103                 scc_get_datum(regs, ((chan)<<1),val); \
 104         }
 105
 106 #define scc_read_reg_zero(regs,chan,val)        { \
 107                 scc_get_datum(regs, ((chan)<<1),val); \
 108         }
 109
 110 #define scc_write_reg(regs,chan,reg,val)        { \
 111                 scc_set_datum(regs, ((chan)<<1),reg); \
 112                 scc_set_datum(regs, ((chan)<<1),val); \
 113         }
 114
 115 #define scc_write_reg_zero(regs,chan,val) { \
 116                 scc_set_datum(regs, ((chan)<<1),val); \
 117         }
 118
 119 #define scc_read_data(regs,chan,val)    { \
 120                 scc_get_datum(regs, ((chan)<<1)+SCC_DATA_OFFSET,val); \
 121         }
 122
 123 #define scc_write_data(regs,chan,val) { \
 124                 scc_set_datum(regs, ((chan)<<1)+SCC_DATA_OFFSET,val); \
 125         }
 126
 127
 128 /*
 129  * Addressable registers
 130  */
 131
 132 #define SCC_RR0         0       /* status register */
 133 #define SCC_RR1         1       /* special receive conditions */
 134 #define SCC_RR2         2       /* (modified) interrupt vector */
 135 #define SCC_RR3         3       /* interrupts pending (cha A only) */
 136 #define SCC_RR8         8       /* recv buffer (alias for data) */
 137 #define SCC_RR10        10      /* sdlc status */
 138 #define SCC_RR12        12      /* BRG constant, low part */
 139 #define SCC_RR13        13      /* BRG constant, high part */
 140 #define SCC_RR15        15      /* interrupts currently enabled */
 141
 142 #define SCC_WR0         0       /* reg select, and commands */
 143 #define SCC_WR1         1       /* interrupt and DMA enables */
 144 #define SCC_WR2         2       /* interrupt vector */
 145 #define SCC_WR3         3       /* receiver params and enables */
 146 #define SCC_WR4         4       /* clock/char/parity params */
 147 #define SCC_WR5         5       /* xmit params and enables */
 148 #define SCC_WR6         6       /* synchr SYNCH/address */
 149 #define SCC_WR7         7       /* synchr SYNCH/flag */
 150 #define SCC_WR8         8       /* xmit buffer (alias for data) */
 151 #define SCC_WR9         9       /* vectoring and resets */
 152 #define SCC_WR10        10      /* synchr params */
 153 #define SCC_WR11        11      /* clocking definitions */
 154 #define SCC_WR12        12      /* BRG constant, low part */
 155 #define SCC_WR13        13      /* BRG constant, high part */
 156 #define SCC_WR14        14      /* BRG enables and commands */
 157 #define SCC_WR15        15      /* interrupt enables */
 158
 159 /*
 160  * Read registers defines
 161  */
 162
 163 #define SCC_RR0_BREAK           0x80    /* break detected (rings twice), or */
 164 #define SCC_RR0_ABORT           0x80    /* abort (synchr) */
 165 #define SCC_RR0_TX_UNDERRUN     0x40    /* xmit buffer empty/end of message */
 166 #define SCC_RR0_CTS             0x20    /* clear-to-send pin active (sampled
 167                                            only on intr and after RESI cmd */
 168 #define SCC_RR0_SYNCH           0x10    /* SYNCH found/still hunting */
 169 #define SCC_RR0_DCD             0x08    /* carrier-detect (same as CTS) */
 170 #define SCC_RR0_TX_EMPTY        0x04    /* xmit buffer empty */
 171 #define SCC_RR0_ZERO_COUNT      0x02    /* ? */
 172 #define SCC_RR0_RX_AVAIL        0x01    /* recv fifo not empty */
 173
 174 #define SCC_RR1_EOF             0x80    /* end-of-frame, SDLC mode */
 175 #define SCC_RR1_CRC_ERR         0x40    /* incorrect CRC or.. */
 176 #define SCC_RR1_FRAME_ERR       0x40    /* ..bad frame */
 177 #define SCC_RR1_RX_OVERRUN      0x20    /* rcv fifo overflow */
 178 #define SCC_RR1_PARITY_ERR      0x10    /* incorrect parity in data */
 179 #define SCC_RR1_RESIDUE0        0x08
 180 #define SCC_RR1_RESIDUE1        0x04
 181 #define SCC_RR1_RESIDUE2        0x02
 182 #define SCC_RR1_ALL_SENT        0x01
 183
 184 /* RR2 contains the interrupt vector unmodified (channel A) or
 185    modified as follows (channel B, if vector-include-status) */
 186
 187 #define SCC_RR2_STATUS(val)     ((val)&0xe)     /* 11/7/95 used to be 0xf */
 188
 189 #define SCC_RR2_B_XMIT_DONE     0x0
 190 #define SCC_RR2_B_EXT_STATUS    0x2
 191 #define SCC_RR2_B_RECV_DONE     0x4
 192 #define SCC_RR2_B_RECV_SPECIAL  0x6
 193 #define SCC_RR2_A_XMIT_DONE     0x8
 194 #define SCC_RR2_A_EXT_STATUS    0xa
 195 #define SCC_RR2_A_RECV_DONE     0xc
 196 #define SCC_RR2_A_RECV_SPECIAL  0xe
 197
 198 /* Interrupts pending, to be read from channel A only (B raz) */
 199 #define SCC_RR3_zero            0xc0
 200 #define SCC_RR3_RX_IP_A         0x20
 201 #define SCC_RR3_TX_IP_A         0x10
 202 #define SCC_RR3_EXT_IP_A        0x08
 203 #define SCC_RR3_RX_IP_B         0x04
 204 #define SCC_RR3_TX_IP_B         0x02
 205 #define SCC_RR3_EXT_IP_B        0x01
 206
 207 /* RR8 is the receive data buffer, a 3 deep FIFO */
 208 #define SCC_RECV_BUFFER         SCC_RR8
 209 #define SCC_RECV_FIFO_DEEP      3
 210
 211 #define SCC_RR10_1CLKS          0x80
 212 #define SCC_RR10_2CLKS          0x40
 213 #define SCC_RR10_zero           0x2d
 214 #define SCC_RR10_LOOP_SND       0x10
 215 #define SCC_RR10_ON_LOOP        0x02
 216
 217 /* RR12/RR13 hold the timing base, upper byte in RR13 */
 218
 219 #define scc_get_timing_base(scc,chan,val)       { \
 220                 register char   tmp;    \
 221                 scc_read_reg(scc,chan,SCC_RR12,val);\
 222                 scc_read_reg(scc,chan,SCC_RR13,tmp);\
 223                 (val) = ((val)<<8)|(tmp&0xff);\
 224         }
 225
 226 #define SCC_RR15_BREAK_IE       0x80
 227 #define SCC_RR15_TX_UNDERRUN_IE 0x40
 228 #define SCC_RR15_CTS_IE         0x20
 229 #define SCC_RR15_SYNCH_IE       0x10
 230 #define SCC_RR15_DCD_IE         0x08
 231 #define SCC_RR15_zero           0x05
 232 #define SCC_RR15_ZERO_COUNT_IE  0x02
 233
 234
 235 /*
 236  * Write registers defines
 237  */
 238
 239 /* WR0 is used for commands too */
 240 #define SCC_RESET_TXURUN_LATCH  0xc0
 241 #define SCC_RESET_TX_CRC        0x80
 242 #define SCC_RESET_RX_CRC        0x40
 243 #define SCC_RESET_HIGHEST_IUS   0x38    /* channel A only */
 244 #define SCC_RESET_ERROR         0x30
 245 #define SCC_RESET_TX_IP         0x28
 246 #define SCC_IE_NEXT_CHAR        0x20
 247 #define SCC_SEND_SDLC_ABORT     0x18
 248 #define SCC_RESET_EXT_IP        0x10
 249
 250 #define SCC_WR1_DMA_ENABLE      0x80    /* dma control */
 251 #define SCC_WR1_DMA_MODE        0x40    /* drive ~req for DMA controller */
 252 #define SCC_WR1_DMA_RECV_DATA   0x20    /* from wire to host memory */
 253                                         /* interrupt enable/conditions */
 254 #define SCC_WR1_RXI_SPECIAL_O   0x18    /* on special only */
 255 #define SCC_WR1_RXI_ALL_CHAR    0x10    /* on each char, or special */
 256 #define SCC_WR1_RXI_FIRST_CHAR  0x08    /* on first char, or special */
 257 #define SCC_WR1_RXI_DISABLE     0x00    /* never on recv */
 258 #define SCC_WR1_PARITY_IE       0x04    /* on parity errors */
 259 #define SCC_WR1_TX_IE           0x02
 260 #define SCC_WR1_EXT_IE          0x01
 261
 262 /* WR2 is common and contains the interrupt vector (high nibble) */
 263
 264 #define SCC_WR3_RX_8_BITS       0xc0
 265 #define SCC_WR3_RX_6_BITS       0x80
 266 #define SCC_WR3_RX_7_BITS       0x40
 267 #define SCC_WR3_RX_5_BITS       0x00
 268 #define SCC_WR3_AUTO_ENABLE     0x20
 269 #define SCC_WR3_HUNT_MODE       0x10
 270 #define SCC_WR3_RX_CRC_ENABLE   0x08
 271 #define SCC_WR3_SDLC_SRCH       0x04
 272 #define SCC_WR3_INHIBIT_SYNCH   0x02
 273 #define SCC_WR3_RX_ENABLE       0x01
 274
 275 /* Should be re-written after reset */
 276 #define SCC_WR4_CLK_x64         0xc0    /* clock divide factor */
 277 #define SCC_WR4_CLK_x32         0x80
 278 #define SCC_WR4_CLK_x16         0x40
 279 #define SCC_WR4_CLK_x1          0x00
 280 #define SCC_WR4_EXT_SYNCH_MODE  0x30    /* synch modes */
 281 #define SCC_WR4_SDLC_MODE       0x20
 282 #define SCC_WR4_16BIT_SYNCH     0x10
 283 #define SCC_WR4_8BIT_SYNCH      0x00
 284 #define SCC_WR4_2_STOP          0x0c    /* asynch modes */
 285 #define SCC_WR4_1_5_STOP        0x08
 286 #define SCC_WR4_1_STOP          0x04
 287 #define SCC_WR4_SYNCH_MODE      0x00
 288 #define SCC_WR4_EVEN_PARITY     0x02
 289 #define SCC_WR4_PARITY_ENABLE   0x01
 290
 291 #define SCC_WR5_DTR             0x80    /* drive DTR pin */
 292 #define SCC_WR5_TX_8_BITS       0x60
 293 #define SCC_WR5_TX_6_BITS       0x40
 294 #define SCC_WR5_TX_7_BITS       0x20
 295 #define SCC_WR5_TX_5_BITS       0x00
 296 #define SCC_WR5_SEND_BREAK      0x10
 297 #define SCC_WR5_TX_ENABLE       0x08
 298 #define SCC_WR5_CRC_16          0x04    /* CRC if non zero, .. */
 299 #define SCC_WR5_SDLC            0x00    /* ..SDLC otherwise  */
 300 #define SCC_WR5_RTS             0x02    /* drive RTS pin */
 301 #define SCC_WR5_TX_CRC_ENABLE   0x01
 302
 303 /* Registers WR6 and WR7 are for synch modes data, with among other things: */
 304
 305 #define SCC_WR6_BISYNCH_12      0x0f
 306 #define SCC_WR6_SDLC_RANGE_MASK 0x0f
 307 #define SCC_WR7_SDLC_FLAG       0x7e
 308
 309 /* Register WR7' (prime) controls some ESCC features */
 310 #define SCC_WR7P_RX_FIFO        0x08    /* Enable interrupt on FIFO 1/2 full */
 311
 312 /* WR8 is the transmit data buffer (no FIFO) */
 313 #define SCC_XMT_BUFFER          SCC_WR8
 314
 315 #define SCC_WR9_HW_RESET        0xc0    /* force hardware reset */
 316 #define SCC_WR9_RESET_CHA_A     0x80
 317 #define SCC_WR9_RESET_CHA_B     0x40
 318 #define SCC_WR9_NON_VECTORED    0x20    /* mbz for Zilog chip */
 319 #define SCC_WR9_STATUS_HIGH     0x10
 320 #define SCC_WR9_MASTER_IE       0x08
 321 #define SCC_WR9_DLC             0x04    /* disable-lower-chain */
 322 #define SCC_WR9_NV              0x02    /* no vector */
 323 #define SCC_WR9_VIS             0x01    /* vector-includes-status */
 324
 325 #define SCC_WR10_CRC_PRESET     0x80
 326 #define SCC_WR10_FM0            0x60
 327 #define SCC_WR10_FM1            0x40
 328 #define SCC_WR10_NRZI           0x20
 329 #define SCC_WR10_NRZ            0x00
 330 #define SCC_WR10_ACTIVE_ON_POLL 0x10
 331 #define SCC_WR10_MARK_IDLE      0x08    /* flag if zero */
 332 #define SCC_WR10_ABORT_ON_URUN  0x04    /* flag if zero */
 333 #define SCC_WR10_LOOP_MODE      0x02
 334 #define SCC_WR10_6BIT_SYNCH     0x01
 335 #define SCC_WR10_8BIT_SYNCH     0x00
 336
 337 #define SCC_WR11_RTxC_XTAL      0x80    /* RTxC pin is input (ext oscill) */
 338 #define SCC_WR11_RCLK_DPLL      0x60    /* clock received data on dpll */
 339 #define SCC_WR11_RCLK_BAUDR     0x40    /* .. on BRG */
 340 #define SCC_WR11_RCLK_TRc_PIN   0x20    /* .. on TRxC pin */
 341 #define SCC_WR11_RCLK_RTc_PIN   0x00    /* .. on RTxC pin */
 342 #define SCC_WR11_XTLK_DPLL      0x18
 343 #define SCC_WR11_XTLK_BAUDR     0x10
 344 #define SCC_WR11_XTLK_TRc_PIN   0x08
 345 #define SCC_WR11_XTLK_RTc_PIN   0x00
 346 #define SCC_WR11_TRc_OUT        0x04    /* drive TRxC pin as output from..*/
 347 #define SCC_WR11_TRcOUT_DPLL    0x03    /* .. the dpll */
 348 #define SCC_WR11_TRcOUT_BAUDR   0x02    /* .. the BRG */
 349 #define SCC_WR11_TRcOUT_XMTCLK  0x01    /* .. the xmit clock */
 350 #define SCC_WR11_TRcOUT_XTAL    0x00    /* .. the external oscillator */
 351
 352 /* WR12/WR13 are for timing base preset */
 353 #define scc_set_timing_base(scc,chan,val)       { \
 354                 scc_write_reg(scc,chan,SCC_RR12,val);\
 355                 scc_write_reg(scc,chan,SCC_RR13,(val)>>8);\
 356         }
 357
 358 /* More commands in this register */
 359 #define SCC_WR14_NRZI_MODE      0xe0    /* synch modulations */
 360 #define SCC_WR14_FM_MODE        0xc0
 361 #define SCC_WR14_RTc_SOURCE     0xa0    /* clock is from pin .. */
 362 #define SCC_WR14_BAUDR_SOURCE   0x80    /* .. or internal BRG */
 363 #define SCC_WR14_DISABLE_DPLL   0x60
 364 #define SCC_WR14_RESET_CLKMISS  0x40
 365 #define SCC_WR14_SEARCH_MODE    0x20
 366 /* ..and more bitsy */
 367 #define SCC_WR14_LOCAL_LOOPB    0x10
 368 #define SCC_WR14_AUTO_ECHO      0x08
 369 #define SCC_WR14_DTR_REQUEST    0x04
 370 #define SCC_WR14_BAUDR_SRC      0x02
 371 #define SCC_WR14_BAUDR_ENABLE   0x01
 372
 373 #define SCC_WR15_BREAK_IE       0x80
 374 #define SCC_WR15_TX_UNDERRUN_IE 0x40
 375 #define SCC_WR15_CTS_IE         0x20
 376 #define SCC_WR15_SYNCHUNT_IE    0x10
 377 #define SCC_WR15_DCD_IE         0x08
 378 #define SCC_WR15_zero           0x05
 379 #define SCC_WR15_ZERO_COUNT_IE  0x02
 380 #define SCC_WR15_ENABLE_ESCC    0x01    /* Enable some ESCC registers */
 381
 382 #define NSCC_LINE               2       /* How many lines are support per 8530 */
 383 /*
 384  * Driver status
 385  */
 386
 387 #define SCC_FLAGS_DMA_PAUSED    0x00001         /* DMA has been paused because of XON/XOFF */
 388 #define SCC_FLAGS_DMA_TX_BUSY   0x00002         /* On going DMA operation.. */
 389
 390 struct scc_softreg {
 391         unsigned char   wr1;
 392         unsigned char   wr4;
 393         unsigned char   wr5;
 394         unsigned char   wr14;
 395
 396         unsigned long   speed;
 397         unsigned long   flags;
 398         unsigned long   dma_flags;
 399 };
 400
 401
 402 struct scc_softc {
 403         scc_regmap_t            regs;
 404         struct scc_dma_ops      *dma_ops;
 405
 406         /* software copy of some write regs, for reg |= */
 407         struct scc_softreg softr[NSCC_LINE];
 408
 409         int             flags;
 410         int             modem[NSCC_LINE]; /* Mach modem bits (TM_DTR etc). */
 411         int             dcd_timer[NSCC_LINE];
 412         int             dma_initted;
 413
 414         char            polling_mode;
 415         char            probed_once;
 416
 417         boolean_t               full_modem;
 418 };
 419
 420 #define DCD_TIMEOUT 4
 421
 422 typedef struct scc_softc *scc_softc_t;
 423 extern struct scc_softc         scc_softc[];
 424
 425 #endif  /*_SCC_8530_H_*/