iokit/Drivers/ata/drvApplePIIXATA/AppleATAPIIXRegs.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * The contents of this file constitute Original Code as defined in and
   7  * are subject to the Apple Public Source License Version 1.1 (the
   8  * "License").  You may not use this file except in compliance with the
   9  * License.  Please obtain a copy of the License at
  10  * http://www.apple.com/publicsource and read it before using this file.
  11  *
  12  * This Original Code and all software distributed under the License are
  13  * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  14  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  15  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT.  Please see the
  17  * License for the specific language governing rights and limitations
  18  * under the License.
  19  *
  20  * @APPLE_LICENSE_HEADER_END@
  21  */
  22 /*
  23  * Copyright (c) 2000 Apple Computer, Inc.  All rights reserved.
  24  *
  25  * Intel PIIX/PIIX3/PIIX4 PCI IDE controller.
  26  * PIIX = PCI-ISA-IDE-Xelerator. (also USB on newer controllers)
  27  *
  28  * Notes:
  29  *
  30  * PIIX  introduced in the "Triton" chipset.
  31  * PIIX3 supports different timings for Master/Slave devices on both channels.
  32  * PIIX4 adds support for Ultra DMA/33.
  33  *
  34  * Be sure to download and read the PIIX errata from Intel's web site at
  35  * developer.intel.com.
  36  *
  37  * HISTORY:
  38  *
  39  */
  40
  41 #ifndef _APPLEATAPIIXREGS_H
  42 #define _APPLEATAPIIXREGS_H
  43
  44 /*
  45  * PCI ID for supported PIIX variants.
  46  */
  47 #define PCI_ID_PIIX     0x12308086
  48 #define PCI_ID_PIIX3    0x70108086
  49 #define PCI_ID_PIIX4    0x71118086
  50 #define PCI_ID_ICH      0x24118086
  51 #define PCI_ID_ICH0     0x24218086
  52 #define PCI_ID_ICH2_M   0x244a8086
  53 #define PCI_ID_ICH2     0x244b8086
  54 #define PCI_ID_NONE     0xffffffff
  55
  56 /*
  57  * Decoded port addresses. Seems to be hardcoded and it does not
  58  * show up in the PCI configuration space memory ranges.
  59  */
  60 #define PIIX_P_CMD_ADDR     0x1f0
  61 #define PIIX_P_CTL_ADDR     0x3f4
  62 #define PIIX_S_CMD_ADDR     0x170
  63 #define PIIX_S_CTL_ADDR     0x374
  64 #define PIIX_CMD_SIZE       8
  65 #define PIIX_CTL_SIZE       4
  66
  67 /*
  68  * IRQ assignment.
  69  */
  70 #define PIIX_P_IRQ          14
  71 #define PIIX_S_IRQ          15
  72
  73 /*
  74  * PIIX has two IDE channels.
  75  */
  76 #define PIIX_CHANNEL_PRIMARY    0
  77 #define PIIX_CHANNEL_SECONDARY  1
  78
  79 /*
  80  * PIIX PCI config space registers.
  81  * Register size (bits) in parenthesis.
  82  */
  83 #define PIIX_PCI_CFID           0x00
  84
  85 #define PIIX_PCI_PCICMD         0x04    // (16) PCI command register
  86 #define PIIX_PCI_PCICMD_IOSE    0x01    // I/O space enable
  87 #define PIIX_PCI_PCICMD_BME     0x04    // bus-master enable
  88
  89 #define PIIX_PCI_PCISTS         0x06    // (16) PCI device status register
  90 #define PIIX_PCI_RID            0x08    // (8)  Revision ID register
  91 #define PIIX_PCI_CLASSC         0x09    // (24) Class code register
  92 #define PIIX_PCI_MLT            0x0d    // (8)  Master latency timer register
  93 #define PIIX_PCI_HEDT           0x0e    // (8)  Header type register
  94
  95 #define PIIX_PCI_BMIBA          0x20    // (32) Bus-Master base address
  96 #define PIIX_PCI_BMIBA_RTE      0x01    // resource type indicator (I/O)
  97 #define PIIX_PCI_BMIBA_MASK     0xfff0  // base address mask
  98
  99 #define PIIX_PCI_IDETIM         0x40    // (16) IDE timing registers (pri)
 100 #define PIIX_PCI_IDETIM_S       0x42    // (16) IDE timing registers (sec)
 101 #define PIIX_PCI_SIDETIM        0x44    // (8)  Slave IDE timing register
 102 #define PIIX_PCI_UDMACTL        0x48    // (8)  Ultra DMA/33 control register
 103 #define PIIX_PCI_UDMATIM        0x4a    // (16) Ultra DMA/33 timing register
 104
 105 #define PIIX_PCI_IDECONFIG      0x54    // (32) IDE I/O Config register
 106
 107 /*
 108  * PIIX PCI configuration space register definition.
 109  *
 110  * PIIX_IDETIM - IDE timing register.
 111  *
 112  * Address:
 113  * 0x40:0x41 - Primary channel
 114  * 0x42:0x43 - Secondary channel
 115  */
 116 #define PIIX_PCI_IDETIM_IDE           0x8000   // IDE decode enable
 117 #define PIIX_PCI_IDETIM_SITRE         0x4000   // slave timing register enable
 118
 119 #define PIIX_PCI_IDETIM_ISP_MASK      0x3000
 120 #define PIIX_PCI_IDETIM_ISP_SHIFT     12
 121 #define PIIX_PCI_IDETIM_ISP_5         0x0000   // IORDY sample point
 122 #define PIIX_PCI_IDETIM_ISP_4         0x1000   // (PCI clocks)
 123 #define PIIX_PCI_IDETIM_ISP_3         0x2000
 124 #define PIIX_PCI_IDETIM_ISP_2         0x3000
 125
 126 #define PIIX_PCI_IDETIM_RTC_MASK      0x0300
 127 #define PIIX_PCI_IDETIM_RTC_SHIFT     8
 128 #define PIIX_PCI_IDETIM_RTC_4         0x0000   // receovery time (PCI clocks)
 129 #define PIIX_PCI_IDETIM_RTC_3         0x0100
 130 #define PIIX_PCI_IDETIM_RTC_2         0x0200
 131 #define PIIX_PCI_IDETIM_RTC_1         0x0300
 132
 133 #define PIIX_PCI_IDETIM_DTE1          0x0080   // DMA timing enable only
 134 #define PIIX_PCI_IDETIM_PPE1          0x0040   // prefetch and posting enabled
 135 #define PIIX_PCI_IDETIM_IE1           0x0020   // IORDY sample point enable
 136 #define PIIX_PCI_IDETIM_TIME1         0x0010   // fast timing enable
 137 #define PIIX_PCI_IDETIM_DTE0          0x0008   // same as above for drive 0
 138 #define PIIX_PCI_IDETIM_PPE0          0x0004
 139 #define PIIX_PCI_IDETIM_IE0           0x0002
 140 #define PIIX_PCI_IDETIM_TIME0         0x0001
 141
 142 /*
 143  * PIIX PCI configuration space register definition.
 144  *
 145  * PIIX_SIDETIM - Slave IDE timing register.
 146  *
 147  * Address: 0x44
 148  */
 149 #define PIIX_PCI_SIDETIM_SISP1_MASK   0xc0
 150 #define PIIX_PCI_SIDETIM_SISP1_SHIFT  6
 151 #define PIIX_PCI_SIDETIM_SRTC1_MASK   0x30
 152 #define PIIX_PCI_SIDETIM_SRTC1_SHIFT  4
 153 #define PIIX_PCI_SIDETIM_PISP1_MASK   0x0c
 154 #define PIIX_PCI_SIDETIM_PISP1_SHIFT  2
 155 #define PIIX_PCI_SIDETIM_PRTC1_MASK   0x03
 156 #define PIIX_PCI_SIDETIM_PRTC1_SHIFT  0
 157
 158 /*
 159  * PIIX PCI configuration space register definition.
 160  *
 161  * PIIX_UDMACTL - Ultra DMA/33 control register
 162  *
 163  * Address: 0x48
 164  */
 165 #define PIIX_PCI_UDMACTL_SSDE1        0x08    // Enable UDMA/33 Sec/Drive1
 166 #define PIIX_PCI_UDMACTL_SSDE0        0x04    // Enable UDMA/33 Sec/Drive0
 167 #define PIIX_PCI_UDMACTL_PSDE1        0x02    // Enable UDMA/33 Pri/Drive1
 168 #define PIIX_PCI_UDMACTL_PSDE0        0x01    // Enable UDMA/33 Pri/Drive0
 169
 170 /*
 171  * PIIX PCI configuration space register definition.
 172  *
 173  * PIIX_UDMATIM - Ultra DMA/33 timing register
 174  *
 175  * Address: 0x4a-0x4b
 176  */
 177 #define PIIX_PCI_UDMATIM_PCT0_MASK    0x0003
 178 #define PIIX_PCI_UDMATIM_PCT0_SHIFT   0
 179 #define PIIX_PCI_UDMATIM_PCT1_MASK    0x0030
 180 #define PIIX_PCI_UDMATIM_PCT1_SHIFT   4
 181 #define PIIX_PCI_UDMATIM_SCT0_MASK    0x0300
 182 #define PIIX_PCI_UDMATIM_SCT0_SHIFT   8
 183 #define PIIX_PCI_UDMATIM_SCT1_MASK    0x3000
 184 #define PIIX_PCI_UDMATIM_SCT1_SHIFT   12
 185
 186
 187 /*
 188  * PIIX IO space register offsets. Base address is set in PIIX_PCI_BMIBA.
 189  * Register size (bits) in parenthesis.
 190  *
 191  * Note:
 192  * For the primary channel, the base address is stored in PIIX_PCI_BMIBA.
 193  * For the secondary channel, an offset (PIIX_IO_BM_OFFSET) is added to
 194  * the value stored in PIIX_PCI_BMIBA.
 195  */
 196 #define PIIX_IO_BMICX            0x00    // (8) Bus master command register
 197 #define PIIX_IO_BMISX            0x02    // (8) Bus master status register
 198 #define PIIX_IO_BMIDTPX          0x04    // (32) Descriptor table register
 199
 200 #define PIIX_IO_BM_OFFSET        0x08    // offset to sec channel registers
 201 #define PIIX_IO_BM_SIZE          0x08    // BM registers size for each channel
 202 #define PIIX_IO_BM_MASK          0xfff0  // BMIBA mask to get I/O base address
 203
 204 /*
 205  * PIIX IO space register definition.
 206  *
 207  * BMICX - Bus master IDE command register
 208  */
 209 #define PIIX_IO_BMICX_SSBM       0x01    // 1=Start, 0=Stop
 210 #define PIIX_IO_BMICX_RWCON      0x08    // 0=Read, 1=Write
 211
 212 /*
 213  * PIIX IO space register definition.
 214  *
 215  * PIIX_BMISX - Bus master IDE status register
 216  */
 217 #define PIIX_IO_BMISX_DMA1CAP    0x40    // drive 1 is capable of DMA transfers
 218 #define PIIX_IO_BMISX_DMA0CAP    0x20    // drive 0 is capable of DMA transfers
 219 #define PIIX_IO_BMISX_IDEINTS    0x04    // IDE device asserted its interrupt
 220 #define PIIX_IO_BMISX_ERROR      0x02    // DMA error (cleared by writing a 1)
 221 #define PIIX_IO_BMISX_BMIDEA     0x01    // bus master active bit
 222
 223 #define PIIX_IO_BMISX_STATUS    (PIIX_IO_BMISX_IDEINTS | \
 224                                  PIIX_IO_BMISX_ERROR   | \
 225                                  PIIX_IO_BMISX_BMIDEA)
 226
 227 /*
 228  * PIIX Bus Master alignment/boundary requirements.
 229  *
 230  * Intel nomemclature:
 231  * WORD  - 16-bit
 232  * DWord - 32-bit
 233  */
 234 #define PIIX_DT_ALIGN    4           // descriptor table must be DWord aligned.
 235 #define PIIX_DT_BOUND    (4 * 1024)  // cannot cross 4K boundary. (or 64K ?)
 236
 237 #define PIIX_BUF_ALIGN   2           // memory buffer must be word aligned.
 238 #define PIIX_BUF_BOUND   (64 * 1024) // cannot cross 64K boundary.
 239 #define PIIX_BUF_LIMIT   (64 * 1024) // limited to 64K in size
 240
 241 /*
 242  * PIIX Bus Master Physical Region Descriptor (PRD).
 243  */
 244 typedef struct {
 245     UInt32  base;      // base address
 246     UInt16  count;     // byte count
 247     UInt16  flags;     // flag bits
 248 } prdEntry_t;
 249
 250 #define PRD_FLAG_EOT          0x8000
 251
 252 #define PRD_COUNT(x)          (((x) == PIIX_BUF_LIMIT) ? 0 : (x))
 253 #define PRD_TABLE_SIZE        PAGE_SIZE
 254 #define PRD_ENTRIES           (PRD_TABLE_SIZE / sizeof(prdEntry_t))
 255
 256 /*
 257  * PIIX Register setting macro.
 258  */
 259 #define SET_REG_FIELD(reg, field, val)     \
 260 {                                          \
 261     reg &= ~(field ## _MASK);              \
 262     reg |= (((val) << field ## _SHIFT) &   \
 263                     field ## _MASK);       \
 264 }
 265
 266 /*
 267  * Convert the "isp" and "rtc" fields in PIIX_IDETIM register from
 268  * PCI clocks to their respective values, and vice-versa.
 269  */
 270 #define PIIX_CLK_TO_ISP(x)    (5 - (x))
 271 #define PIIX_ISP_TO_CLK(x)    PIIX_CLK_TO_ISP(x)
 272 #define PIIX_CLK_TO_RTC(x)    (4 - (x))
 273 #define PIIX_RTC_TO_CLK(x)    PIIX_CLK_TO_RTC(x)
 274
 275 #endif /* !_APPLEATAPIIXREGS_H */