osfmk/ppc/hw_perfmon_mmcr.h

   1 /*
   2  * Copyright (c) 2002 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #ifndef _HW_PERFMON_MMCR_H_
  30 #define _HW_PERFMON_MMCR_H_
  31
  32 #ifndef __ppc__
  33 #error This file is only useful on PowerPC.
  34 #endif
  35
  36 typedef struct {
  37         uint32_t disable_counters_always : 1;     /*     0: disable counters */
  38         uint32_t disable_counters_supervisor : 1; /*     1: disable counters (supervisor) */
  39         uint32_t disable_counters_user : 1;       /*     2: disable counters (user) */
  40         uint32_t disable_counters_marked : 1;     /*     3: disable counters (marked bit == 1) */
  41         uint32_t disable_counters_unmarked : 1;   /*     4: disable counters (marked bit == 0) */
  42         uint32_t enable_pmi : 1;                  /*     5: performance monitor interrupt enable */
  43         uint32_t on_pmi_stop_counting : 1;        /*     6: disable counters (pmi) */
  44         uint32_t timebase_bit_selector : 2;       /*   7-8: TBL bit for TB events */
  45         uint32_t enable_timebase_pmi : 1;         /*     9: enable pmi on TBL bit transition */
  46         uint32_t threshold_value : 6;             /* 10-15: threshold value */
  47         uint32_t enable_pmi_on_pmc1 : 1;          /*    16: enable pmi on pmc1 overflow */
  48         uint32_t enable_pmi_on_pmcn : 1;          /*    17: enable pmi on any pmc except pmc1 overflow */
  49         uint32_t enable_pmi_trigger : 1;          /*    18: enable triggering of pmcn by pmc1 overflow */
  50         uint32_t pmc1_event : 7;                  /* 19-25: pmc1 event select */
  51         uint32_t pmc2_event : 6;                  /* 26-31: pmc2 event select */
  52 } ppc32_mmcr0_bits_t;
  53
  54 typedef union {
  55         uint32_t value;
  56         ppc32_mmcr0_bits_t field;
  57 } ppc32_mmcr0_reg_t;
  58
  59 typedef struct {
  60         uint32_t pmc3_event : 5;
  61         uint32_t pmc4_event : 5;
  62         uint32_t pmc5_event : 5;
  63         uint32_t pmc6_event : 6;
  64         uint32_t /*reserved*/ : 11;
  65 } ppc32_mmcr1_bits_t;
  66
  67 typedef union {
  68         uint32_t value;
  69         ppc32_mmcr1_bits_t field;
  70 } ppc32_mmcr1_reg_t;
  71
  72 typedef struct {
  73         uint32_t threshold_multiplier : 1;
  74         uint32_t /*reserved*/ : 31;
  75 } ppc32_mmcr2_bits_t;
  76
  77 typedef union {
  78         uint32_t value;
  79         ppc32_mmcr2_bits_t field;
  80 } ppc32_mmcr2_reg_t;
  81
  82 typedef struct {
  83         uint32_t /* reserved */ : 32;             /*  0-31: reserved */
  84         uint32_t disable_counters_always : 1;     /*    32: disable counters */
  85         uint32_t disable_counters_supervisor : 1; /*    33: disable counters (supervisor) */
  86         uint32_t disable_counters_user : 1;       /*    34: disable counters (user) */
  87         uint32_t disable_counters_marked : 1;     /*    35: disable counters (marked bit == 1) */
  88         uint32_t disable_counters_unmarked : 1;   /*    36: disable counters (marked bit == 0) */
  89         uint32_t enable_pmi : 1;                  /*    37: performance monitor interrupt enable */
  90         uint32_t on_pmi_stop_counting : 1;        /*    38: disable counters (pmi) */
  91         uint32_t timebase_bit_selector : 2;       /* 39-40: TBL bit for timebase events */
  92         uint32_t enable_timebase_pmi : 1;         /*    41: enable pmi on TBL bit transition */
  93         uint32_t threshold_value : 6;             /* 42-47: threshold value */
  94         uint32_t enable_pmi_on_pmc1 : 1;          /*    48: enable pmi on pmc1 overflow */
  95         uint32_t enable_pmi_on_pmcn : 1;          /*    49: enable pmi on any pmc except pmc1 overflow */
  96         uint32_t enable_pmi_trigger : 1;          /*    50: enable triggering of pmcn by pmc1 overflow */
  97         uint32_t pmc1_event : 5;                  /* 51-55: pmc1 event select */
  98         uint32_t perfmon_event_occurred : 1;      /*    56: performance monitor event has occurred */
  99         uint32_t /* reserved */ : 1;              /*    57: reserved */
 100         uint32_t pmc2_event : 5;                  /* 58-62: pmc2 event select */
 101         uint32_t disable_counters_hypervisor : 1; /*    63: disable counters (hypervisor) */
 102 } ppc64_mmcr0_bits_t;
 103
 104 typedef union {
 105         uint64_t value;
 106         ppc64_mmcr0_bits_t field;
 107 } ppc64_mmcr0_reg_t;
 108
 109 typedef struct {
 110         uint32_t ttm0_select : 2;                 /*   0-1: FPU/ISU/IFU/VMX unit select */
 111         uint32_t /* reserved */ : 1;              /*     2: reserved */
 112         uint32_t ttm1_select : 2;                 /*   3-4: IDU/ISU/ISU unit select */
 113         uint32_t /* reserved */ : 1;              /*     5: reserved */
 114         uint32_t ttm2_select : 2;                 /*   6-7: IFU/LSU0 unit select */
 115         uint32_t /* reserved */ : 1;              /*     8: reserved */
 116         uint32_t ttm3_select : 2;                 /*  9-10: LSU1 select */
 117         uint32_t /* reserved */ : 1;              /*    11: reserved */
 118         uint32_t lane0_select : 2;                /* 12-13: Byte lane 0 unit select (TD_CP_DBG0SEL) */
 119         uint32_t lane1_select : 2;                /* 14-15: Byte lane 1 unit select (TD_CP_DBG1SEL) */
 120         uint32_t lane2_select : 2;                /* 16-17: Byte lane 2 unit select (TD_CP_DBG2SEL) */
 121         uint32_t lane3_select : 2;                /* 18-19: Byte lane 3 unit select (TD_CP_DBG3SEL) */
 122         uint32_t /* reserved */ : 4;              /* 20-23: reserved */
 123         uint32_t pmc1_adder_lane_select : 1;      /*    24: PMC1 Event Adder Lane Select (PMC1_ADDER_SELECT) */
 124         uint32_t pmc2_adder_lane_select : 1;      /*    25: PMC2 Event Adder Lane Select (PMC2_ADDER_SELECT) */
 125         uint32_t pmc6_adder_lane_select : 1;      /*    26: PMC6 Event Adder Lane Select (PMC6_ADDER_SELECT) */
 126         uint32_t pmc5_adder_lane_select : 1;      /*    27: PMC5 Event Adder Lane Select (PMC5_ADDER_SELECT) */
 127         uint32_t pmc8_adder_lane_select : 1;      /*    28: PMC8 Event Adder Lane Select (PMC8_ADDER_SELECT) */
 128         uint32_t pmc7_adder_lane_select : 1;      /*    29: PMC7 Event Adder Lane Select (PMC7_ADDER_SELECT) */
 129         uint32_t pmc3_adder_lane_select : 1;      /*    30: PMC3 Event Adder Lane Select (PMC3_ADDER_SELECT) */
 130         uint32_t pmc4_adder_lane_select : 1;      /*    31: PMC4 Event Adder Lane Select (PMC4_ADDER_SELECT) */
 131         uint32_t pmc3_event : 5;                  /* 32-36: pmc3 event select */
 132         uint32_t pmc4_event : 5;                  /* 37-41: pmc4 event select */
 133         uint32_t pmc5_event : 5;                  /* 42-46: pmc5 event select */
 134         uint32_t pmc6_event : 5;                  /* 47-51: pmc6 event select */
 135         uint32_t pmc7_event : 5;                  /* 52-56: pmc7 event select */
 136         uint32_t pmc8_event : 5;                  /* 57-61: pmc8 event select */
 137         uint32_t speculative_event : 2;           /* 62-63: SPeCulative count event SELector */
 138 } ppc64_mmcr1_bits_t;
 139
 140 typedef union {
 141         uint64_t value;
 142         ppc64_mmcr1_bits_t field;
 143 } ppc64_mmcr1_reg_t;
 144
 145 typedef struct {
 146         uint32_t /* reserved */ : 32;             /*  0-31: reserved */
 147         uint32_t siar_sdar_same_instruction : 1;  /*    32: SIAR and SDAR are from same instruction */
 148         uint32_t disable_counters_pmc1_pmc4 : 1;  /*    33: disable counters PMC1-PMC4 */
 149         uint32_t disable_counters_pmc5_pmc8 : 1;  /*    34: disable counters PMC5-PMC8 */
 150         uint32_t problem_state_siar : 1;          /*    35: MSR[PR] bit when SIAR set */
 151         uint32_t hypervisor_state_siar : 1;       /*    36: MSR[HV] bit when SIAR set */
 152         uint32_t /* reserved */ : 3;              /* 37-39: reserved */
 153         uint32_t threshold_start_event : 3;       /* 40-42: threshold start event */
 154         uint32_t threshold_end_event : 3;         /* 43-45: threshold end event */
 155         uint32_t /* reserved */ : 3;              /* 46-48: reserved */
 156         uint32_t imr_select : 1;                  /*    49: imr select */
 157         uint32_t imr_mark : 2;                    /* 50-51: imr mark */
 158         uint32_t imr_mask : 4;                    /* 52-55: imr mask */
 159         uint32_t imr_match : 4;                   /* 56-59: imr match */
 160         uint32_t disable_counters_tags_inactive : 1; /* 60: disable counters in tags inactive mode */
 161         uint32_t disable_counters_tags_active : 1; /*   61: disable counters in tags active mode */
 162         uint32_t disable_counters_wait_state : 1; /*    62: freeze counters in wait state (CNTL[31]=0) */
 163         uint32_t sample_enable : 1;               /*    63: sampling enabled */
 164 } ppc64_mmcra_bits_t;
 165
 166 typedef union {
 167         uint64_t value;
 168         ppc64_mmcra_bits_t field;
 169 } ppc64_mmcra_reg_t;
 170
 171 /* PPC_PERFMON_FUNC_* values are taken apart to fill in the appropriate configuration bitfields: */
 172 typedef struct {
 173         uint32_t /* reserved */ : 22;
 174         uint32_t SPECSEL : 2;
 175         uint32_t TD_CP_DBGxSEL : 2;
 176         uint32_t TTM3SEL : 2;
 177         uint32_t TTM1SEL : 2;
 178         uint32_t TTM0SEL : 2;
 179 } ppc_func_bits_t;
 180
 181 typedef union {
 182         uint32_t value;
 183         ppc_func_bits_t field;
 184 } ppc_func_unit_t;
 185
 186 #endif /* _HW_PERFMON_MMCR_H_ */