osfmk/i386/cpuid.h

   1 /*
   2  * Copyright (c) 2000-2005 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. Please obtain a copy of the License at
  10  * http://www.opensource.apple.com/apsl/ and read it before using this
  11  * file.
  12  *
  13  * The Original Code and all software distributed under the License are
  14  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  15  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  16  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  18  * Please see the License for the specific language governing rights and
  19  * limitations under the License.
  20  *
  21  * @APPLE_LICENSE_HEADER_END@
  22  */
  23 /*
  24  * @OSF_COPYRIGHT@
  25  */
  26
  27 /*
  28  * x86 CPU identification
  29  *
  30  */
  31
  32 #ifndef _MACHINE_CPUID_H_
  33 #define _MACHINE_CPUID_H_
  34
  35 #include <sys/appleapiopts.h>
  36
  37 #ifdef __APPLE_API_PRIVATE
  38
  39 #define CPUID_VID_SIZE          12
  40 #define CPUID_VID_INTEL         "GenuineIntel"
  41 #define CPUID_VID_UMC           "UMC UMC UMC "
  42 #define CPUID_VID_AMD           "AuthenticAMD"
  43 #define CPUID_VID_CYRIX         "CyrixInstead"
  44 #define CPUID_VID_NEXGEN        "NexGenDriven"
  45 #define CPUID_VID_CENTAUR       "CentaurHauls"
  46 #define CPUID_VID_RISE          "RiseRiseRise"
  47 #define CPUID_VID_SIS           "SiS SiS SiS "
  48 #define CPUID_VID_TRANSMETA     "GenuineTMx86"
  49 #define CPUID_VID_NSC           "Geode by NSC"
  50
  51 #define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"
  52
  53 #define CPUID_FEATURE_FPU    0x00000001 /* Floating point unit on-chip */
  54 #define CPUID_FEATURE_VME    0x00000002 /* Virtual Mode Extension */
  55 #define CPUID_FEATURE_DE     0x00000004 /* Debugging Extension */
  56 #define CPUID_FEATURE_PSE    0x00000008 /* Page Size Extension */
  57 #define CPUID_FEATURE_TSC    0x00000010 /* Time Stamp Counter */
  58 #define CPUID_FEATURE_MSR    0x00000020 /* Model Specific Registers */
  59 #define CPUID_FEATURE_PAE    0x00000040 /* Physical Address Extension */
  60 #define CPUID_FEATURE_MCE    0x00000080 /* Machine Check Exception */
  61 #define CPUID_FEATURE_CX8    0x00000100 /* CMPXCHG8B */
  62 #define CPUID_FEATURE_APIC   0x00000200 /* On-chip APIC */
  63 #define CPUID_FEATURE_SEP    0x00000800 /* Fast System Call */
  64 #define CPUID_FEATURE_MTRR   0x00001000 /* Memory Type Range Register */
  65 #define CPUID_FEATURE_PGE    0x00002000 /* Page Global Enable */
  66 #define CPUID_FEATURE_MCA    0x00004000 /* Machine Check Architecture */
  67 #define CPUID_FEATURE_CMOV   0x00008000 /* Conditional Move Instruction */
  68 #define CPUID_FEATURE_PAT    0x00010000 /* Page Attribute Table */
  69 #define CPUID_FEATURE_PSE36  0x00020000 /* 36-bit Page Size Extension */
  70 #define CPUID_FEATURE_PSN    0x00040000 /* Processor Serial Number */
  71 #define CPUID_FEATURE_CLFSH  0x00080000 /* CLFLUSH Instruction supported */
  72 #define CPUID_FEATURE_DS     0x00200000 /* Debug Store */
  73 #define CPUID_FEATURE_ACPI   0x00400000 /* Thermal Monitor, SW-controlled clock */
  74 #define CPUID_FEATURE_MMX    0x00800000 /* MMX supported */
  75 #define CPUID_FEATURE_FXSR   0x01000000 /* Fast floating point save/restore */
  76 #define CPUID_FEATURE_SSE    0x02000000 /* Streaming SIMD extensions */
  77 #define CPUID_FEATURE_SSE2   0x04000000 /* Streaming SIMD extensions 2 */
  78 #define CPUID_FEATURE_SS     0x08000000 /* Self-Snoop */
  79 #define CPUID_FEATURE_HTT    0x10000000 /* Hyper-Threading Technology */
  80 #define CPUID_FEATURE_TM     0x20000000 /* Thermal Monitor */
  81
  82 #define CPUID_TYPE_OEM              0x0 /* Original processor */
  83 #define CPUID_TYPE_OVERDRIVE        0x1 /* Overdrive processor */
  84 #define CPUID_TYPE_DUAL             0x2 /* Can be used as dual processor */
  85 #define CPUID_TYPE_RESERVED         0x3 /* Reserved */
  86
  87 #define CPUID_FAMILY_386            0x3 /* Intel 386 (not part of CPUID) */
  88
  89 #define CPUID_MODEL_I386_DX         0x0 /* Intel 386 (not part of CPUID) */
  90
  91 #define CPUID_FAMILY_486            0x4 /* Intel 486 */
  92
  93 #define CPUID_MODEL_I486_DX         0x0 /* Intel 486DX */
  94 #define CPUID_MODEL_I486_DX_S       0x1 /* Intel 486DX-S */
  95 #define CPUID_MODEL_I486_SX         0x2 /* Intel 486SX */
  96 #define CPUID_MODEL_I486_DX2        0x3 /* Intel 486DX2 */
  97 #define CPUID_MODEL_I486_SL         0x4 /* Intel 486SL */
  98 #define CPUID_MODEL_I486_SX2        0x5 /* Intel 486SX2 */
  99 #define CPUID_MODEL_I486_DX2WB      0x7 /* Intel 486DX2WB */
 100 #define CPUID_MODEL_I486_DX4        0x8 /* Intel 486DX4 */
 101 #define CPUID_MODEL_I486_DX4WB      0x9 /* Intel 486DX4WB */
 102
 103 #define CPUID_MODEL_AM486_DX        0x1 /* AMD 486DX */
 104 #define CPUID_MODEL_AM486_DX2       0x3 /* AMD 486DX2 */
 105 #define CPUID_MODEL_AM486_DX2WB     0x7 /* AMD 486DX2WB */
 106 #define CPUID_MODEL_AM486_DX4       0x8 /* AMD 486DX4 */
 107 #define CPUID_MODEL_AM486_DX4WB     0x9 /* AMD 486DX4WB */
 108 #define CPUID_MODEL_AM486_5X86      0xE /* AMD 5x86 */
 109 #define CPUID_MODEL_AM486_5X86WB    0xF /* AMD 5x86WB */
 110
 111 #define CPUID_MODEL_MEDIAGX         0x4 /* Cyrix MediaGX */
 112 #define CPUID_MODEL_CYRIX5X86       0x9 /* CYRIX 5X86 */
 113
 114 #define CPUID_FAMILY_586            0x5 /* Intel Pentium, AMD K5/K6*/
 115
 116 #define CPUID_MODEL_UMC5D           0x1 /* UMC U5D */
 117 #define CPUID_MODEL_UMC5S           0x2 /* UMC U5S */
 118 #define CPUID_MODEL_UMC486_DX2      0x3 /* UMC U486_DX2 */
 119 #define CPUID_MODEL_UMC486_SX2      0x5 /* UMC U486_SX2 */
 120
 121 #define CPUID_MODEL_P5A             0x0 /* Intel P5 60/66 Step A */
 122 #define CPUID_MODEL_P5              0x1 /* Intel P5 60/66 */
 123 #define CPUID_MODEL_P54             0x2 /* Intel P5 75/80/100/120/133/166 */
 124 #define CPUID_MODEL_P24T            0x3 /* Intel P5 Overdrive 63/83 */
 125
 126 #define CPUID_MODEL_K5M0            0x0 /* AMD-K5 Model 0 */
 127 #define CPUID_MODEL_K5M1            0x1 /* AMD-K5 Model 1 */
 128 #define CPUID_MODEL_K5M2            0x2 /* AMD-K5 Model 2 */
 129 #define CPUID_MODEL_K5M3            0x3 /* AMD-K5 Model 3 */
 130 #define CPUID_MODEL_K6M6            0x6 /* AMD-K6 Model 6 */
 131 #define CPUID_MODEL_K6M7            0x7 /* AMD-K6 Model 7 */
 132 #define CPUID_MODEL_K6_2            0x8 /* AMD-K6-2 Model 8 */
 133 #define CPUID_MODEL_K6_III          0x9 /* AMD-K6-III Model 9 */
 134
 135 #define CPUID_MODEL_CYRIX_M1              0x2 /* Cyrix M1 */
 136 #define CPUID_MODEL_MEDIAGX_MMX           0x4 /* Cyrix MediaGX MMX Enhanced */
 137
 138 #define CPUID_FAMILY_686            0x6 /* Intel Pentium Pro, II, III; AMD Athlon */
 139
 140 #define CPUID_MODEL_P6              0x1 /* Intel P6 */
 141 #define CPUID_MODEL_PII             0x3 /* Intel PII */
 142 #define CPUID_MODEL_P65             0x5 /* Intel PII/Xeon/Celeron model 5 */
 143 #define CPUID_MODEL_P66             0x6 /* Intel Celeron model 6 */
 144 #define CPUID_MODEL_P67             0x7 /* Intel PIII/Xeon model 7 */
 145 #define CPUID_MODEL_P68             0x8 /* Intel PIII/Xeon/Celeron model 8 */
 146 #define CPUID_MODEL_PM9             0x9 /* Intel Pentium M model 9 */
 147 #define CPUID_MODEL_P6A             0xA /* Intel PIII Xeon model A */
 148 #define CPUID_MODEL_P6B             0xB /* Intel PIII model B */
 149 #define CPUID_MODEL_PMD             0xD /* Intel Pentium M model D */
 150
 151 #define CPUID_MODEL_ATHLON_M1       0x1 /* AMD Athlon Model 1 */
 152 #define CPUID_MODEL_ATHLON_M2       0x2 /* AMD Athlon Model 2 */
 153 #define CPUID_MODEL_DURON_M3        0x3 /* AMD Duron Model 3 */
 154 #define CPUID_MODEL_ATHLON_M4       0x4 /* AMD Athlon Model 4 */
 155 #define CPUID_MODEL_ATHLON_M6       0x6 /* (Mobile) AMD Athlon/Duron MP/XP/4 Model 6 */
 156 #define CPUID_MODEL_DURON_M7        0x7 /* (Mobile) AMD Duron Model 7 */
 157 #define CPUID_MODEL_ATHLON_M8       0x8 /* (Mobile) Athlon XP/MP/XP-M Model 8 */
 158 #define CPUID_MODEL_ATHLON_M10      0xA /* (Mobile) AMD Athlon XP/MP/XP-M/XP-M(LV) Model 10 */
 159
 160 #define CPUID_MODEL_CYRIX_M2        0x0 /* Cyrix M2 */
 161 #define CPUID_MODEL_CYRIX_MII       0x2 /* VIA Cyrix MII (6x86MX) */
 162 #define CPUID_MODEL_VIA_CYRIX_M2    0x5 /* VIA C3 Cyrix M2 */
 163 #define CPUID_MODEL_WINCHIP_C5A     0x6 /* VIA C3 WinChip C5A */
 164 #define CPUID_MODEL_WINCHIP_C5BC    0x7 /* VIA C3 WinChip C5B/C5C */
 165 #define CPUID_MODEL_WINCHIP_C5N     0x8 /* VIA C3 WinChip C5N */
 166 #define CPUID_MODEL_WINCHIP_C5XLP   0x9 /* VIA C3 WinChip C5P */
 167
 168 #define CPUID_MODEL_NX586           0x0 /* NexGen Nx586 */
 169
 170 #define CPUID_MODEL_RISE_MP6_0      0x0 /* Rise mP6 */
 171 #define CPUID_MODEL_RISE_MP6_2      0x2 /* Rise mP6 */
 172
 173 #define CPUID_MODEL_SIS_55X         0x0 /* SIS 55x */
 174
 175 #define CPUID_MODEL_TM_CRUSOE       0x4 /* Transmeta Crusoe TM3x00 and TM5x00 */
 176
 177 #define CPUID_MODEL_CENTAUR_C6            0x4 /* Centaur C6 */
 178 #define CPUID_MODEL_CENTAUR_C2            0x8 /* Centaur C2 */
 179 #define CPUID_MODEL_CENTAUR_C3            0x9 /* Centaur C3 */
 180
 181 #define CPUID_MODEL_GX1               0x4 /* AMD Geode GX1 */
 182 #define CPUID_MODEL_GX2               0x5 /* AMD Geode GX */
 183
 184 #define CPUID_FAMILY_ITANIUM        0x7 /* Intel Intanium */
 185 #define CPUID_FAMILY_EXTENDED       0xF /* Intel Pentium 4, Itanium II */
 186
 187 #define CPUID_EXTFAMILY_PENTIUM4    0x0 /* Intel Pentium 4 */
 188 #define CPUID_EXTFAMILY_ITANIUM2    0x1 /* Intel Itanium 2 */
 189
 190 #define CPUID_MODEL_ATHLON64        0x4 /* AMD Athlon 64 Model 4 */
 191 #define CPUID_MODEL_OPTERON         0x5 /* AMD Opteron Model 4 */
 192
 193 #define CPUID_BRAND_UNSUPPORTED     0x00
 194 #define CPUID_BRAND_CELERON_1       0x01 /* Intel Celeron */
 195 #define CPUID_BRAND_PENTIUM_III_2   0x02 /* Intel Pentium III */
 196 #define CPUID_BRAND_PIII_XEON       0x03 /* Intel Pentium III Xeon / Celeron */
 197 #define CPUID_BRAND_PENTIUM_III_4   0x04 /* Intel Pentium III */
 198 #define CPUID_BRAND_PENTIUM_III_M   0x05 /* Mobile Intel Pentium III-M */
 199 #define CPUID_BRAND_M_CELERON_7     0x07 /* Mobile Intel Celeron */
 200 #define CPUID_BRAND_PENTIUM4_8      0x08 /* Intel Pentium 4 */
 201 #define CPUID_BRAND_PENTIUM4_9      0x09 /* Intel Pentium 4 */
 202 #define CPUID_BRAND_CELERON_A       0x0A /* Intel Celeron */
 203 #define CPUID_BRAND_XEON            0x0B /* Intel Xeon (MP) */
 204 #define CPUID_BRAND_XEON_MP         0x0C /* Intel Xeon MP */
 205 #define CPUID_BRAND_PENTIUM4_M      0x0E /* Mobile Intel Pentium 4-M / Xeon */
 206 #define CPUID_BRAND_M_CELERON_F     0x0F /* Mobile Intel Celeron */
 207 #define CPUID_BRAND_MOBILE_17       0x11 /* Mobile Genuine Intel */
 208 #define CPUID_BRAND_CELERON_M       0x12 /* Intel Celeron M */
 209 #define CPUID_BRAND_M_CELERON_13    0x13 /* Mobile Intel Celeron */
 210 #define CPUID_BRAND_CELERON_14      0x14 /* Intel Celeron */
 211 #define CPUID_BRAND_MOBILE_15       0x15 /* Mobile Genuine Intel */
 212 #define CPUID_BRAND_PENTIUM_M       0x16 /* Intel Pentium M */
 213 #define CPUID_BRAND_M_CELERON_17    0x17 /* Mobile Intel Celeron */
 214
 215 #define CPUID_CACHE_SIZE        16      /* Number of descriptor vales */
 216
 217 #define CPUID_CACHE_NULL           0x00 /* NULL */
 218 #define CPUID_CACHE_ITLB_4K        0x01 /* Instruction TLB, 4K pages */
 219 #define CPUID_CACHE_ITLB_4M        0x02 /* Instruction TLB, 4M pages */
 220 #define CPUID_CACHE_DTLB_4K        0x03 /* Data TLB, 4K pages */
 221 #define CPUID_CACHE_DTLB_4M        0x04 /* Data TLB, 4M pages */
 222 #define CPUID_CACHE_ICACHE_8K      0x06 /* Instruction cache, 8K */
 223 #define CPUID_CACHE_ICACHE_16K     0x08 /* Instruction cache, 16K */
 224 #define CPUID_CACHE_DCACHE_8K      0x0A /* Data cache, 8K */
 225 #define CPUID_CACHE_DCACHE_16K     0x0C /* Data cache, 16K */
 226 #define CPUID_CACHE_L3CACHE_512K   0x22 /* 3rd-level cache, 512K */
 227 #define CPUID_CACHE_L3CACHE_1M     0x23 /* 3rd-level cache, 1M */
 228 #define CPUID_CACHE_L3CACHE_2M     0x25 /* 3rd-level cache, 2M */
 229 #define CPUID_CACHE_L3CACHE_4M     0x29 /* 3rd-level cache, 4M */
 230 #define CPUID_CACHE_DCACHE_32K     0x2C /* Data cache, 32K, 8-way */
 231 #define CPUID_CACHE_ICACHE_32K     0x30 /* Instruction cache, 32K, 8-way */
 232 #define CPUID_CACHE_UCACHE_128K_S4 0x39 /* 2nd-level cache, 128K, 4-way, sectored */
 233 #define CPUID_CACHE_UCACHE_128K_S2 0x3B /* 2nd-level cache, 128K, 2-way, sectored */
 234 #define CPUID_CACHE_UCACHE_256K_S4 0x3C /* 2nd-level cache, 256K, 4-way, sectored */
 235 #define CPUID_CACHE_NOCACHE        0x40 /* No 2nd level or 3rd-level cache */
 236 #define CPUID_CACHE_UCACHE_128K    0x41 /* 2nd-level cache, 128K */
 237 #define CPUID_CACHE_UCACHE_256K    0x42 /* 2nd-level cache, 256K */
 238 #define CPUID_CACHE_UCACHE_512K    0x43 /* 2nd-level cache, 512K */
 239 #define CPUID_CACHE_UCACHE_1M      0x44 /* 2nd-level cache, 1M */
 240 #define CPUID_CACHE_UCACHE_2M      0x45 /* 2nd-level cache, 2M */
 241 #define CPUID_CACHE_ITLB_64        0x50 /* Instruction TLB, 64 entries */
 242 #define CPUID_CACHE_ITLB_128       0x51 /* Instruction TLB, 128 entries */
 243 #define CPUID_CACHE_ITLB_256       0x52 /* Instruction TLB, 256 entries */
 244 #define CPUID_CACHE_DTLB_64        0x5B /* Data TLB, 64 entries */
 245 #define CPUID_CACHE_DTLB_128       0x5C /* Data TLB, 128 entries */
 246 #define CPUID_CACHE_DTLB_256       0x5D /* Data TLB, 256 entries */
 247 #define CPUID_CACHE_DCACHE_16K_8   0x60 /* Data cache, 8K, 64 byte line size, 8-way */
 248 #define CPUID_CACHE_DCACHE_8K_64   0x66 /* Data cache, 8K, 64 byte line size */
 249 #define CPUID_CACHE_DCACHE_16K_64  0x67 /* Data cache, 16K, 64 byte line size */
 250 #define CPUID_CACHE_DCACHE_32K_64  0x68 /* Data cache, 32K, 64 byte line size */
 251 #define CPUID_CACHE_TRACE_12K      0x70 /* Trace cache 12K-uop, 8-way */
 252 #define CPUID_CACHE_TRACE_16K      0x71 /* Trace cache 16K-uop, 8-way */
 253 #define CPUID_CACHE_TRACE_32K      0x72 /* Trace cache 32K-uop, 8-way */
 254 #define CPUID_CACHE_UCACHE_1M_64_4 0x78 /* 2nd-level, 1M, 4-way, 64 bytes */
 255 #define CPUID_CACHE_UCACHE_128K_64 0x79 /* 2nd-level, 128K, 8-way, 64 bytes */
 256 #define CPUID_CACHE_UCACHE_256K_64 0x7A /* 2nd-level, 256K, 8-way, 64 bytes */
 257 #define CPUID_CACHE_UCACHE_512K_64 0x7B /* 2nd-level, 512K, 8-way, 64 bytes */
 258 #define CPUID_CACHE_UCACHE_1M_64   0x7C /* 2nd-level, 1M, 8-way, 64 bytes */
 259 #define CPUID_CACHE_UCACHE_2M_64   0x7D /* 2nd-level, 2M, 8-way, 64 bytes */
 260 #define CPUID_CACHE_UCACHE_512K_64_2  0x7F /* 2nd-level, 512K, 2-way, 64 bytes */
 261 #define CPUID_CACHE_UCACHE_256K_32 0x82 /* 2nd-level, 256K, 8-way, 32 bytes */
 262 #define CPUID_CACHE_UCACHE_512K_32 0x83 /* 2nd-level, 512K, 8-way, 32 bytes */
 263 #define CPUID_CACHE_UCACHE_1M_32   0x84 /* 2nd-level, 1M, 8-way, 32 bytes */
 264 #define CPUID_CACHE_UCACHE_2M_32   0x85 /* 2nd-level, 2M, 8-way, 32 bytes */
 265 #define CPUID_CACHE_UCACHE_512K_64_4 0x86 /* 2nd-level, 512K, 4-way, 64 bytes */
 266 #define CPUID_CACHE_UCACHE_1M_64_8 0x87 /* 2nd-level, 1M, 8-way, 64 bytes */
 267 #define CPUID_CACHE_ITLB_128_4     0xB0 /* Instruction TLB, 4-way, 128 entries */
 268 #define CPUID_CACHE_DTLB_128_4     0xB3 /* Data TLB, 4-way, 128 entries */
 269 #define CPUID_CACHE_PREFETCH_64    0xF0 /* 64-Byte Prefetching */
 270 #define CPUID_CACHE_PREFETCH_128   0xF1 /* 128-Byte Prefetching */
 271
 272 #ifndef ASSEMBLER
 273 #include <stdint.h>
 274 #include <mach/mach_types.h>
 275 #include <kern/kern_types.h>
 276 #include <mach/machine.h>
 277
 278
 279 static inline void
 280 do_cpuid(uint32_t selector, uint32_t *data)
 281 {
 282         asm("cpuid"
 283                 : "=a" (data[0]),
 284                   "=b" (data[1]),
 285                   "=c" (data[2]),
 286                   "=d" (data[3])
 287                 : "a"(selector));
 288 }
 289
 290 /*
 291  * Cache ID descriptor structure.
 292  * Note: description string absent in kernel.
 293  */
 294 typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ;
 295 typedef struct {
 296         unsigned char   value;          /* Descriptor value */
 297         cache_type_t    type;           /* Cache type */
 298         unsigned int    size;           /* Cache size */
 299         unsigned int    linesize;       /* Cache line size */
 300 #ifdef KERNEL
 301         const char      *description;   /* Cache description */
 302 #endif /* KERNEL */
 303 } cpuid_cache_desc_t;
 304
 305 #ifdef KERNEL
 306 #define CACHE_DESC(value,type,size,linesize,text) \
 307         { value, type, size, linesize, text }
 308 #else
 309 #define CACHE_DESC(value,type,size,linesize,text) \
 310         { value, type, size, linesize }
 311 #endif /* KERNEL */
 312
 313 /* Physical CPU info */
 314 typedef struct {
 315         char            cpuid_vendor[16];
 316         char            cpuid_brand_string[48];
 317         const char      *cpuid_model_string;
 318
 319         uint32_t        cpuid_value;
 320         cpu_type_t      cpuid_type;
 321         uint8_t         cpuid_family;
 322         uint8_t         cpuid_model;
 323         uint8_t         cpuid_extmodel;
 324         uint8_t         cpuid_extfamily;
 325         uint8_t         cpuid_stepping;
 326         uint32_t        cpuid_features;
 327         uint32_t        cpuid_signature;
 328         uint8_t         cpuid_brand;
 329
 330         uint32_t        cache_size[LCACHE_MAX];
 331         uint32_t        cache_linesize;
 332
 333         uint8_t         cache_info[64];    /* list of cache descriptors */
 334
 335 } i386_cpu_info_t;
 336
 337 #ifdef __cplusplus
 338 extern "C" {
 339 #endif
 340
 341 /*
 342  * External declarations
 343  */
 344 extern cpu_type_t       cpuid_cputype(int);
 345 extern void             cpuid_cpu_display(const char *, __unused int);
 346 extern void             cpuid_feature_display(const char *, __unused int);
 347 extern char *           cpuid_get_feature_names(uint32_t, char *, unsigned);
 348
 349 extern uint32_t         cpuid_features(void);
 350 extern uint32_t         cpuid_family(void);
 351
 352 extern void             cpuid_get_info(i386_cpu_info_t *info_p);
 353 extern i386_cpu_info_t  *cpuid_info(void);
 354
 355 /* XXX obsolescent: */
 356 extern uint32_t         cpuid_feature;
 357 extern void             set_cpu_model(void);
 358
 359 #ifdef __cplusplus
 360 }
 361 #endif
 362
 363 #endif /* ASSEMBLER */
 364
 365 #endif /* __APPLE_API_PRIVATE */
 366 #endif /* _MACHINE_CPUID_H_ */