pexpert/pexpert/ppc/protos.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. Please obtain a copy of the License at
  10  * http://www.opensource.apple.com/apsl/ and read it before using this
  11  * file.
  12  *
  13  * The Original Code and all software distributed under the License are
  14  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  15  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  16  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  18  * Please see the License for the specific language governing rights and
  19  * limitations under the License.
  20  *
  21  * @APPLE_LICENSE_HEADER_END@
  22  */
  23 #ifndef _PEXPERT_PPC_PROTOS_H_
  24 #define _PEXPERT_PPC_PROTOS_H_
  25
  26 #define mtsprg(n, reg)  __asm__ volatile("mtsprg  " # n ", %0" : : "r" (reg))
  27 #define mfsprg(reg, n)  __asm__ volatile("mfsprg  %0, " # n : "=r" (reg))
  28
  29 #define mtspr(spr, val)  __asm__ volatile("mtspr  " # spr ", %0" : : "r" (val))
  30 #define mfspr(reg, spr)  __asm__ volatile("mfspr  %0, " # spr : "=r" (reg))
  31
  32 /*
  33  * Various memory/IO synchronisation instructions
  34  */
  35
  36         /*      Use eieio as a memory barrier to order stores.
  37          *      Useful for device control and PTE maintenance.
  38          */
  39
  40 #define eieio() \
  41         __asm__ volatile("eieio")
  42
  43         /*      Use sync to ensure previous stores have completed.
  44                 This is  required when manipulating locks and/or
  45                 maintaining PTEs or other shared structures on SMP
  46                 machines.
  47         */
  48
  49 #define sync() \
  50         __asm__ volatile("sync")
  51
  52         /*      Use isync to sychronize context; that is, the ensure
  53                 no prefetching of instructions happen before the
  54                 instruction.
  55         */
  56
  57 #define isync() \
  58         __asm__ volatile("isync")
  59
  60
  61 //------------------------------------------------------------------------
  62 // from ppc/endian.h
  63 static __inline__ unsigned int byte_reverse_word(unsigned int word);
  64 static __inline__ unsigned int byte_reverse_word(unsigned int word) {
  65         unsigned int result;
  66         __asm__ volatile("lwbrx %0, 0, %1" : "=r" (result) : "r" (&word));
  67         return result;
  68 }
  69
  70 //------------------------------------------------------------------------
  71 // from ppc/serial_io.h
  72 extern void initialize_serial(void * scc_phys_base, uint32_t serial_baud);
  73
  74
  75 //------------------------------------------------------------------------
  76 // from osfmk/ppc/POWERMAC/video_console.c
  77
  78 extern void initialize_screen(void *, unsigned int);
  79
  80 extern void vc_progress_initialize( void * desc,
  81                                     const unsigned char * data,
  82                                     const unsigned char * clut );
  83
  84 extern void vc_display_icon( void * desc,
  85                              const unsigned char * data );
  86
  87 //-------------------------------------------------------------------------
  88 // from osfmk/console/panic_dialog.c
  89 extern void panic_ui_initialize(const unsigned char * clut);
  90
  91 // from osfmk/ppc/serial_console.c
  92 extern int  switch_to_serial_console(void);
  93 extern void switch_to_old_console(int old_console);
  94
  95 typedef unsigned spl_t;
  96
  97 //------------------------------------------------------------------------
  98 // from bsd/dev/ppc/busses.h which clashes with mach/device/device_types.h
  99 typedef int             io_req_t;
 100
 101
 102 //typedef struct ipc_port         *ipc_port_t;
 103
 104 extern void            cninit(void);
 105
 106 /*
 107  *      Temporarily stolen from Firmware.h
 108  */
 109
 110 extern void dbgTrace(unsigned int item1, unsigned int item2, unsigned int item3);
 111 #if 1           /* (TEST/DEBUG) - eliminate inline */
 112 extern __inline__ void dbgTrace(unsigned int item1, unsigned int item2, unsigned int item3) {
 113
 114         __asm__ volatile("mr   r3,%0" : : "r" (item1) : "r3");
 115         __asm__ volatile("mr   r4,%0" : : "r" (item2) : "r4");
 116         __asm__ volatile("mr   r5,%0" : : "r" (item3) : "r5");
 117         __asm__ volatile("lis  r0,hi16(CutTrace)" : : : "r0");
 118         __asm__ volatile("ori  r0,r0,lo16(CutTrace)" : : : "r0");
 119         __asm__ volatile("sc");
 120         return;
 121 }
 122 #endif
 123
 124 extern void DoPreempt(void);
 125 extern __inline__ void DoPreempt(void) {
 126         __asm__ volatile("lis  r0,hi16(DoPreemptCall)" : : : "r0");
 127         __asm__ volatile("ori  r0,r0,lo16(DoPreemptCall)" : : : "r0");
 128         __asm__ volatile("sc");
 129         return;
 130 }
 131
 132 extern void CreateFakeIO(void);
 133 extern __inline__ void CreateFakeIO(void) {
 134         __asm__ volatile("lis  r0,hi16(CreateFakeIOCall)" : : : "r0");
 135         __asm__ volatile("ori  r0,r0,lo16(CreateFakeIOCall)" : : : "r0");
 136         __asm__ volatile("sc");
 137                 return;
 138 }
 139
 140 extern void StoreReal(unsigned int val, unsigned int addr);
 141 extern void ReadReal(unsigned int raddr, unsigned int *vaddr);
 142 extern unsigned int LLTraceSet(unsigned int tflags);
 143 extern void GratefulDebInit(void);
 144 extern void GratefulDebDisp(unsigned int coord, unsigned int data);
 145 extern void checkNMI(void);
 146
 147 #endif /* _PEXPERT_PPC_PROTOS_H_ */