osfmk/ppc/commpage/bzero_32.s

   1 /*
   2  * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #define ASSEMBLER
  30 #include <sys/appleapiopts.h>
  31 #include <ppc/asm.h>
  32 #include <machine/cpu_capabilities.h>
  33 #include <machine/commpage.h>
  34
  35         .text
  36         .align  2
  37
  38
  39 // *******************
  40 // * B Z E R O _ 3 2 *
  41 // *******************
  42 //
  43 // For 32-bit processors with a 32-byte cache line.
  44 //
  45 // Register use:
  46 //              r0 = zero
  47 //              r3 = original ptr, not changed since memset returns it
  48 //              r4 = count of bytes to set
  49 //              r9 = working operand ptr
  50 // We do not touch r2 and r10-r12, which some callers depend on.
  51
  52         .align  5
  53 bzero_32:                                               // void bzero(void *b, size_t len);
  54         cmplwi  cr7,r4,32               // too short for DCBZ?
  55         li              r0,0                    // get a 0
  56         neg             r5,r3                   // start to compute #bytes to align
  57         mr              r9,r3                   // make copy of operand ptr (can't change r3)
  58         blt             cr7,Ltail               // length < 32, too short for DCBZ
  59
  60 // At least 32 bytes long, so compute alignment and #cache blocks.
  61
  62         andi.   r5,r5,0x1F              // r5 <-  #bytes to 32-byte align
  63         sub             r4,r4,r5                // adjust length
  64         srwi    r8,r4,5                 // r8 <- #32-byte chunks
  65         cmpwi   cr1,r8,0                // any chunks?
  66         mtctr   r8                              // set up loop count
  67         beq             1f                              // skip if already 32-byte aligned (r8!=0)
  68
  69 // 32-byte align.  We just store 32 0s, rather than test and use conditional
  70 // branches.  We've already stored the first few bytes above.
  71
  72         stw             r0,0(r9)
  73         stw             r0,4(r9)
  74         stw             r0,8(r9)
  75         stw             r0,12(r9)
  76         stw             r0,16(r9)
  77         stw             r0,20(r9)
  78         stw             r0,24(r9)
  79         stw             r0,28(r9)
  80         add             r9,r9,r5                // now rp is 32-byte aligned
  81         beq             cr1,Ltail               // skip if no 32-byte chunks
  82
  83 // Loop doing 32-byte version of DCBZ instruction.
  84 // NB: we take alignment exceptions on cache-inhibited memory.
  85 // The kernel could be changed to zero cr7 when emulating a
  86 // dcbz (as it does on 64-bit processors), so we could avoid all
  87 // but the first.
  88
  89 1:
  90         andi.   r5,r4,0x1F              // will there be trailing bytes?
  91         b               2f
  92         .align  4
  93 2:
  94         dcbz    0,r9                    // zero another 32 bytes
  95         addi    r9,r9,32
  96         bdnz    2b
  97
  98         beqlr                                   // no trailing bytes
  99
 100 // Store trailing bytes.
 101
 102 Ltail:
 103         andi.   r5,r4,0x10              // test bit 27 separately
 104         mtcrf   0x01,r4                 // remaining byte count to cr7
 105
 106         beq             2f                              // no 16-byte chunks
 107         stw             r0,0(r9)
 108         stw             r0,4(r9)
 109         stw             r0,8(r9)
 110         stw             r0,12(r9)
 111         addi    r9,r9,16
 112 2:
 113         bf              28,4f                   // 8-byte chunk?
 114         stw             r0,0(r9)
 115         stw             r0,4(r9)
 116         addi    r9,r9,8
 117 4:
 118         bf              29,5f                   // word?
 119         stw             r0,0(r9)
 120         addi    r9,r9,4
 121 5:
 122         bf              30,6f                   // halfword?
 123         sth             r0,0(r9)
 124         addi    r9,r9,2
 125 6:
 126         bflr    31                              // byte?
 127         stb             r0,0(r9)
 128         blr
 129
 130         COMMPAGE_DESCRIPTOR(bzero_32,_COMM_PAGE_BZERO,kCache32,0,kCommPage32)