pexpert/pexpert/arm64/BCM2837.h

   1 /*
   2  * Copyright (c) 2016 Apple Inc. All rights reserved.
   3  */
   4
   5 #ifndef _PEXPERT_ARM_BCM2837_H
   6 #define _PEXPERT_ARM_BCM2837_H
   7
   8 #ifdef BCM2837
   9 #include "arm64_common.h"
  10 #endif
  11
  12 #define NO_MONITOR 1
  13 #define NO_ECORE 1
  14
  15 #ifndef ASSEMBLER
  16
  17 #define PI3_UART
  18
  19 #define PI3_BREAK                               asm volatile("brk #0");
  20
  21 #define BCM2837_GPIO_BASE       0x3F200000
  22 #define BCM2837_GPIO_SIZE       0xA0
  23 #define BCM2837_GPFSEL0         0x3F200000
  24 #define BCM2837_GPSET0          0x3F20001C
  25 #define BCM2837_GPCLR0          0x3F200028
  26 #define BCM2837_GPPUD           0x3F200094
  27 #define BCM2837_GPPUDCLK0       0x3F200098
  28
  29 #define BCM2837_AUX_BASE        0x3F215000
  30 #define BCM2837_AUX_SIZE        0x70
  31 #define BCM2837_AUX_ENABLES     0x3F215004
  32 #define BCM2837_AUX_MU_IO_REG   0x3F215040
  33 #define BCM2837_AUX_MU_IER_REG  0x3F215044
  34 #define BCM2837_AUX_MU_IIR_REG  0x3F215048
  35 #define BCM2837_AUX_MU_LCR_REG  0x3F21504C
  36 #define BCM2837_AUX_MU_MCR_REG  0x3F215050
  37 #define BCM2837_AUX_MU_LSR_REG  0x3F215054
  38 #define BCM2837_AUX_MU_MSR_REG  0x3F215058
  39 #define BCM2837_AUX_MU_SCRATCH  0x3F21505C
  40 #define BCM2837_AUX_MU_CNTL_REG 0x3F215060
  41 #define BCM2837_AUX_MU_STAT_REG 0x3F215064
  42 #define BCM2837_AUX_MU_BAUD_REG 0x3F215068
  43
  44 #define BCM2837_GPFSEL0_V               (pi3_gpio_base_vaddr + 0x0)
  45 #define BCM2837_GPSET0_V                (pi3_gpio_base_vaddr + 0x1C)
  46 #define BCM2837_GPCLR0_V                (pi3_gpio_base_vaddr + 0x28)
  47 #define BCM2837_GPPUD_V                 (pi3_gpio_base_vaddr + 0x94)
  48 #define BCM2837_GPPUDCLK0_V             (pi3_gpio_base_vaddr + 0x98)
  49
  50 #define BCM2837_FSEL_INPUT              0x0
  51 #define BCM2837_FSEL_OUTPUT             0x1
  52 #define BCM2837_FSEL_ALT0               0x4
  53 #define BCM2837_FSEL_ALT1               0x5
  54 #define BCM2837_FSEL_ALT2               0x6
  55 #define BCM2837_FSEL_ALT3               0x7
  56 #define BCM2837_FSEL_ALT4               0x3
  57 #define BCM2837_FSEL_ALT5               0x2
  58
  59 #define BCM2837_FSEL_NFUNCS             54
  60 #define BCM2837_FSEL_REG(func)          (BCM2837_GPFSEL0_V + (4 * ((func) / 10)))
  61 #define BCM2837_FSEL_OFFS(func)         (((func) % 10) * 3)
  62 #define BCM2837_FSEL_MASK(func)         (0x7 << BCM2837_FSEL_OFFS(func))
  63
  64 #define BCM2837_AUX_ENABLES_V           (pi3_aux_base_vaddr + 0x4)
  65 #define BCM2837_AUX_MU_IO_REG_V         (pi3_aux_base_vaddr + 0x40)
  66 #define BCM2837_AUX_MU_IER_REG_V        (pi3_aux_base_vaddr + 0x44)
  67 #define BCM2837_AUX_MU_IIR_REG_V        (pi3_aux_base_vaddr + 0x48)
  68 #define BCM2837_AUX_MU_LCR_REG_V        (pi3_aux_base_vaddr + 0x4C)
  69 #define BCM2837_AUX_MU_MCR_REG_V        (pi3_aux_base_vaddr + 0x50)
  70 #define BCM2837_AUX_MU_LSR_REG_V        (pi3_aux_base_vaddr + 0x54)
  71 #define BCM2837_AUX_MU_MSR_REG_V        (pi3_aux_base_vaddr + 0x58)
  72 #define BCM2837_AUX_MU_SCRATCH_V        (pi3_aux_base_vaddr + 0x5C)
  73 #define BCM2837_AUX_MU_CNTL_REG_V       (pi3_aux_base_vaddr + 0x60)
  74 #define BCM2837_AUX_MU_STAT_REG_V       (pi3_aux_base_vaddr + 0x64)
  75 #define BCM2837_AUX_MU_BAUD_REG_V       (pi3_aux_base_vaddr + 0x68)
  76 #define BCM2837_PUT32(addr, value) do { *((volatile uint32_t *) addr) = value; } while(0)
  77 #define BCM2837_GET32(addr) *((volatile uint32_t *) addr)
  78
  79 #define PLATFORM_PANIC_LOG_PADDR        0x3c0fc000
  80 #define PLATFORM_PANIC_LOG_SIZE         16384        // 16kb
  81 #endif /* ! ASSEMBLER */
  82
  83 #endif /* ! _PEXPERT_ARM_BCM2837_H */