osfmk/i386/cpuid.h

   1 /*
   2  * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31
  32 /*
  33  * x86 CPU identification
  34  *
  35  */
  36
  37 #ifndef _MACHINE_CPUID_H_
  38 #define _MACHINE_CPUID_H_
  39
  40 #include <sys/appleapiopts.h>
  41
  42 #ifdef __APPLE_API_PRIVATE
  43
  44 #define CPUID_VID_INTEL         "GenuineIntel"
  45 #define CPUID_VID_AMD           "AuthenticAMD"
  46
  47 #define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"
  48
  49 #define _Bit(n)                 (1ULL << n)
  50 #define _HBit(n)                (1ULL << ((n)+32))
  51
  52 /*
  53  * The CPUID_FEATURE_XXX values define 64-bit values
  54  * returned in %ecx:%edx to a CPUID request with %eax of 1:
  55  */
  56 #define CPUID_FEATURE_FPU       _Bit(0)   /* Floating point unit on-chip */
  57 #define CPUID_FEATURE_VME       _Bit(1)   /* Virtual Mode Extension */
  58 #define CPUID_FEATURE_DE        _Bit(2)   /* Debugging Extension */
  59 #define CPUID_FEATURE_PSE       _Bit(3)   /* Page Size Extension */
  60 #define CPUID_FEATURE_TSC       _Bit(4)   /* Time Stamp Counter */
  61 #define CPUID_FEATURE_MSR       _Bit(5)   /* Model Specific Registers */
  62 #define CPUID_FEATURE_PAE       _Bit(6)   /* Physical Address Extension */
  63 #define CPUID_FEATURE_MCE       _Bit(7)   /* Machine Check Exception */
  64 #define CPUID_FEATURE_CX8       _Bit(8)   /* CMPXCHG8B */
  65 #define CPUID_FEATURE_APIC      _Bit(9)   /* On-chip APIC */
  66 #define CPUID_FEATURE_SEP       _Bit(11)  /* Fast System Call */
  67 #define CPUID_FEATURE_MTRR      _Bit(12)  /* Memory Type Range Register */
  68 #define CPUID_FEATURE_PGE       _Bit(13)  /* Page Global Enable */
  69 #define CPUID_FEATURE_MCA       _Bit(14)  /* Machine Check Architecture */
  70 #define CPUID_FEATURE_CMOV      _Bit(15)  /* Conditional Move Instruction */
  71 #define CPUID_FEATURE_PAT       _Bit(16)  /* Page Attribute Table */
  72 #define CPUID_FEATURE_PSE36     _Bit(17)  /* 36-bit Page Size Extension */
  73 #define CPUID_FEATURE_PSN       _Bit(18)  /* Processor Serial Number */
  74 #define CPUID_FEATURE_CLFSH     _Bit(19)  /* CLFLUSH Instruction supported */
  75 #define CPUID_FEATURE_DS        _Bit(21)  /* Debug Store */
  76 #define CPUID_FEATURE_ACPI      _Bit(22)  /* Thermal monitor and Clock Ctrl */
  77 #define CPUID_FEATURE_MMX       _Bit(23)  /* MMX supported */
  78 #define CPUID_FEATURE_FXSR      _Bit(24)  /* Fast floating pt save/restore */
  79 #define CPUID_FEATURE_SSE       _Bit(25)  /* Streaming SIMD extensions */
  80 #define CPUID_FEATURE_SSE2      _Bit(26)  /* Streaming SIMD extensions 2 */
  81 #define CPUID_FEATURE_SS        _Bit(27)  /* Self-Snoop */
  82 #define CPUID_FEATURE_HTT       _Bit(28)  /* Hyper-Threading Technology */
  83 #define CPUID_FEATURE_TM        _Bit(29)  /* Thermal Monitor (TM1) */
  84 #define CPUID_FEATURE_PBE       _Bit(31)  /* Pend Break Enable */
  85
  86 #define CPUID_FEATURE_SSE3      _HBit(0)  /* Streaming SIMD extensions 3 */
  87 #define CPUID_FEATURE_PCLMULQDQ _HBit(1)  /* PCLMULQDQ instruction */
  88 #define CPUID_FEATURE_DTES64    _HBit(2)  /* 64-bit DS layout */
  89 #define CPUID_FEATURE_MONITOR   _HBit(3)  /* Monitor/mwait */
  90 #define CPUID_FEATURE_DSCPL     _HBit(4)  /* Debug Store CPL */
  91 #define CPUID_FEATURE_VMX       _HBit(5)  /* VMX */
  92 #define CPUID_FEATURE_SMX       _HBit(6)  /* SMX */
  93 #define CPUID_FEATURE_EST       _HBit(7)  /* Enhanced SpeedsTep (GV3) */
  94 #define CPUID_FEATURE_TM2       _HBit(8)  /* Thermal Monitor 2 */
  95 #define CPUID_FEATURE_SSSE3     _HBit(9)  /* Supplemental SSE3 instructions */
  96 #define CPUID_FEATURE_CID       _HBit(10) /* L1 Context ID */
  97 #define CPUID_FEATURE_CX16      _HBit(13) /* CmpXchg16b instruction */
  98 #define CPUID_FEATURE_xTPR      _HBit(14) /* Send Task PRiority msgs */
  99 #define CPUID_FEATURE_PDCM      _HBit(15) /* Perf/Debug Capability MSR */
 100
 101 #define CPUID_FEATURE_DCA       _HBit(18) /* Direct Cache Access */
 102 #define CPUID_FEATURE_SSE4_1    _HBit(19) /* Streaming SIMD extensions 4.1 */
 103 #define CPUID_FEATURE_SSE4_2    _HBit(20) /* Streaming SIMD extensions 4.2 */
 104 #define CPUID_FEATURE_xAPIC     _HBit(21) /* Extended APIC Mode */
 105 #define CPUID_FEATURE_MOVBE     _HBit(22) /* MOVBE instruction */
 106 #define CPUID_FEATURE_POPCNT    _HBit(23) /* POPCNT instruction */
 107 #define CPUID_FEATURE_AES       _HBit(25) /* AES instructions */
 108 #define CPUID_FEATURE_XSAVE     _HBit(26) /* XSAVE instructions */
 109 #define CPUID_FEATURE_OSXSAVE   _HBit(27) /* XGETBV/XSETBV instructions */
 110 #define CPUID_FEATURE_VMM       _HBit(31) /* VMM (Hypervisor) present */
 111 #define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
 112 #define CPUID_FEATURE_PCID      _HBit(17) /* ASID-PCID support */
 113 #define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
 114 #define CPUID_FEATURE_AVX1_0    _HBit(28) /* AVX 1.0 instructions */
 115
 116 /*
 117  * The CPUID_EXTFEATURE_XXX values define 64-bit values
 118  * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
 119  */
 120 #define CPUID_EXTFEATURE_SYSCALL   _Bit(11)     /* SYSCALL/sysret */
 121 #define CPUID_EXTFEATURE_XD        _Bit(20)     /* eXecute Disable */
 122
 123 #define CPUID_EXTFEATURE_1GBPAGE   _Bit(26)     /* 1GB pages */
 124 #define CPUID_EXTFEATURE_RDTSCP    _Bit(27)     /* RDTSCP */
 125 #define CPUID_EXTFEATURE_EM64T     _Bit(29)     /* Extended Mem 64 Technology */
 126
 127 #define CPUID_EXTFEATURE_LAHF      _HBit(0)     /* LAFH/SAHF instructions */
 128
 129 /*
 130  * The CPUID_EXTFEATURE_XXX values define 64-bit values
 131  * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
 132  */
 133 #define CPUID_EXTFEATURE_TSCI      _Bit(8)      /* TSC Invariant */
 134
 135 #define CPUID_CACHE_SIZE        16      /* Number of descriptor values */
 136
 137 #define CPUID_MWAIT_EXTENSION   _Bit(0) /* enumeration of WMAIT extensions */
 138 #define CPUID_MWAIT_BREAK       _Bit(1) /* interrupts are break events     */
 139
 140 #define CPUID_MODEL_YONAH       0x0E
 141 #define CPUID_MODEL_MEROM       0x0F
 142 #define CPUID_MODEL_PENRYN      0x17
 143 #define CPUID_MODEL_NEHALEM     0x1A
 144 #define CPUID_MODEL_FIELDS      0x1E    /* Lynnfield, Clarksfield, Jasper */
 145 #define CPUID_MODEL_DALES       0x1F    /* Havendale, Auburndale */
 146 #define CPUID_MODEL_NEHALEM_EX  0x2E
 147 #define CPUID_MODEL_DALES_32NM  0x25    /* Clarkdale, Arrandale */
 148 #define CPUID_MODEL_WESTMERE    0x2C    /* Gulftown, Westmere-EP, Westmere-WS */
 149 #define CPUID_MODEL_WESTMERE_EX 0x2F
 150 #define CPUID_MODEL_SANDYBRIDGE 0x2A
 151 #define CPUID_MODEL_JAKETOWN    0x2D
 152
 153 #ifndef ASSEMBLER
 154 #include <stdint.h>
 155 #include <mach/mach_types.h>
 156 #include <kern/kern_types.h>
 157 #include <mach/machine.h>
 158
 159
 160 typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
 161 static inline void
 162 cpuid(uint32_t *data)
 163 {
 164         asm("cpuid"
 165                 : "=a" (data[eax]),
 166                   "=b" (data[ebx]),
 167                   "=c" (data[ecx]),
 168                   "=d" (data[edx])
 169                 : "a"  (data[eax]),
 170                   "b"  (data[ebx]),
 171                   "c"  (data[ecx]),
 172                   "d"  (data[edx]));
 173 }
 174
 175 static inline void
 176 do_cpuid(uint32_t selector, uint32_t *data)
 177 {
 178         asm("cpuid"
 179                 : "=a" (data[0]),
 180                   "=b" (data[1]),
 181                   "=c" (data[2]),
 182                   "=d" (data[3])
 183                 : "a"(selector),
 184                   "b" (0),
 185                   "c" (0),
 186                   "d" (0));
 187 }
 188
 189 /*
 190  * Cache ID descriptor structure, used to parse CPUID leaf 2.
 191  * Note: not used in kernel.
 192  */
 193 typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t ;
 194 typedef struct {
 195         unsigned char   value;          /* Descriptor value */
 196         cache_type_t    type;           /* Cache type */
 197         unsigned int    size;           /* Cache size */
 198         unsigned int    linesize;       /* Cache line size */
 199 #ifdef KERNEL
 200         const char      *description;   /* Cache description */
 201 #endif /* KERNEL */
 202 } cpuid_cache_desc_t;
 203
 204 #ifdef KERNEL
 205 #define CACHE_DESC(value,type,size,linesize,text) \
 206         { value, type, size, linesize, text }
 207 #else
 208 #define CACHE_DESC(value,type,size,linesize,text) \
 209         { value, type, size, linesize }
 210 #endif /* KERNEL */
 211
 212 /* Monitor/mwait Leaf: */
 213 typedef struct {
 214         uint32_t        linesize_min;
 215         uint32_t        linesize_max;
 216         uint32_t        extensions;
 217         uint32_t        sub_Cstates;
 218 } cpuid_mwait_leaf_t;
 219
 220 /* Thermal and Power Management Leaf: */
 221 typedef struct {
 222         boolean_t       sensor;
 223         boolean_t       dynamic_acceleration;
 224         boolean_t       invariant_APIC_timer;
 225         boolean_t       core_power_limits;
 226         boolean_t       fine_grain_clock_mod;
 227         boolean_t       package_thermal_intr;
 228         uint32_t        thresholds;
 229         boolean_t       ACNT_MCNT;
 230         boolean_t       hardware_feedback;
 231         boolean_t       energy_policy;
 232 } cpuid_thermal_leaf_t;
 233
 234
 235 /* XSAVE Feature Leaf: */
 236 typedef struct {
 237         uint32_t        extended_state[4];      /* eax .. edx */
 238 } cpuid_xsave_leaf_t;
 239
 240
 241 /* Architectural Performance Monitoring Leaf: */
 242 typedef struct {
 243         uint8_t         version;
 244         uint8_t         number;
 245         uint8_t         width;
 246         uint8_t         events_number;
 247         uint32_t        events;
 248         uint8_t         fixed_number;
 249         uint8_t         fixed_width;
 250 } cpuid_arch_perf_leaf_t;
 251
 252 /* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
 253 typedef struct {
 254         char            cpuid_vendor[16];
 255         char            cpuid_brand_string[48];
 256         const char      *cpuid_model_string;
 257
 258         cpu_type_t      cpuid_type;     /* this is *not* a cpu_type_t in our <mach/machine.h> */
 259         uint8_t         cpuid_family;
 260         uint8_t         cpuid_model;
 261         uint8_t         cpuid_extmodel;
 262         uint8_t         cpuid_extfamily;
 263         uint8_t         cpuid_stepping;
 264         uint64_t        cpuid_features;
 265         uint64_t        cpuid_extfeatures;
 266         uint32_t        cpuid_signature;
 267         uint8_t         cpuid_brand;
 268         uint8_t         cpuid_processor_flag;
 269
 270         uint32_t        cache_size[LCACHE_MAX];
 271         uint32_t        cache_linesize;
 272
 273         uint8_t         cache_info[64];    /* list of cache descriptors */
 274
 275         uint32_t        cpuid_cores_per_package;
 276         uint32_t        cpuid_logical_per_package;
 277         uint32_t        cache_sharing[LCACHE_MAX];
 278         uint32_t        cache_partitions[LCACHE_MAX];
 279
 280         cpu_type_t      cpuid_cpu_type;                 /* <mach/machine.h> */
 281         cpu_subtype_t   cpuid_cpu_subtype;              /* <mach/machine.h> */
 282
 283         /* Per-vendor info */
 284         cpuid_mwait_leaf_t      cpuid_mwait_leaf;
 285 #define cpuid_mwait_linesize_max        cpuid_mwait_leaf.linesize_max
 286 #define cpuid_mwait_linesize_min        cpuid_mwait_leaf.linesize_min
 287 #define cpuid_mwait_extensions          cpuid_mwait_leaf.extensions
 288 #define cpuid_mwait_sub_Cstates         cpuid_mwait_leaf.sub_Cstates
 289         cpuid_thermal_leaf_t    cpuid_thermal_leaf;
 290         cpuid_arch_perf_leaf_t  cpuid_arch_perf_leaf;
 291         cpuid_xsave_leaf_t      cpuid_xsave_leaf;
 292
 293         /* Cache details: */
 294         uint32_t        cpuid_cache_linesize;
 295         uint32_t        cpuid_cache_L2_associativity;
 296         uint32_t        cpuid_cache_size;
 297
 298         /* Virtual and physical address aize: */
 299         uint32_t        cpuid_address_bits_physical;
 300         uint32_t        cpuid_address_bits_virtual;
 301
 302         uint32_t        cpuid_microcode_version;
 303
 304         /* Numbers of tlbs per processor [i|d, small|large, level0|level1] */
 305         uint32_t        cpuid_tlb[2][2][2];
 306                         #define TLB_INST        0
 307                         #define TLB_DATA        1
 308                         #define TLB_SMALL       0
 309                         #define TLB_LARGE       1
 310         uint32_t        cpuid_stlb;
 311
 312         uint32_t        core_count;
 313         uint32_t        thread_count;
 314
 315         /* Max leaf ids available from CPUID */
 316         uint32_t        cpuid_max_basic;
 317         uint32_t        cpuid_max_ext;
 318
 319         /* Family-specific info links */
 320         uint32_t                cpuid_cpufamily;
 321         cpuid_mwait_leaf_t      *cpuid_mwait_leafp;
 322         cpuid_thermal_leaf_t    *cpuid_thermal_leafp;
 323         cpuid_arch_perf_leaf_t  *cpuid_arch_perf_leafp;
 324         cpuid_xsave_leaf_t      *cpuid_xsave_leafp;
 325 } i386_cpu_info_t;
 326
 327 #ifdef __cplusplus
 328 extern "C" {
 329 #endif
 330
 331 /*
 332  * External declarations
 333  */
 334 extern cpu_type_t       cpuid_cputype(void);
 335 extern cpu_subtype_t    cpuid_cpusubtype(void);
 336 extern void             cpuid_cpu_display(const char *);
 337 extern void             cpuid_feature_display(const char *);
 338 extern void             cpuid_extfeature_display(const char *);
 339 extern char *           cpuid_get_feature_names(uint64_t, char *, unsigned);
 340 extern char *           cpuid_get_extfeature_names(uint64_t, char *, unsigned);
 341
 342 extern uint64_t         cpuid_features(void);
 343 extern uint64_t         cpuid_extfeatures(void);
 344 extern uint32_t         cpuid_family(void);
 345 extern uint32_t         cpuid_cpufamily(void);
 346
 347 extern void             cpuid_get_info(i386_cpu_info_t *info_p);
 348 extern i386_cpu_info_t  *cpuid_info(void);
 349
 350 extern void             cpuid_set_info(void);
 351
 352 #ifdef __cplusplus
 353 }
 354 #endif
 355
 356 #endif /* ASSEMBLER */
 357
 358 #endif /* __APPLE_API_PRIVATE */
 359 #endif /* _MACHINE_CPUID_H_ */