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1 /*
2 * Copyright (c) 2000-2020 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /*
32 * Mach Operating System
33 * Copyright (c) 1991,1990,1989,1988 Carnegie Mellon University
34 * All Rights Reserved.
35 *
36 * Permission to use, copy, modify and distribute this software and its
37 * documentation is hereby granted, provided that both the copyright
38 * notice and this permission notice appear in all copies of the
39 * software, derivative works or modified versions, and any portions
40 * thereof, and that both notices appear in supporting documentation.
41 *
42 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
43 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
44 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
45 *
46 * Carnegie Mellon requests users of this software to return to
47 *
48 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
49 * School of Computer Science
50 * Carnegie Mellon University
51 * Pittsburgh PA 15213-3890
52 *
53 * any improvements or extensions that they make and grant Carnegie Mellon
54 * the rights to redistribute these changes.
55 */
56 /*
57 */
58
59 /*
60 * Hardware trap/fault handler.
61 */
62
63 #include <mach_kdp.h>
64 #include <mach_ldebug.h>
65
66 #include <types.h>
67 #include <i386/eflags.h>
68 #include <i386/trap.h>
69 #include <i386/pmap.h>
70 #include <i386/fpu.h>
71 #include <i386/panic_notify.h>
72 #include <i386/lapic.h>
73
74 #include <mach/exception.h>
75 #include <mach/kern_return.h>
76 #include <mach/vm_param.h>
77 #include <mach/i386/thread_status.h>
78
79 #include <vm/vm_kern.h>
80 #include <vm/vm_fault.h>
81
82 #include <kern/kern_types.h>
83 #include <kern/processor.h>
84 #include <kern/thread.h>
85 #include <kern/task.h>
86 #include <kern/sched.h>
87 #include <kern/sched_prim.h>
88 #include <kern/exception.h>
89 #include <kern/spl.h>
90 #include <kern/misc_protos.h>
91 #include <kern/debug.h>
92 #if CONFIG_TELEMETRY
93 #include <kern/telemetry.h>
94 #endif
95 #include <sys/kdebug.h>
96 #include <kperf/kperf.h>
97 #include <prng/random.h>
98
99 #include <string.h>
100
101 #include <i386/postcode.h>
102 #include <i386/mp_desc.h>
103 #include <i386/proc_reg.h>
104 #include <i386/machine_routines.h>
105 #if CONFIG_MCA
106 #include <i386/machine_check.h>
107 #endif
108 #include <mach/i386/syscall_sw.h>
109
110 #include <libkern/OSDebug.h>
111 #include <i386/cpu_threads.h>
112 #include <machine/pal_routines.h>
113
114 extern void throttle_lowpri_io(int);
115 extern void kprint_state(x86_saved_state64_t *saved_state);
116 #if DEVELOPMENT || DEBUG
117 int insnstream_force_cacheline_mismatch = 0;
118 extern int panic_on_cacheline_mismatch;
119 extern char panic_on_trap_procname[];
120 extern uint32_t panic_on_trap_mask;
121 #endif
122
123 extern int insn_copyin_count;
124
125 /*
126 * Forward declarations
127 */
128 static void panic_trap(x86_saved_state64_t *saved_state, uint32_t pl, kern_return_t fault_result) __dead2;
129 static void set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip);
130 #if DEVELOPMENT || DEBUG
131 static __attribute__((noinline)) void copy_instruction_stream(thread_t thread, uint64_t rip, int trap_code, bool inspect_cacheline);
132 #else
133 static __attribute__((noinline)) void copy_instruction_stream(thread_t thread, uint64_t rip, int trap_code);
134 #endif
135
136 #if CONFIG_DTRACE
137 /* See <rdar://problem/4613924> */
138 perfCallback tempDTraceTrapHook = NULL; /* Pointer to DTrace fbt trap hook routine */
139
140 extern boolean_t dtrace_tally_fault(user_addr_t);
141 extern boolean_t dtrace_handle_trap(int, x86_saved_state_t *);
142 #endif
143
144 #ifdef MACH_BSD
145 extern char * proc_name_address(void *p);
146 #endif /* MACH_BSD */
147
148 extern boolean_t pmap_smep_enabled;
149 extern boolean_t pmap_smap_enabled;
150
151 __attribute__((noreturn))
152 void
153 thread_syscall_return(
154 kern_return_t ret)
155 {
156 thread_t thr_act = current_thread();
157 boolean_t is_mach;
158 int code;
159
160 pal_register_cache_state(thr_act, DIRTY);
161
162 if (thread_is_64bit_addr(thr_act)) {
163 x86_saved_state64_t *regs;
164
165 regs = USER_REGS64(thr_act);
166
167 code = (int) (regs->rax & SYSCALL_NUMBER_MASK);
168 is_mach = (regs->rax & SYSCALL_CLASS_MASK)
169 == (SYSCALL_CLASS_MACH << SYSCALL_CLASS_SHIFT);
170 if (kdebug_enable && is_mach) {
171 /* Mach trap */
172 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
173 MACHDBG_CODE(DBG_MACH_EXCP_SC, code) | DBG_FUNC_END,
174 ret, 0, 0, 0, 0);
175 }
176 regs->rax = ret;
177 #if DEBUG
178 if (is_mach) {
179 DEBUG_KPRINT_SYSCALL_MACH(
180 "thread_syscall_return: 64-bit mach ret=%u\n",
181 ret);
182 } else {
183 DEBUG_KPRINT_SYSCALL_UNIX(
184 "thread_syscall_return: 64-bit unix ret=%u\n",
185 ret);
186 }
187 #endif
188 } else {
189 x86_saved_state32_t *regs;
190
191 regs = USER_REGS32(thr_act);
192
193 code = ((int) regs->eax);
194 is_mach = (code < 0);
195 if (kdebug_enable && is_mach) {
196 /* Mach trap */
197 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
198 MACHDBG_CODE(DBG_MACH_EXCP_SC, -code) | DBG_FUNC_END,
199 ret, 0, 0, 0, 0);
200 }
201 regs->eax = ret;
202 #if DEBUG
203 if (is_mach) {
204 DEBUG_KPRINT_SYSCALL_MACH(
205 "thread_syscall_return: 32-bit mach ret=%u\n",
206 ret);
207 } else {
208 DEBUG_KPRINT_SYSCALL_UNIX(
209 "thread_syscall_return: 32-bit unix ret=%u\n",
210 ret);
211 }
212 #endif
213 }
214
215 #if DEBUG || DEVELOPMENT
216 kern_allocation_name_t
217 prior __assert_only = thread_get_kernel_state(thr_act)->allocation_name;
218 assertf(prior == NULL, "thread_set_allocation_name(\"%s\") not cleared", kern_allocation_get_name(prior));
219 #endif /* DEBUG || DEVELOPMENT */
220
221 throttle_lowpri_io(1);
222
223 thread_exception_return();
224 /*NOTREACHED*/
225 }
226
227 /*
228 * Fault recovery in copyin/copyout routines.
229 */
230 struct recovery {
231 uintptr_t fault_addr;
232 uintptr_t recover_addr;
233 };
234
235 extern struct recovery recover_table[];
236 extern struct recovery recover_table_end[];
237
238 const char * trap_type[] = {TRAP_NAMES};
239 unsigned TRAP_TYPES = sizeof(trap_type) / sizeof(trap_type[0]);
240
241 extern void PE_incoming_interrupt(int interrupt);
242
243 #if defined(__x86_64__) && DEBUG
244 void
245 kprint_state(x86_saved_state64_t *saved_state)
246 {
247 kprintf("current_cpu_datap() 0x%lx\n", (uintptr_t)current_cpu_datap());
248 kprintf("Current GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_GS_BASE));
249 kprintf("Kernel GS base MSR 0x%llx\n", rdmsr64(MSR_IA32_KERNEL_GS_BASE));
250 kprintf("state at 0x%lx:\n", (uintptr_t) saved_state);
251
252 kprintf(" rdi 0x%llx\n", saved_state->rdi);
253 kprintf(" rsi 0x%llx\n", saved_state->rsi);
254 kprintf(" rdx 0x%llx\n", saved_state->rdx);
255 kprintf(" r10 0x%llx\n", saved_state->r10);
256 kprintf(" r8 0x%llx\n", saved_state->r8);
257 kprintf(" r9 0x%llx\n", saved_state->r9);
258
259 kprintf(" cr2 0x%llx\n", saved_state->cr2);
260 kprintf("real cr2 0x%lx\n", get_cr2());
261 kprintf(" r15 0x%llx\n", saved_state->r15);
262 kprintf(" r14 0x%llx\n", saved_state->r14);
263 kprintf(" r13 0x%llx\n", saved_state->r13);
264 kprintf(" r12 0x%llx\n", saved_state->r12);
265 kprintf(" r11 0x%llx\n", saved_state->r11);
266 kprintf(" rbp 0x%llx\n", saved_state->rbp);
267 kprintf(" rbx 0x%llx\n", saved_state->rbx);
268 kprintf(" rcx 0x%llx\n", saved_state->rcx);
269 kprintf(" rax 0x%llx\n", saved_state->rax);
270
271 kprintf(" gs 0x%x\n", saved_state->gs);
272 kprintf(" fs 0x%x\n", saved_state->fs);
273
274 kprintf(" isf.trapno 0x%x\n", saved_state->isf.trapno);
275 kprintf(" isf._pad 0x%x\n", saved_state->isf._pad);
276 kprintf(" isf.trapfn 0x%llx\n", saved_state->isf.trapfn);
277 kprintf(" isf.err 0x%llx\n", saved_state->isf.err);
278 kprintf(" isf.rip 0x%llx\n", saved_state->isf.rip);
279 kprintf(" isf.cs 0x%llx\n", saved_state->isf.cs);
280 kprintf(" isf.rflags 0x%llx\n", saved_state->isf.rflags);
281 kprintf(" isf.rsp 0x%llx\n", saved_state->isf.rsp);
282 kprintf(" isf.ss 0x%llx\n", saved_state->isf.ss);
283 }
284 #endif
285
286
287 /*
288 * Non-zero indicates latency assert is enabled and capped at valued
289 * absolute time units.
290 */
291
292 uint64_t interrupt_latency_cap = 0;
293 boolean_t ilat_assert = FALSE;
294
295 void
296 interrupt_latency_tracker_setup(void)
297 {
298 uint32_t ilat_cap_us;
299 if (PE_parse_boot_argn("interrupt_latency_cap_us", &ilat_cap_us, sizeof(ilat_cap_us))) {
300 interrupt_latency_cap = ilat_cap_us * NSEC_PER_USEC;
301 nanoseconds_to_absolutetime(interrupt_latency_cap, &interrupt_latency_cap);
302 } else {
303 interrupt_latency_cap = LockTimeOut;
304 }
305 PE_parse_boot_argn("-interrupt_latency_assert_enable", &ilat_assert, sizeof(ilat_assert));
306 }
307
308 void
309 interrupt_reset_latency_stats(void)
310 {
311 uint32_t i;
312 for (i = 0; i < real_ncpus; i++) {
313 cpu_data_ptr[i]->cpu_max_observed_int_latency =
314 cpu_data_ptr[i]->cpu_max_observed_int_latency_vector = 0;
315 }
316 }
317
318 void
319 interrupt_populate_latency_stats(char *buf, unsigned bufsize)
320 {
321 uint32_t i, tcpu = ~0;
322 uint64_t cur_max = 0;
323
324 for (i = 0; i < real_ncpus; i++) {
325 if (cur_max < cpu_data_ptr[i]->cpu_max_observed_int_latency) {
326 cur_max = cpu_data_ptr[i]->cpu_max_observed_int_latency;
327 tcpu = i;
328 }
329 }
330
331 if (tcpu < real_ncpus) {
332 snprintf(buf, bufsize, "0x%x 0x%x 0x%llx", tcpu, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency_vector, cpu_data_ptr[tcpu]->cpu_max_observed_int_latency);
333 }
334 }
335
336 uint32_t interrupt_timer_coalescing_enabled = 1;
337 uint64_t interrupt_coalesced_timers;
338
339 /*
340 * Handle interrupts:
341 * - local APIC interrupts (IPIs, timers, etc) are handled by the kernel,
342 * - device interrupts go to the platform expert.
343 */
344 void
345 interrupt(x86_saved_state_t *state)
346 {
347 uint64_t rip;
348 uint64_t rsp;
349 int interrupt_num;
350 boolean_t user_mode = FALSE;
351 int ipl;
352 int cnum = cpu_number();
353 cpu_data_t *cdp = cpu_data_ptr[cnum];
354 int itype = DBG_INTR_TYPE_UNKNOWN;
355 int handled;
356
357 x86_saved_state64_t *state64 = saved_state64(state);
358 rip = state64->isf.rip;
359 rsp = state64->isf.rsp;
360 interrupt_num = state64->isf.trapno;
361 if (state64->isf.cs & 0x03) {
362 user_mode = TRUE;
363 }
364
365 #if DEVELOPMENT || DEBUG
366 uint64_t frameptr = is_saved_state64(state) ? state64->rbp : saved_state32(state)->ebp;
367 uint32_t traptrace_index = traptrace_start(interrupt_num, rip, mach_absolute_time(), frameptr);
368 #endif
369
370 if (cpu_data_ptr[cnum]->lcpu.package->num_idle == topoParms.nLThreadsPerPackage) {
371 cpu_data_ptr[cnum]->cpu_hwIntpexits[interrupt_num]++;
372 }
373
374 if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_INTERPROCESSOR_INTERRUPT)) {
375 itype = DBG_INTR_TYPE_IPI;
376 } else if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_TIMER_INTERRUPT)) {
377 itype = DBG_INTR_TYPE_TIMER;
378 } else {
379 itype = DBG_INTR_TYPE_OTHER;
380 }
381
382 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
383 MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_START,
384 interrupt_num,
385 (user_mode ? rip : VM_KERNEL_UNSLIDE(rip)),
386 user_mode, itype, 0);
387
388 SCHED_STATS_INC(interrupt_count);
389
390 #if CONFIG_TELEMETRY
391 if (telemetry_needs_record) {
392 telemetry_mark_curthread(user_mode, FALSE);
393 }
394 #endif
395
396 ipl = get_preemption_level();
397
398 /*
399 * Handle local APIC interrupts
400 * else call platform expert for devices.
401 */
402 handled = lapic_interrupt(interrupt_num, state);
403
404 if (!handled) {
405 if (interrupt_num == (LAPIC_DEFAULT_INTERRUPT_BASE + LAPIC_CMCI_INTERRUPT)) {
406 /*
407 * CMCI can be signalled on any logical processor, and the kexts
408 * that implement handling CMCI use IOKit to register handlers for
409 * the CMCI vector, so if we see a CMCI, do not encode a CPU
410 * number in bits 8:31 (since the vector is the same regardless of
411 * the handling CPU).
412 */
413 PE_incoming_interrupt(interrupt_num);
414 } else if (cnum <= lapic_max_interrupt_cpunum) {
415 PE_incoming_interrupt((cnum << 8) | interrupt_num);
416 }
417 }
418
419 if (__improbable(get_preemption_level() != ipl)) {
420 panic("Preemption level altered by interrupt vector 0x%x: initial 0x%x, final: 0x%x\n", interrupt_num, ipl, get_preemption_level());
421 }
422
423
424 if (__improbable(cdp->cpu_nested_istack)) {
425 cdp->cpu_nested_istack_events++;
426 } else {
427 uint64_t ctime = mach_absolute_time();
428 uint64_t int_latency = ctime - cdp->cpu_int_event_time;
429 uint64_t esdeadline, ehdeadline;
430 /* Attempt to process deferred timers in the context of
431 * this interrupt, unless interrupt time has already exceeded
432 * TCOAL_ILAT_THRESHOLD.
433 */
434 #define TCOAL_ILAT_THRESHOLD (30000ULL)
435
436 if ((int_latency < TCOAL_ILAT_THRESHOLD) &&
437 interrupt_timer_coalescing_enabled) {
438 esdeadline = cdp->rtclock_timer.queue.earliest_soft_deadline;
439 ehdeadline = cdp->rtclock_timer.deadline;
440 if ((ctime >= esdeadline) && (ctime < ehdeadline)) {
441 interrupt_coalesced_timers++;
442 TCOAL_DEBUG(0x88880000 | DBG_FUNC_START, ctime, esdeadline, ehdeadline, interrupt_coalesced_timers, 0);
443 rtclock_intr(state);
444 TCOAL_DEBUG(0x88880000 | DBG_FUNC_END, ctime, esdeadline, interrupt_coalesced_timers, 0, 0);
445 } else {
446 TCOAL_DEBUG(0x77770000, ctime, cdp->rtclock_timer.queue.earliest_soft_deadline, cdp->rtclock_timer.deadline, interrupt_coalesced_timers, 0);
447 }
448 }
449
450 if (__improbable(ilat_assert && (int_latency > interrupt_latency_cap) && !machine_timeout_suspended())) {
451 panic("Interrupt vector 0x%x exceeded interrupt latency threshold, 0x%llx absolute time delta, prior signals: 0x%x, current signals: 0x%x", interrupt_num, int_latency, cdp->cpu_prior_signals, cdp->cpu_signals);
452 }
453
454 if (__improbable(int_latency > cdp->cpu_max_observed_int_latency)) {
455 cdp->cpu_max_observed_int_latency = int_latency;
456 cdp->cpu_max_observed_int_latency_vector = interrupt_num;
457 }
458 }
459
460 /*
461 * Having serviced the interrupt first, look at the interrupted stack depth.
462 */
463 if (!user_mode) {
464 uint64_t depth = cdp->cpu_kernel_stack
465 + sizeof(struct thread_kernel_state)
466 + sizeof(struct i386_exception_link *)
467 - rsp;
468 if (__improbable(depth > kernel_stack_depth_max)) {
469 kernel_stack_depth_max = (vm_offset_t)depth;
470 KERNEL_DEBUG_CONSTANT(
471 MACHDBG_CODE(DBG_MACH_SCHED, MACH_STACK_DEPTH),
472 (long) depth, (long) VM_KERNEL_UNSLIDE(rip), 0, 0, 0);
473 }
474 }
475
476 if (cnum == master_cpu) {
477 ml_entropy_collect();
478 }
479
480 #if KPERF
481 kperf_interrupt();
482 #endif /* KPERF */
483
484 KDBG_RELEASE(MACHDBG_CODE(DBG_MACH_EXCP_INTR, 0) | DBG_FUNC_END,
485 interrupt_num);
486
487 assert(ml_get_interrupts_enabled() == FALSE);
488
489 #if DEVELOPMENT || DEBUG
490 if (traptrace_index != TRAPTRACE_INVALID_INDEX) {
491 traptrace_end(traptrace_index, mach_absolute_time());
492 }
493 #endif
494 }
495
496 static inline void
497 reset_dr7(void)
498 {
499 long dr7 = 0x400; /* magic dr7 reset value; 32 bit on i386, 64 bit on x86_64 */
500 __asm__ volatile ("mov %0,%%dr7" : : "r" (dr7));
501 }
502 #if MACH_KDP
503 unsigned kdp_has_active_watchpoints = 0;
504 #define NO_WATCHPOINTS (!kdp_has_active_watchpoints)
505 #else
506 #define NO_WATCHPOINTS 1
507 #endif
508 /*
509 * Trap from kernel mode. Only page-fault errors are recoverable,
510 * and then only in special circumstances. All other errors are
511 * fatal. Return value indicates if trap was handled.
512 */
513
514 void
515 kernel_trap(
516 x86_saved_state_t *state,
517 uintptr_t *lo_spp)
518 {
519 x86_saved_state64_t *saved_state;
520 int code;
521 user_addr_t vaddr;
522 int type;
523 vm_map_t map = 0; /* protected by T_PAGE_FAULT */
524 kern_return_t result = KERN_FAILURE;
525 kern_return_t fault_result = KERN_SUCCESS;
526 thread_t thread;
527 boolean_t intr;
528 vm_prot_t prot;
529 struct recovery *rp;
530 vm_offset_t kern_ip;
531 int is_user;
532 int trap_pl = get_preemption_level();
533
534 thread = current_thread();
535
536 if (__improbable(is_saved_state32(state))) {
537 panic("kernel_trap(%p) with 32-bit state", state);
538 }
539 saved_state = saved_state64(state);
540
541 /* Record cpu where state was captured */
542 saved_state->isf.cpu = cpu_number();
543
544 vaddr = (user_addr_t)saved_state->cr2;
545 type = saved_state->isf.trapno;
546 code = (int)(saved_state->isf.err & 0xffff);
547 intr = (saved_state->isf.rflags & EFL_IF) != 0; /* state of ints at trap */
548 kern_ip = (vm_offset_t)saved_state->isf.rip;
549
550 is_user = (vaddr < VM_MAX_USER_PAGE_ADDRESS);
551
552 #if DEVELOPMENT || DEBUG
553 uint32_t traptrace_index = traptrace_start(type, kern_ip, mach_absolute_time(), saved_state->rbp);
554 #endif
555
556 #if CONFIG_DTRACE
557 /*
558 * Is there a DTrace hook?
559 */
560 if (__improbable(tempDTraceTrapHook != NULL)) {
561 if (tempDTraceTrapHook(type, state, lo_spp, 0) == KERN_SUCCESS) {
562 /*
563 * If it succeeds, we are done...
564 */
565 goto common_return;
566 }
567 }
568
569 /* Handle traps originated from probe context. */
570 if (thread != THREAD_NULL && thread->t_dtrace_inprobe) {
571 if (dtrace_handle_trap(type, state)) {
572 goto common_return;
573 }
574 }
575
576 #endif /* CONFIG_DTRACE */
577
578 /*
579 * we come here with interrupts off as we don't want to recurse
580 * on preemption below. but we do want to re-enable interrupts
581 * as soon we possibly can to hold latency down
582 */
583 if (__improbable(T_PREEMPT == type)) {
584 ast_taken_kernel();
585
586 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
587 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
588 0, 0, 0, VM_KERNEL_UNSLIDE(kern_ip), 0);
589
590 goto common_return;
591 }
592
593 user_addr_t kd_vaddr = is_user ? vaddr : VM_KERNEL_UNSLIDE(vaddr);
594 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
595 (MACHDBG_CODE(DBG_MACH_EXCP_KTRAP_x86, type)) | DBG_FUNC_NONE,
596 (unsigned)(kd_vaddr >> 32), (unsigned)kd_vaddr, is_user,
597 VM_KERNEL_UNSLIDE(kern_ip), 0);
598
599
600 if (T_PAGE_FAULT == type) {
601 /*
602 * assume we're faulting in the kernel map
603 */
604 map = kernel_map;
605
606 if (__probable((thread != THREAD_NULL) && (thread->map != kernel_map) &&
607 (vaddr < VM_MAX_USER_PAGE_ADDRESS))) {
608 /* fault occurred in userspace */
609 map = thread->map;
610
611 /* Intercept a potential Supervisor Mode Execute
612 * Protection fault. These criteria identify
613 * both NX faults and SMEP faults, but both
614 * are fatal. We avoid checking PTEs (racy).
615 * (The VM could just redrive a SMEP fault, hence
616 * the intercept).
617 */
618 if (__improbable((code == (T_PF_PROT | T_PF_EXECUTE)) &&
619 (pmap_smep_enabled) && (saved_state->isf.rip == vaddr))) {
620 goto debugger_entry;
621 }
622
623 /*
624 * Additionally check for SMAP faults...
625 * which are characterized by page-present and
626 * the AC bit unset (i.e. not from copyin/out path).
627 */
628 if (__improbable(code & T_PF_PROT &&
629 pmap_smap_enabled &&
630 (saved_state->isf.rflags & EFL_AC) == 0)) {
631 goto debugger_entry;
632 }
633
634 /*
635 * If we're not sharing cr3 with the user
636 * and we faulted in copyio,
637 * then switch cr3 here and dismiss the fault.
638 */
639 if (no_shared_cr3 &&
640 (thread->machine.specFlags & CopyIOActive) &&
641 map->pmap->pm_cr3 != get_cr3_base()) {
642 pmap_assert(current_cpu_datap()->cpu_pmap_pcid_enabled == FALSE);
643 set_cr3_raw(map->pmap->pm_cr3);
644 return;
645 }
646 if (__improbable(vaddr < PAGE_SIZE) &&
647 ((thread->machine.specFlags & CopyIOActive) == 0)) {
648 goto debugger_entry;
649 }
650 }
651 }
652
653 (void) ml_set_interrupts_enabled(intr);
654
655 switch (type) {
656 case T_NO_FPU:
657 fpnoextflt();
658 goto common_return;
659
660 case T_FPU_FAULT:
661 fpextovrflt();
662 goto common_return;
663
664 case T_FLOATING_POINT_ERROR:
665 fpexterrflt();
666 goto common_return;
667
668 case T_SSE_FLOAT_ERROR:
669 fpSSEexterrflt();
670 goto common_return;
671
672 case T_INVALID_OPCODE:
673 fpUDflt(kern_ip);
674 goto debugger_entry;
675
676 case T_DEBUG:
677 if ((saved_state->isf.rflags & EFL_TF) == 0 && NO_WATCHPOINTS) {
678 /* We've somehow encountered a debug
679 * register match that does not belong
680 * to the kernel debugger.
681 * This isn't supposed to happen.
682 */
683 reset_dr7();
684 goto common_return;
685 }
686 goto debugger_entry;
687 case T_INT3:
688 goto debugger_entry;
689 case T_PAGE_FAULT:
690
691 #if CONFIG_DTRACE
692 if (thread != THREAD_NULL && thread->t_dtrace_inprobe) { /* Executing under dtrace_probe? */
693 if (dtrace_tally_fault(vaddr)) { /* Should a fault under dtrace be ignored? */
694 /*
695 * DTrace has "anticipated" the possibility of this fault, and has
696 * established the suitable recovery state. Drop down now into the
697 * recovery handling code in "case T_GENERAL_PROTECTION:".
698 */
699 goto FALL_THROUGH;
700 }
701 }
702 #endif /* CONFIG_DTRACE */
703
704 prot = VM_PROT_READ;
705
706 if (code & T_PF_WRITE) {
707 prot |= VM_PROT_WRITE;
708 }
709 if (code & T_PF_EXECUTE) {
710 prot |= VM_PROT_EXECUTE;
711 }
712
713 fault_result = result = vm_fault(map,
714 vaddr,
715 prot,
716 FALSE, VM_KERN_MEMORY_NONE,
717 THREAD_UNINT, NULL, 0);
718
719 if (result == KERN_SUCCESS) {
720 goto common_return;
721 }
722 /*
723 * fall through
724 */
725 #if CONFIG_DTRACE
726 FALL_THROUGH:
727 #endif /* CONFIG_DTRACE */
728
729 case T_GENERAL_PROTECTION:
730 /*
731 * If there is a failure recovery address
732 * for this fault, go there.
733 */
734 for (rp = recover_table; rp < recover_table_end; rp++) {
735 if (kern_ip == rp->fault_addr) {
736 set_recovery_ip(saved_state, rp->recover_addr);
737 goto common_return;
738 }
739 }
740
741 /*
742 * Check thread recovery address also.
743 */
744 if (thread != THREAD_NULL && thread->recover) {
745 set_recovery_ip(saved_state, thread->recover);
746 thread->recover = 0;
747 goto common_return;
748 }
749 /*
750 * Unanticipated page-fault errors in kernel
751 * should not happen.
752 *
753 * fall through...
754 */
755 OS_FALLTHROUGH;
756 default:
757 /*
758 * Exception 15 is reserved but some chips may generate it
759 * spuriously. Seen at startup on AMD Athlon-64.
760 */
761 if (type == 15) {
762 kprintf("kernel_trap() ignoring spurious trap 15\n");
763 goto common_return;
764 }
765 debugger_entry:
766 /* Ensure that the i386_kernel_state at the base of the
767 * current thread's stack (if any) is synchronized with the
768 * context at the moment of the trap, to facilitate
769 * access through the debugger.
770 */
771 sync_iss_to_iks(state);
772 #if MACH_KDP
773 if (kdp_i386_trap(type, saved_state, result, (vm_offset_t)vaddr)) {
774 goto common_return;
775 }
776 #endif
777 }
778 pal_cli();
779 panic_trap(saved_state, trap_pl, fault_result);
780 /*
781 * NO RETURN
782 */
783
784 common_return:
785 #if DEVELOPMENT || DEBUG
786 if (traptrace_index != TRAPTRACE_INVALID_INDEX) {
787 traptrace_end(traptrace_index, mach_absolute_time());
788 }
789 #endif
790 return;
791 }
792
793 static void
794 set_recovery_ip(x86_saved_state64_t *saved_state, vm_offset_t ip)
795 {
796 saved_state->isf.rip = ip;
797 }
798
799 static void
800 panic_trap(x86_saved_state64_t *regs, uint32_t pl, kern_return_t fault_result)
801 {
802 const char *trapname = "Unknown";
803 pal_cr_t cr0, cr2, cr3, cr4;
804 boolean_t potential_smep_fault = FALSE, potential_kernel_NX_fault = FALSE;
805 boolean_t potential_smap_fault = FALSE;
806
807 pal_get_control_registers( &cr0, &cr2, &cr3, &cr4 );
808 assert(ml_get_interrupts_enabled() == FALSE);
809 current_cpu_datap()->cpu_fatal_trap_state = regs;
810 /*
811 * Issue an I/O port read if one has been requested - this is an
812 * event logic analyzers can use as a trigger point.
813 */
814 panic_notify();
815
816 kprintf("CPU %d panic trap number 0x%x, rip 0x%016llx\n",
817 cpu_number(), regs->isf.trapno, regs->isf.rip);
818 kprintf("cr0 0x%016llx cr2 0x%016llx cr3 0x%016llx cr4 0x%016llx\n",
819 cr0, cr2, cr3, cr4);
820
821 if (regs->isf.trapno < TRAP_TYPES) {
822 trapname = trap_type[regs->isf.trapno];
823 }
824
825 if ((regs->isf.trapno == T_PAGE_FAULT) && (regs->isf.err == (T_PF_PROT | T_PF_EXECUTE)) && (regs->isf.rip == regs->cr2)) {
826 if (pmap_smep_enabled && (regs->isf.rip < VM_MAX_USER_PAGE_ADDRESS)) {
827 potential_smep_fault = TRUE;
828 } else if (regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
829 potential_kernel_NX_fault = TRUE;
830 }
831 } else if (pmap_smap_enabled &&
832 regs->isf.trapno == T_PAGE_FAULT &&
833 regs->isf.err & T_PF_PROT &&
834 regs->cr2 < VM_MAX_USER_PAGE_ADDRESS &&
835 regs->isf.rip >= VM_MIN_KERNEL_AND_KEXT_ADDRESS) {
836 potential_smap_fault = TRUE;
837 }
838
839 #undef panic
840 panic("Kernel trap at 0x%016llx, type %d=%s, registers:\n"
841 "CR0: 0x%016llx, CR2: 0x%016llx, CR3: 0x%016llx, CR4: 0x%016llx\n"
842 "RAX: 0x%016llx, RBX: 0x%016llx, RCX: 0x%016llx, RDX: 0x%016llx\n"
843 "RSP: 0x%016llx, RBP: 0x%016llx, RSI: 0x%016llx, RDI: 0x%016llx\n"
844 "R8: 0x%016llx, R9: 0x%016llx, R10: 0x%016llx, R11: 0x%016llx\n"
845 "R12: 0x%016llx, R13: 0x%016llx, R14: 0x%016llx, R15: 0x%016llx\n"
846 "RFL: 0x%016llx, RIP: 0x%016llx, CS: 0x%016llx, SS: 0x%016llx\n"
847 "Fault CR2: 0x%016llx, Error code: 0x%016llx, Fault CPU: 0x%x%s%s%s%s, PL: %d, VF: %d\n",
848 regs->isf.rip, regs->isf.trapno, trapname,
849 cr0, cr2, cr3, cr4,
850 regs->rax, regs->rbx, regs->rcx, regs->rdx,
851 regs->isf.rsp, regs->rbp, regs->rsi, regs->rdi,
852 regs->r8, regs->r9, regs->r10, regs->r11,
853 regs->r12, regs->r13, regs->r14, regs->r15,
854 regs->isf.rflags, regs->isf.rip, regs->isf.cs & 0xFFFF,
855 regs->isf.ss & 0xFFFF, regs->cr2, regs->isf.err, regs->isf.cpu,
856 virtualized ? " VMM" : "",
857 potential_kernel_NX_fault ? " Kernel NX fault" : "",
858 potential_smep_fault ? " SMEP/User NX fault" : "",
859 potential_smap_fault ? " SMAP fault" : "",
860 pl,
861 fault_result);
862 }
863
864 #if CONFIG_DTRACE
865 extern kern_return_t dtrace_user_probe(x86_saved_state_t *);
866 #endif
867
868 #if DEBUG
869 uint32_t fsigs[2];
870 uint32_t fsigns, fsigcs;
871 #endif
872
873 /*
874 * Trap from user mode.
875 */
876 void
877 user_trap(
878 x86_saved_state_t *saved_state)
879 {
880 int exc;
881 int err;
882 mach_exception_code_t code;
883 mach_exception_subcode_t subcode;
884 int type;
885 user_addr_t vaddr;
886 vm_prot_t prot;
887 thread_t thread = current_thread();
888 kern_return_t kret;
889 user_addr_t rip;
890 unsigned long dr6 = 0; /* 32 bit for i386, 64 bit for x86_64 */
891 int current_cpu = cpu_number();
892 #if DEVELOPMENT || DEBUG
893 bool inspect_cacheline = false;
894 uint32_t traptrace_index;
895 #endif
896 assert((is_saved_state32(saved_state) && !thread_is_64bit_addr(thread)) ||
897 (is_saved_state64(saved_state) && thread_is_64bit_addr(thread)));
898
899 if (is_saved_state64(saved_state)) {
900 x86_saved_state64_t *regs;
901
902 regs = saved_state64(saved_state);
903
904 /* Record cpu where state was captured */
905 regs->isf.cpu = current_cpu;
906
907 type = regs->isf.trapno;
908 err = (int)regs->isf.err & 0xffff;
909 vaddr = (user_addr_t)regs->cr2;
910 rip = (user_addr_t)regs->isf.rip;
911 #if DEVELOPMENT || DEBUG
912 traptrace_index = traptrace_start(type, rip, mach_absolute_time(), regs->rbp);
913 #endif
914 } else {
915 x86_saved_state32_t *regs;
916
917 regs = saved_state32(saved_state);
918
919 /* Record cpu where state was captured */
920 regs->cpu = current_cpu;
921
922 type = regs->trapno;
923 err = regs->err & 0xffff;
924 vaddr = (user_addr_t)regs->cr2;
925 rip = (user_addr_t)regs->eip;
926 #if DEVELOPMENT || DEBUG
927 traptrace_index = traptrace_start(type, rip, mach_absolute_time(), regs->ebp);
928 #endif
929 }
930
931 #if DEVELOPMENT || DEBUG
932 /*
933 * Copy the cacheline of code into the thread's instruction stream save area
934 * before enabling interrupts (the assumption is that we have not otherwise faulted or
935 * trapped since the original cache line stores). If the saved code is not valid,
936 * we'll catch it below when we process the copyin() for unhandled faults.
937 */
938 if (type == T_PAGE_FAULT || type == T_INVALID_OPCODE || type == T_GENERAL_PROTECTION) {
939 #define CACHELINE_SIZE 64
940 THREAD_TO_PCB(thread)->insn_cacheline[CACHELINE_SIZE] = (uint8_t)(rip & (CACHELINE_SIZE - 1));
941 bcopy(&cpu_shadowp(current_cpu)->cpu_rtimes[0],
942 &THREAD_TO_PCB(thread)->insn_cacheline[0],
943 sizeof(THREAD_TO_PCB(thread)->insn_cacheline) - 1);
944 inspect_cacheline = true;
945 }
946 #endif
947
948 if (type == T_DEBUG) {
949 if (thread->machine.ids) {
950 unsigned long clear = 0;
951 /* Stash and clear this processor's DR6 value, in the event
952 * this was a debug register match
953 */
954 __asm__ volatile ("mov %%db6, %0" : "=r" (dr6));
955 __asm__ volatile ("mov %0, %%db6" : : "r" (clear));
956 }
957 /* [Re]Enable LBRs *BEFORE* enabling interrupts to ensure we hit the right CPU */
958 i386_lbr_enable();
959 }
960
961 pal_sti();
962
963 KERNEL_DEBUG_CONSTANT_IST(KDEBUG_TRACE,
964 (MACHDBG_CODE(DBG_MACH_EXCP_UTRAP_x86, type)) | DBG_FUNC_NONE,
965 (unsigned)(vaddr >> 32), (unsigned)vaddr,
966 (unsigned)(rip >> 32), (unsigned)rip, 0);
967
968 code = 0;
969 subcode = 0;
970 exc = 0;
971
972 #if CONFIG_DTRACE
973 /*
974 * DTrace does not consume all user traps, only INT_3's for now.
975 * Avoid needlessly calling tempDTraceTrapHook here, and let the
976 * INT_3 case handle them.
977 */
978 #endif
979
980 DEBUG_KPRINT_SYSCALL_MASK(1,
981 "user_trap: type=0x%x(%s) err=0x%x cr2=%p rip=%p\n",
982 type, trap_type[type], err, (void *)(long) vaddr, (void *)(long) rip);
983
984 switch (type) {
985 case T_DIVIDE_ERROR:
986 exc = EXC_ARITHMETIC;
987 code = EXC_I386_DIV;
988 break;
989
990 case T_DEBUG:
991 {
992 pcb_t pcb;
993 /*
994 * Update the PCB with this processor's DR6 value
995 * in the event this was a debug register match.
996 */
997 pcb = THREAD_TO_PCB(thread);
998 if (pcb->ids) {
999 /*
1000 * We can get and set the status register
1001 * in 32-bit mode even on a 64-bit thread
1002 * because the high order bits are not
1003 * used on x86_64
1004 */
1005 if (thread_is_64bit_addr(thread)) {
1006 x86_debug_state64_t *ids = pcb->ids;
1007 ids->dr6 = dr6;
1008 } else { /* 32 bit thread */
1009 x86_debug_state32_t *ids = pcb->ids;
1010 ids->dr6 = (uint32_t) dr6;
1011 }
1012 }
1013 exc = EXC_BREAKPOINT;
1014 code = EXC_I386_SGL;
1015 break;
1016 }
1017 case T_INT3:
1018 #if CONFIG_DTRACE
1019 if (dtrace_user_probe(saved_state) == KERN_SUCCESS) {
1020 return; /* If it succeeds, we are done... */
1021 }
1022 #endif
1023 exc = EXC_BREAKPOINT;
1024 code = EXC_I386_BPT;
1025 break;
1026
1027 case T_OVERFLOW:
1028 exc = EXC_ARITHMETIC;
1029 code = EXC_I386_INTO;
1030 break;
1031
1032 case T_OUT_OF_BOUNDS:
1033 exc = EXC_SOFTWARE;
1034 code = EXC_I386_BOUND;
1035 break;
1036
1037 case T_INVALID_OPCODE:
1038 if (fpUDflt(rip) == 1) {
1039 exc = EXC_BAD_INSTRUCTION;
1040 code = EXC_I386_INVOP;
1041 }
1042 break;
1043
1044 case T_NO_FPU:
1045 fpnoextflt();
1046 break;
1047
1048 case T_FPU_FAULT:
1049 fpextovrflt();
1050 /*
1051 * Raise exception.
1052 */
1053 exc = EXC_BAD_ACCESS;
1054 code = VM_PROT_READ | VM_PROT_EXECUTE;
1055 subcode = 0;
1056 break;
1057
1058 case T_INVALID_TSS: /* invalid TSS == iret with NT flag set */
1059 exc = EXC_BAD_INSTRUCTION;
1060 code = EXC_I386_INVTSSFLT;
1061 subcode = err;
1062 break;
1063
1064 case T_SEGMENT_NOT_PRESENT:
1065 exc = EXC_BAD_INSTRUCTION;
1066 code = EXC_I386_SEGNPFLT;
1067 subcode = err;
1068 break;
1069
1070 case T_STACK_FAULT:
1071 exc = EXC_BAD_INSTRUCTION;
1072 code = EXC_I386_STKFLT;
1073 subcode = err;
1074 break;
1075
1076 case T_GENERAL_PROTECTION:
1077 /*
1078 * There's a wide range of circumstances which generate this
1079 * class of exception. From user-space, many involve bad
1080 * addresses (such as a non-canonical 64-bit address).
1081 * So we map this to EXC_BAD_ACCESS (and thereby SIGSEGV).
1082 * The trouble is cr2 doesn't contain the faulting address;
1083 * we'd need to decode the faulting instruction to really
1084 * determine this. We'll leave that to debuggers.
1085 * However, attempted execution of privileged instructions
1086 * (e.g. cli) also generate GP faults and so we map these to
1087 * to EXC_BAD_ACCESS (and thence SIGSEGV) also - rather than
1088 * EXC_BAD_INSTRUCTION which is more accurate. We just can't
1089 * win!
1090 */
1091 exc = EXC_BAD_ACCESS;
1092 code = EXC_I386_GPFLT;
1093 subcode = err;
1094 break;
1095
1096 case T_PAGE_FAULT:
1097 {
1098 prot = VM_PROT_READ;
1099
1100 if (err & T_PF_WRITE) {
1101 prot |= VM_PROT_WRITE;
1102 }
1103 if (__improbable(err & T_PF_EXECUTE)) {
1104 prot |= VM_PROT_EXECUTE;
1105 }
1106 #if DEVELOPMENT || DEBUG
1107 uint32_t fsig = 0;
1108 fsig = thread_fpsimd_hash(thread);
1109 #if DEBUG
1110 fsigs[0] = fsig;
1111 #endif
1112 #endif
1113 kret = vm_fault(thread->map,
1114 vaddr,
1115 prot, FALSE, VM_KERN_MEMORY_NONE,
1116 THREAD_ABORTSAFE, NULL, 0);
1117 #if DEVELOPMENT || DEBUG
1118 if (fsig) {
1119 uint32_t fsig2 = thread_fpsimd_hash(thread);
1120 #if DEBUG
1121 fsigcs++;
1122 fsigs[1] = fsig2;
1123 #endif
1124 if (fsig != fsig2) {
1125 panic("FP/SIMD state hash mismatch across fault thread: %p 0x%x->0x%x", thread, fsig, fsig2);
1126 }
1127 } else {
1128 #if DEBUG
1129 fsigns++;
1130 #endif
1131 }
1132 #endif
1133 if (__probable((kret == KERN_SUCCESS) || (kret == KERN_ABORTED))) {
1134 break;
1135 } else if (__improbable(kret == KERN_FAILURE)) {
1136 /*
1137 * For a user trap, vm_fault() should never return KERN_FAILURE.
1138 * If it does, we're leaking preemption disables somewhere in the kernel.
1139 */
1140 panic("vm_fault() KERN_FAILURE from user fault on thread %p", thread);
1141 }
1142
1143 /* PAL debug hook (empty on x86) */
1144 pal_dbg_page_fault(thread, vaddr, kret);
1145 exc = EXC_BAD_ACCESS;
1146 code = kret;
1147 subcode = vaddr;
1148 }
1149 break;
1150
1151 case T_SSE_FLOAT_ERROR:
1152 fpSSEexterrflt();
1153 exc = EXC_ARITHMETIC;
1154 code = EXC_I386_SSEEXTERR;
1155 subcode = ((struct x86_fx_thread_state *)thread->machine.ifps)->fx_MXCSR;
1156 break;
1157
1158
1159 case T_FLOATING_POINT_ERROR:
1160 fpexterrflt();
1161 exc = EXC_ARITHMETIC;
1162 code = EXC_I386_EXTERR;
1163 subcode = ((struct x86_fx_thread_state *)thread->machine.ifps)->fx_status;
1164 break;
1165
1166 case T_DTRACE_RET:
1167 #if CONFIG_DTRACE
1168 if (dtrace_user_probe(saved_state) == KERN_SUCCESS) {
1169 return; /* If it succeeds, we are done... */
1170 }
1171 #endif
1172 /*
1173 * If we get an INT 0x7f when we do not expect to,
1174 * treat it as an illegal instruction
1175 */
1176 exc = EXC_BAD_INSTRUCTION;
1177 code = EXC_I386_INVOP;
1178 break;
1179
1180 default:
1181 panic("Unexpected user trap, type %d", type);
1182 }
1183
1184 if (exc != 0) {
1185 uint16_t cs;
1186 boolean_t intrs;
1187
1188 if (is_saved_state64(saved_state)) {
1189 cs = saved_state64(saved_state)->isf.cs;
1190 } else {
1191 cs = saved_state32(saved_state)->cs;
1192 }
1193
1194 if (last_branch_support_enabled) {
1195 intrs = ml_set_interrupts_enabled(FALSE);
1196 /*
1197 * This is a bit racy (it's possible for this thread to migrate to another CPU, then
1198 * migrate back, but that seems rather rare in practice), but good enough to ensure
1199 * the LBRs are saved before proceeding with exception/signal dispatch.
1200 */
1201 if (current_cpu == cpu_number()) {
1202 i386_lbr_synch(thread);
1203 }
1204 ml_set_interrupts_enabled(intrs);
1205 }
1206
1207 /*
1208 * Do not try to copyin from the instruction stream if the page fault was due
1209 * to an access to rip and was unhandled.
1210 * Do not deal with cases when %cs != USER[64]_CS
1211 * And of course there's no need to copy the instruction stream if the boot-arg
1212 * was set to 0.
1213 */
1214 if (insn_copyin_count > 0 &&
1215 (cs == USER64_CS || cs == USER_CS) && (type != T_PAGE_FAULT || vaddr != rip)) {
1216 #if DEVELOPMENT || DEBUG
1217 copy_instruction_stream(thread, rip, type, inspect_cacheline);
1218 #else
1219 copy_instruction_stream(thread, rip, type);
1220 #endif
1221 }
1222
1223 #if DEVELOPMENT || DEBUG
1224 if (traptrace_index != TRAPTRACE_INVALID_INDEX) {
1225 traptrace_end(traptrace_index, mach_absolute_time());
1226 }
1227 #endif
1228 /*
1229 * Note: Codepaths that directly return from user_trap() have pending
1230 * ASTs processed in locore
1231 */
1232 i386_exception(exc, code, subcode);
1233 /* NOTREACHED */
1234 } else {
1235 #if DEVELOPMENT || DEBUG
1236 if (traptrace_index != TRAPTRACE_INVALID_INDEX) {
1237 traptrace_end(traptrace_index, mach_absolute_time());
1238 }
1239 #endif
1240 }
1241 }
1242
1243 /*
1244 * Copyin up to x86_INSTRUCTION_STATE_MAX_INSN_BYTES bytes from the page that includes `rip`,
1245 * ensuring that we stay on the same page, clipping the start or end, as needed.
1246 * Add the clipped amount back at the start or end, depending on where it fits.
1247 * Consult the variable populated by the boot-arg `insn_capcnt'
1248 */
1249 static __attribute__((noinline)) void
1250 copy_instruction_stream(thread_t thread, uint64_t rip, int __unused trap_code
1251 #if DEVELOPMENT || DEBUG
1252 , bool inspect_cacheline
1253 #endif
1254 )
1255 {
1256 #if x86_INSTRUCTION_STATE_MAX_INSN_BYTES > 4096
1257 #error x86_INSTRUCTION_STATE_MAX_INSN_BYTES cannot exceed a page in size.
1258 #endif
1259 pcb_t pcb = THREAD_TO_PCB(thread);
1260 vm_map_offset_t pagemask = ~vm_map_page_mask(current_map());
1261 vm_map_offset_t rip_page = rip & pagemask;
1262 vm_map_offset_t start_addr;
1263 vm_map_offset_t insn_offset;
1264 vm_map_offset_t end_addr = rip + (insn_copyin_count / 2);
1265 void *stack_buffer;
1266 int copyin_err = 0;
1267 #if defined(MACH_BSD) && (DEVELOPMENT || DEBUG)
1268 void *procname;
1269 #endif
1270
1271 #if DEVELOPMENT || DEBUG
1272 assert(insn_copyin_count <= x86_INSTRUCTION_STATE_MAX_INSN_BYTES);
1273 #else
1274 if (insn_copyin_count > x86_INSTRUCTION_STATE_MAX_INSN_BYTES ||
1275 insn_copyin_count < 64 /* CACHELINE_SIZE */) {
1276 return;
1277 }
1278 #endif
1279
1280 #pragma clang diagnostic push
1281 #pragma clang diagnostic ignored "-Walloca"
1282 stack_buffer = __builtin_alloca(insn_copyin_count);
1283 #pragma clang diagnostic pop
1284
1285 if (rip >= (insn_copyin_count / 2)) {
1286 start_addr = rip - (insn_copyin_count / 2);
1287 } else {
1288 start_addr = 0;
1289 }
1290
1291 if (start_addr < rip_page) {
1292 insn_offset = (insn_copyin_count / 2) - (rip_page - start_addr);
1293 end_addr += (rip_page - start_addr);
1294 start_addr = rip_page;
1295 } else if (end_addr >= (rip_page + (~pagemask + 1))) {
1296 start_addr -= (end_addr - (rip_page + (~pagemask + 1))); /* Adjust start address backward */
1297 /* Adjust instruction offset due to start address change */
1298 insn_offset = (insn_copyin_count / 2) + (end_addr - (rip_page + (~pagemask + 1)));
1299 end_addr = rip_page + (~pagemask + 1); /* clip to the start of the next page (non-inclusive */
1300 } else {
1301 insn_offset = insn_copyin_count / 2;
1302 }
1303
1304 disable_preemption(); /* Prevent copyin from faulting in the instruction stream */
1305 if (
1306 #if DEVELOPMENT || DEBUG
1307 (insnstream_force_cacheline_mismatch < 2) &&
1308 #endif
1309 ((end_addr > start_addr) && (copyin_err = copyin(start_addr, stack_buffer, end_addr - start_addr)) == 0)) {
1310 enable_preemption();
1311
1312 if (pcb->insn_state == 0) {
1313 pcb->insn_state = kalloc(sizeof(x86_instruction_state_t));
1314 }
1315
1316 if (pcb->insn_state != 0) {
1317 bcopy(stack_buffer, pcb->insn_state->insn_bytes, end_addr - start_addr);
1318 bzero(&pcb->insn_state->insn_bytes[end_addr - start_addr],
1319 insn_copyin_count - (end_addr - start_addr));
1320
1321 pcb->insn_state->insn_stream_valid_bytes = (int)(end_addr - start_addr);
1322 pcb->insn_state->insn_offset = (int)insn_offset;
1323
1324 #if DEVELOPMENT || DEBUG
1325 /* Now try to validate the cacheline we read at early-fault time matches the code
1326 * copied in. Before we do that, we have to make sure the buffer contains a valid
1327 * cacheline by looking for the 2 sentinel values written in the event the cacheline
1328 * could not be copied.
1329 */
1330 #define CACHELINE_DATA_NOT_PRESENT 0xdeadc0debeefcafeULL
1331 #define CACHELINE_MASK (CACHELINE_SIZE - 1)
1332
1333 if (inspect_cacheline &&
1334 (*(uint64_t *)(uintptr_t)&pcb->insn_cacheline[0] != CACHELINE_DATA_NOT_PRESENT &&
1335 *(uint64_t *)(uintptr_t)&pcb->insn_cacheline[8] != CACHELINE_DATA_NOT_PRESENT)) {
1336 /*
1337 * The position of the cacheline in the instruction buffer is at offset
1338 * insn_offset - (rip & CACHELINE_MASK)
1339 */
1340 if (__improbable((rip & CACHELINE_MASK) > insn_offset)) {
1341 printf("thread %p code cacheline @ %p clipped wrt copied-in code (offset %d)\n",
1342 thread, (void *)(rip & ~CACHELINE_MASK), (int)(rip & CACHELINE_MASK));
1343 } else if (bcmp(&pcb->insn_state->insn_bytes[insn_offset - (rip & CACHELINE_MASK)],
1344 &pcb->insn_cacheline[0], CACHELINE_SIZE) != 0
1345 || insnstream_force_cacheline_mismatch
1346 ) {
1347 #if x86_INSTRUCTION_STATE_CACHELINE_SIZE != CACHELINE_SIZE
1348 #error cacheline size mismatch
1349 #endif
1350 bcopy(&pcb->insn_cacheline[0], &pcb->insn_state->insn_cacheline[0],
1351 x86_INSTRUCTION_STATE_CACHELINE_SIZE);
1352 /* Mark the instruction stream as being out-of-synch */
1353 pcb->insn_state->out_of_synch = 1;
1354
1355 printf("thread %p code cacheline @ %p mismatches with copied-in code [trap 0x%x]\n",
1356 thread, (void *)(rip & ~CACHELINE_MASK), trap_code);
1357 for (int i = 0; i < 8; i++) {
1358 printf("\t[%d] cl=0x%08llx vs. ci=0x%08llx\n", i, *(uint64_t *)(uintptr_t)&pcb->insn_cacheline[i * 8],
1359 *(uint64_t *)(uintptr_t)&pcb->insn_state->insn_bytes[(i * 8) + insn_offset - (rip & CACHELINE_MASK)]);
1360 }
1361 if (panic_on_cacheline_mismatch) {
1362 panic("Cacheline mismatch while processing unhandled exception.");
1363 }
1364 } else {
1365 printf("thread %p code cacheline @ %p DOES match with copied-in code\n",
1366 thread, (void *)(rip & ~CACHELINE_MASK));
1367 pcb->insn_state->out_of_synch = 0;
1368 }
1369 } else if (inspect_cacheline) {
1370 printf("thread %p could not capture code cacheline at fault IP %p [offset %d]\n",
1371 (void *)thread, (void *)rip, (int)(insn_offset - (rip & CACHELINE_MASK)));
1372 pcb->insn_state->out_of_synch = 0;
1373 }
1374 #else
1375 pcb->insn_state->out_of_synch = 0;
1376 #endif /* DEVELOPMENT || DEBUG */
1377
1378 #if defined(MACH_BSD) && (DEVELOPMENT || DEBUG)
1379 if (panic_on_trap_procname[0] != 0) {
1380 char procnamebuf[65] = {0};
1381
1382 if (thread->task->bsd_info != NULL) {
1383 procname = proc_name_address(thread->task->bsd_info);
1384 strlcpy(procnamebuf, procname, sizeof(procnamebuf));
1385
1386 if (strcasecmp(panic_on_trap_procname, procnamebuf) == 0 &&
1387 ((1U << trap_code) & panic_on_trap_mask) != 0) {
1388 panic("Panic requested on trap type 0x%x for process `%s'", trap_code,
1389 panic_on_trap_procname);
1390 /*NORETURN*/
1391 }
1392 }
1393 }
1394 #endif /* MACH_BSD && (DEVELOPMENT || DEBUG) */
1395 }
1396 } else {
1397 enable_preemption();
1398
1399 pcb->insn_state_copyin_failure_errorcode = copyin_err;
1400 #if DEVELOPMENT || DEBUG
1401 if (inspect_cacheline && pcb->insn_state == 0) {
1402 pcb->insn_state = kalloc(sizeof(x86_instruction_state_t));
1403 }
1404 if (pcb->insn_state != 0) {
1405 pcb->insn_state->insn_stream_valid_bytes = 0;
1406 pcb->insn_state->insn_offset = 0;
1407
1408 if (inspect_cacheline &&
1409 (*(uint64_t *)(uintptr_t)&pcb->insn_cacheline[0] != CACHELINE_DATA_NOT_PRESENT &&
1410 *(uint64_t *)(uintptr_t)&pcb->insn_cacheline[8] != CACHELINE_DATA_NOT_PRESENT)) {
1411 /*
1412 * We can still copy the cacheline into the instruction state structure
1413 * if it contains valid data
1414 */
1415 pcb->insn_state->out_of_synch = 1;
1416 bcopy(&pcb->insn_cacheline[0], &pcb->insn_state->insn_cacheline[0],
1417 x86_INSTRUCTION_STATE_CACHELINE_SIZE);
1418 }
1419 }
1420 #endif /* DEVELOPMENT || DEBUG */
1421 }
1422 }
1423
1424 /*
1425 * Handle exceptions for i386.
1426 *
1427 * If we are an AT bus machine, we must turn off the AST for a
1428 * delayed floating-point exception.
1429 *
1430 * If we are providing floating-point emulation, we may have
1431 * to retrieve the real register values from the floating point
1432 * emulator.
1433 */
1434 void
1435 i386_exception(
1436 int exc,
1437 mach_exception_code_t code,
1438 mach_exception_subcode_t subcode)
1439 {
1440 mach_exception_data_type_t codes[EXCEPTION_CODE_MAX];
1441
1442 DEBUG_KPRINT_SYSCALL_MACH("i386_exception: exc=%d code=0x%llx subcode=0x%llx\n",
1443 exc, code, subcode);
1444 codes[0] = code; /* new exception interface */
1445 codes[1] = subcode;
1446 exception_triage(exc, codes, 2);
1447 /*NOTREACHED*/
1448 }
1449
1450
1451 /* Synchronize a thread's x86_kernel_state (if any) with the given
1452 * x86_saved_state_t obtained from the trap/IPI handler; called in
1453 * kernel_trap() prior to entering the debugger, and when receiving
1454 * an "MP_KDP" IPI. Called with null saved_state if an incoming IPI
1455 * was detected from the kernel while spinning with interrupts masked.
1456 */
1457
1458 void
1459 sync_iss_to_iks(x86_saved_state_t *saved_state)
1460 {
1461 struct x86_kernel_state *iks = NULL;
1462 vm_offset_t kstack;
1463 boolean_t record_active_regs = FALSE;
1464
1465 /* The PAL may have a special way to sync registers */
1466 if (saved_state && saved_state->flavor == THREAD_STATE_NONE) {
1467 pal_get_kern_regs( saved_state );
1468 }
1469
1470 if (current_thread() != NULL &&
1471 (kstack = current_thread()->kernel_stack) != 0) {
1472 x86_saved_state64_t *regs = saved_state64(saved_state);
1473
1474 iks = STACK_IKS(kstack);
1475
1476 /* Did we take the trap/interrupt in kernel mode? */
1477 if (saved_state == NULL || /* NULL => polling in kernel */
1478 regs == USER_REGS64(current_thread())) {
1479 record_active_regs = TRUE;
1480 } else {
1481 iks->k_rbx = regs->rbx;
1482 iks->k_rsp = regs->isf.rsp;
1483 iks->k_rbp = regs->rbp;
1484 iks->k_r12 = regs->r12;
1485 iks->k_r13 = regs->r13;
1486 iks->k_r14 = regs->r14;
1487 iks->k_r15 = regs->r15;
1488 iks->k_rip = regs->isf.rip;
1489 }
1490 }
1491
1492 if (record_active_regs == TRUE) {
1493 /* Show the trap handler path */
1494 __asm__ volatile ("movq %%rbx, %0" : "=m" (iks->k_rbx));
1495 __asm__ volatile ("movq %%rsp, %0" : "=m" (iks->k_rsp));
1496 __asm__ volatile ("movq %%rbp, %0" : "=m" (iks->k_rbp));
1497 __asm__ volatile ("movq %%r12, %0" : "=m" (iks->k_r12));
1498 __asm__ volatile ("movq %%r13, %0" : "=m" (iks->k_r13));
1499 __asm__ volatile ("movq %%r14, %0" : "=m" (iks->k_r14));
1500 __asm__ volatile ("movq %%r15, %0" : "=m" (iks->k_r15));
1501 /* "Current" instruction pointer */
1502 __asm__ volatile ("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:"
1503 : "=m" (iks->k_rip)
1504 :
1505 : "rax");
1506 }
1507 }
1508
1509 /*
1510 * This is used by the NMI interrupt handler (from mp.c) to
1511 * uncondtionally sync the trap handler context to the IKS
1512 * irrespective of whether the NMI was fielded in kernel
1513 * or user space.
1514 */
1515 void
1516 sync_iss_to_iks_unconditionally(__unused x86_saved_state_t *saved_state)
1517 {
1518 struct x86_kernel_state *iks;
1519 vm_offset_t kstack;
1520
1521 if ((kstack = current_thread()->kernel_stack) != 0) {
1522 iks = STACK_IKS(kstack);
1523 /* Display the trap handler path */
1524 __asm__ volatile ("movq %%rbx, %0" : "=m" (iks->k_rbx));
1525 __asm__ volatile ("movq %%rsp, %0" : "=m" (iks->k_rsp));
1526 __asm__ volatile ("movq %%rbp, %0" : "=m" (iks->k_rbp));
1527 __asm__ volatile ("movq %%r12, %0" : "=m" (iks->k_r12));
1528 __asm__ volatile ("movq %%r13, %0" : "=m" (iks->k_r13));
1529 __asm__ volatile ("movq %%r14, %0" : "=m" (iks->k_r14));
1530 __asm__ volatile ("movq %%r15, %0" : "=m" (iks->k_r15));
1531 /* "Current" instruction pointer */
1532 __asm__ volatile ("leaq 1f(%%rip), %%rax; mov %%rax, %0\n1:" : "=m" (iks->k_rip)::"rax");
1533 }
1534 }
1535
1536 #if DEBUG
1537 #define TERI 1
1538 #endif
1539
1540 #if TERI
1541 extern void thread_exception_return_internal(void) __dead2;
1542
1543 void
1544 thread_exception_return(void)
1545 {
1546 thread_t thread = current_thread();
1547 ml_set_interrupts_enabled(FALSE);
1548 if (thread_is_64bit_addr(thread) != task_has_64Bit_addr(thread->task)) {
1549 panic("Task/thread bitness mismatch %p %p, task: %d, thread: %d", thread, thread->task, thread_is_64bit_addr(thread), task_has_64Bit_addr(thread->task));
1550 }
1551
1552 if (thread_is_64bit_addr(thread)) {
1553 if ((gdt_desc_p(USER64_CS)->access & ACC_PL_U) == 0) {
1554 panic("64-GDT mismatch %p, descriptor: %p", thread, gdt_desc_p(USER64_CS));
1555 }
1556 } else {
1557 if ((gdt_desc_p(USER_CS)->access & ACC_PL_U) == 0) {
1558 panic("32-GDT mismatch %p, descriptor: %p", thread, gdt_desc_p(USER_CS));
1559 }
1560 }
1561 assert(get_preemption_level() == 0);
1562 thread_exception_return_internal();
1563 }
1564 #endif
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