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[apple/xnu.git] / osfmk / ppc / Firmware.s
1 /*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * The contents of this file constitute Original Code as defined in and
7 * are subject to the Apple Public Source License Version 1.1 (the
8 * "License"). You may not use this file except in compliance with the
9 * License. Please obtain a copy of the License at
10 * http://www.apple.com/publicsource and read it before using this file.
11 *
12 * This Original Code and all software distributed under the License are
13 * distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, EITHER
14 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
15 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT. Please see the
17 * License for the specific language governing rights and limitations
18 * under the License.
19 *
20 * @APPLE_LICENSE_HEADER_END@
21 */
22 /*
23 * @OSF_FREE_COPYRIGHT@
24 */
25 /*
26 * @APPLE_FREE_COPYRIGHT@
27 */
28
29 /*
30 Firmware.s
31
32 Handle things that should be treated as an extension of the hardware
33
34 Lovingly crafted by Bill Angell using traditional methods and only natural or recycled materials.
35 No animal products are used other than rendered otter bile and deep fried pork lard.
36
37 */
38
39 #include <cpus.h>
40 #include <ppc/asm.h>
41 #include <ppc/proc_reg.h>
42 #include <ppc/spec_reg.h>
43 #include <ppc/POWERMAC/mp/MPPlugIn.h>
44 #include <ppc/exception.h>
45 #include <mach/machine/vm_param.h>
46 #include <assym.s>
47
48
49 /*
50 * Here we generate the table of supported firmware calls
51 */
52
53
54
55 .data
56 .align 5 /* Line up on cache line */
57
58 .globl EXT(FWtable)
59
60 EXT(FWtable):
61
62 .globl CutTrace /* Let everyone know 'bout it */
63 .set CutTrace,(.-EXT(FWtable))/4|0x80000000 /* Call number for CutTrace */
64 .long callUnimp /* This was already handled in lowmem_vectors */
65
66 #include <ppc/FirmwareCalls.h>
67
68 .set EXT(FirmwareCnt), (.-EXT(FWtable))/4 /* Get the top number */
69
70 .text
71
72 #define SIMPLESCC 1
73 #define NOTQUITEASSIMPLE 1
74 /*
75 * This routine handles the firmware call routine. It must be entered with IR and DR off,
76 * interruptions disabled, and in supervisor state.
77 *
78 * When we enter, we expect R0 to have call number, and LR
79 * to point to the return. Also, all registers saved in savearea in R13.
80 * R3 is as passed in by the user. All others must be gotten from the save area
81 */
82
83 ENTRY(FirmwareCall, TAG_NO_FRAME_USED)
84
85 rlwinm r1,r0,2,1,29 /* Clear out bit 0 and multiply by 4 */
86 lis r12,HIGH_ADDR(EXT(FWtable)) /* Get the high part of the firmware call table */
87 cmplwi r1,EXT(FirmwareCnt)*4 /* Is it a valid firmware call number */
88 mflr r11 /* Save the return */
89 ori r12,r12,LOW_ADDR(EXT(FWtable)) /* Now the low part */
90 ble+ goodCall /* Yeah, it is... */
91
92 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
93 blr /* Return for errors... */
94
95 goodCall: mfsprg r10,0 /* Make sure about the per_proc block */
96 lwzx r1,r1,r12 /* Pick up the address of the routine */
97 lwz r4,saver4(r13) /* Pass in caller's R4 */
98 lwz r5,saver5(r13) /* Pass in caller's R5 */
99 rlwinm. r1,r1,0,0,29 /* Make sure the flag bits are clear */
100 stw r11,PP_TEMPWORK1(r10) /* Save our return point */
101
102 mtlr r1 /* Put it in the LR */
103 beq- callUnimp /* This one was unimplimented... */
104
105 blrl /* Call the routine... */
106
107 mfsprg r10,0 /* Make sure about the per_proc again */
108 stw r3,saver3(r13) /* Pass back the return code to caller */
109 lwz r11,PP_TEMPWORK1(r10) /* Get our return point */
110 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
111 mtlr r11 /* Set the return */
112 blr /* Bye, dudes... */
113
114 callUnimp: lwz r11,PP_TEMPWORK1(r10) /* Restore the return address */
115 li r3,T_SYSTEM_CALL /* Tell the vector handler that we know nothing */
116 mtlr r11 /* Restore the LR */
117 blr /* Return for errors... */
118
119 /*
120 * This routine is used to store using a real address. It stores parmeter1 at parameter2.
121 */
122
123 ENTRY(StoreReal, TAG_NO_FRAME_USED)
124
125 lis r0,HIGH_ADDR(StoreRealCall) /* Get the top part of the SC number */
126 ori r0,r0,LOW_ADDR(StoreRealCall) /* and the bottom part */
127 sc /* Do it to it */
128 blr /* Bye bye, Birdie... */
129
130 ENTRY(StoreRealLL, TAG_NO_FRAME_USED)
131
132 stw r3,0(r4) /* Store the word */
133 blr /* Leave... */
134
135 /*
136 * This routine is used to clear a range of physical pages.
137 */
138
139 ENTRY(ClearReal, TAG_NO_FRAME_USED)
140
141 lis r0,HIGH_ADDR(ClearRealCall) /* Get the top part of the SC number */
142 ori r0,r0,LOW_ADDR(ClearRealCall) /* and the bottom part */
143 sc /* Do it to it */
144 blr /* Bye bye, Birdie... */
145
146 ENTRY(ClearRealLL, TAG_NO_FRAME_USED)
147
148 /*
149 * We take the first parameter as a physical address. The second is the length in bytes.
150 * Being crazy, I'll round the address down, and the length up. We could end up clearing
151 * an extra page at the start and one at the end, but we don't really care. If someone
152 * is stupid enough to give me unaligned addresses and lengths, I am just arrogant enough
153 * to take them at their word and to hell with them.
154 */
155
156 neg r5,r3 /* Negate the address */
157 addi r4,r4,4095 /* Round length up */
158 rlwinm r5,r5,0,20,31 /* Save extra length */
159 rlwinm r3,r3,0,0,19 /* Round the page on down */
160 add r4,r4,r5 /* Add up all extra lengths */
161 li r6,32 /* Get a displacement */
162 rlwinm r4,r4,0,0,19 /* Round the length back down */
163
164 clrloop: subi r4,r4,32 /* Back off a cache line */
165 dcbz 0,r3 /* Do the even line */
166 sub. r4,r4,r6 /* Back off a second time (we only do this to generate a CR */
167 dcbz r6,r3 /* Clear the even line */
168 addi r3,r3,64 /* Move up to every other line */
169 bgt+ clrloop /* Go until we've done it all... */
170
171 blr /* Leave... */
172 /*
173 * This routine will read in 32 byte of real storage.
174 */
175
176 ENTRY(ReadReal, TAG_NO_FRAME_USED)
177
178 mfmsr r0 /* Get the MSR */
179 rlwinm r5,r0,0,28,26 /* Clear DR bit */
180 rlwinm r5,r5,0,17,15 /* Clear EE bit */
181 mtmsr r5 /* Disable EE and DR */
182 isync /* Just make sure about it */
183
184 lwz r5,0(r3) /* Get word 0 */
185 lwz r6,4(r3) /* Get word 1 */
186 lwz r7,8(r3) /* Get word 2 */
187 lwz r8,12(r3) /* Get word 3 */
188 rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
189 lwz r9,16(r3) /* Get word 4 */
190 lwz r10,20(r3) /* Get word 5 */
191 rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
192 lwz r11,24(r3) /* Get word 6 */
193 lwz r12,28(r3) /* Get word 7 */
194
195 mtmsr r0 /* Restore original machine state */
196 isync /* Insure goodness */
197
198 stw r5,0(r4) /* Set word 0 */
199 stw r6,4(r4) /* Set word 1 */
200 stw r7,8(r4) /* Set word 2 */
201 stw r8,12(r4) /* Set word 3 */
202 stw r9,16(r4) /* Set word 4 */
203 stw r10,20(r4) /* Set word 5 */
204 stw r11,24(r4) /* Set word 6 */
205 stw r12,28(r4) /* Set word 7 */
206
207 blr
208
209
210 /*
211 * This routine is used to load all 4 DBATs.
212 */
213
214 ENTRY(LoadDBATs, TAG_NO_FRAME_USED)
215
216 lis r0,HIGH_ADDR(LoadDBATsCall) /* Top half of LoadDBATsCall firmware call number */
217 ori r0,r0,LOW_ADDR(LoadDBATsCall) /* Bottom half */
218 sc /* Do it to it */
219
220 blr /* Bye bye, Birdie... */
221
222 ENTRY(xLoadDBATsLL, TAG_NO_FRAME_USED)
223
224 lwz r4,0(r3) /* Get DBAT 0 high */
225 lwz r5,4(r3) /* Get DBAT 0 low */
226 lwz r6,8(r3) /* Get DBAT 1 high */
227 lwz r7,12(r3) /* Get DBAT 1 low */
228 lwz r8,16(r3) /* Get DBAT 2 high */
229 lwz r9,20(r3) /* Get DBAT 2 low */
230 lwz r10,24(r3) /* Get DBAT 3 high */
231 lwz r11,28(r3) /* Get DBAT 3 low */
232
233 sync /* Common decency and the state law require that you wash your hands */
234 mtdbatu 0,r4 /* Load DBAT 0 high */
235 mtdbatl 0,r5 /* Load DBAT 0 low */
236 mtdbatu 1,r6 /* Load DBAT 1 high */
237 mtdbatl 1,r7 /* Load DBAT 1 low */
238 mtdbatu 2,r8 /* Load DBAT 2 high */
239 mtdbatl 2,r9 /* Load DBAT 2 low */
240 mtdbatu 3,r10 /* Load DBAT 3 high */
241 mtdbatl 3,r11 /* Load DBAT 3 low */
242 sync /* Make sure it's done */
243 isync /* Toss out anything new */
244
245 blr /* Leave... */
246
247 /*
248 * This routine is used to load all 4 IBATs.
249 */
250
251 ENTRY(LoadIBATs, TAG_NO_FRAME_USED)
252
253 lis r0,HIGH_ADDR(LoadIBATsCall) /* Top half of LoadIBATsCall firmware call number */
254 ori r0,r0,LOW_ADDR(LoadIBATsCall) /* Bottom half */
255 sc /* Do it to it */
256 blr /* Bye bye, Birdie... */
257
258 ENTRY(xLoadIBATsLL, TAG_NO_FRAME_USED)
259
260 lwz r4,0(r3) /* Get IBAT 0 high */
261 lwz r5,4(r3) /* Get IBAT 0 low */
262 lwz r6,8(r3) /* Get IBAT 1 high */
263 lwz r7,12(r3) /* Get IBAT 1 low */
264 lwz r8,16(r3) /* Get IBAT 2 high */
265 lwz r9,20(r3) /* Get IBAT 2 low */
266 lwz r10,24(r3) /* Get IBAT 3 high */
267 lwz r11,28(r3) /* Get IBAT 3 low */
268
269 sync /* Common decency and the state law require that you wash your hands */
270 mtibatu 0,r4 /* Load IBAT 0 high */
271 mtibatl 0,r5 /* Load IBAT 0 low */
272 mtibatu 1,r6 /* Load IBAT 1 high */
273 mtibatl 1,r7 /* Load IBAT 1 low */
274 mtibatu 2,r8 /* Load IBAT 2 high */
275 mtibatl 2,r9 /* Load IBAT 2 low */
276 mtibatu 3,r10 /* Load IBAT 3 high */
277 mtibatl 3,r11 /* Load IBAT 3 low */
278 sync /* Make sure it's done */
279 isync /* Toss out anything new */
280
281 blr /* Leave... */
282
283
284 /*
285 * This is the glue to call the CutTrace firmware call
286 */
287
288 ENTRY(dbgTrace, TAG_NO_FRAME_USED)
289
290 lis r0,HIGH_ADDR(CutTrace) /* Top half of CreateFakeIO firmware call number */
291 ori r0,r0,LOW_ADDR(CutTrace) /* Bottom half */
292 sc /* Do it to it */
293 blr /* Bye bye, Birdie... */
294
295 /*
296 * This is the glue to create a fake I/O interruption
297 */
298
299 ENTRY(CreateFakeIO, TAG_NO_FRAME_USED)
300
301 lis r0,HIGH_ADDR(CreateFakeIOCall) /* Top half of CreateFakeIO firmware call number */
302 ori r0,r0,LOW_ADDR(CreateFakeIOCall) /* Bottom half */
303 sc /* Do it to it */
304 blr /* Bye bye, Birdie... */
305
306 /*
307 * This is the glue to create a fake Dec interruption
308 */
309
310 ENTRY(CreateFakeDEC, TAG_NO_FRAME_USED)
311
312 #if 0
313 mflr r4 ; (TEST/DEBUG)
314 bl EXT(ml_sense_nmi) ; (TEST/DEBUG)
315 mtlr r4 ; (TEST/DEBUG)
316 #endif
317 lis r0,HIGH_ADDR(CreateFakeDECCall) /* Top half of CreateFakeDEC firmware call number */
318 ori r0,r0,LOW_ADDR(CreateFakeDECCall) /* Bottom half */
319 sc /* Do it to it */
320 blr /* Bye bye, Birdie... */
321
322
323 /*
324 * This is the glue to create a shutdown context
325 */
326
327 ENTRY(CreateShutdownCTX, TAG_NO_FRAME_USED)
328
329 lis r0,HIGH_ADDR(CreateShutdownCTXCall) /* Top half of CreateFakeIO firmware call number */
330 ori r0,r0,LOW_ADDR(CreateShutdownCTXCall) /* Bottom half */
331 sc /* Do it to it */
332 blr /* Bye bye, Birdie... */
333
334 /*
335 * This is the glue to choke system
336 */
337
338 ENTRY(ChokeSys, TAG_NO_FRAME_USED)
339
340 lis r0,HIGH_ADDR(Choke) /* Top half of Choke firmware call number */
341 ori r0,r0,LOW_ADDR(Choke) /* Bottom half */
342 sc /* Do it to it */
343 blr /* Bye bye, Birdie... */
344
345 /*
346 * Used to initialize the SCC for debugging output
347 */
348
349
350 ENTRY(fwSCCinit, TAG_NO_FRAME_USED)
351
352 mfmsr r8 /* Save the MSR */
353 mr. r3,r3 /* See if printer or modem */
354 rlwinm r12,r8,0,28,25 /* Turn off translation */
355 lis r10,0xF301 /* Set the top part */
356 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
357 #if 0
358 mtmsr r12 /* Smash the MSR */
359 isync /* Make it clean */
360 #endif
361
362 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
363 beq+ fwSCCprnt /* It sure are... */
364 ori r10,r10,0x0002 /* Move it over to the modem port */
365
366 fwSCCprnt: dcbf 0,r10 /* Insure it is out */
367 sync
368 eieio
369 dcbi 0,r10 /* Toss it */
370 sync
371
372
373 li r7,0x09 /* Set the register */
374 stb r7,0(r10) /* Set the register */
375 dcbf 0,r10 /* Force it out */
376 sync /* Make sure it's out there */
377 dcbi 0,r10
378 eieio
379
380 li r7,0x80 /* Reset channel A */
381 stb r7,0(r10) /* Set the register */
382 dcbf 0,r10 /* Force it out */
383 sync /* Make sure it's out there */
384 dcbi 0,r10
385 eieio
386
387 li r7,0x04 /* Set the register */
388 stb r7,0(r10) /* Set the register */
389 dcbf 0,r10 /* Force it out */
390 sync /* Make sure it's out there */
391 dcbi 0,r10
392 eieio
393
394 li r7,0x44 /* x16 clock, 1 stop bit */
395 stb r7,0(r10) /* Set the register */
396 dcbf 0,r10 /* Force it out */
397 sync /* Make sure it's out there */
398 dcbi 0,r10
399 eieio
400
401 li r7,0x03 /* Set the register */
402 stb r7,0(r10) /* Set the register */
403 dcbf 0,r10 /* Force it out */
404 sync /* Make sure it's out there */
405 dcbi 0,r10
406 eieio
407
408 li r7,0xC0 /* 8 bits per char */
409 stb r7,0(r10) /* Set the register */
410 dcbf 0,r10 /* Force it out */
411 sync /* Make sure it's out there */
412 dcbi 0,r10
413 eieio
414
415 li r7,0x05 /* Set the register */
416 stb r7,0(r10) /* Set the register */
417 dcbf 0,r10 /* Force it out */
418 sync /* Make sure it's out there */
419 dcbi 0,r10
420 eieio
421
422 li r7,0xE2 /* DTR mode, 8bit/char */
423 stb r7,0(r10) /* Set the register */
424 dcbf 0,r10 /* Force it out */
425 sync /* Make sure it's out there */
426 dcbi 0,r10
427 eieio
428
429 li r7,0x02 /* Set the register */
430 stb r7,0(r10) /* Set the register */
431 dcbf 0,r10 /* Force it out */
432 sync /* Make sure it's out there */
433 dcbi 0,r10
434 eieio
435
436 li r7,0x00 /* Vector 0 */
437 stb r7,0(r10) /* Set the register */
438 dcbf 0,r10 /* Force it out */
439 sync /* Make sure it's out there */
440 dcbi 0,r10
441 eieio
442
443 li r7,0x0A /* Set the register */
444 stb r7,0(r10) /* Set the register */
445 dcbf 0,r10 /* Force it out */
446 sync /* Make sure it's out there */
447 dcbi 0,r10
448 eieio
449
450 li r7,0x00 /* Clear misc controls */
451 stb r7,0(r10) /* Set the register */
452 dcbf 0,r10 /* Force it out */
453 sync /* Make sure it's out there */
454 dcbi 0,r10
455 eieio
456
457 li r7,0x0B /* Set the register */
458 stb r7,0(r10) /* Set the register */
459 dcbf 0,r10 /* Force it out */
460 sync /* Make sure it's out there */
461 dcbi 0,r10
462 eieio
463
464 li r7,0x50 /* B/R gen T/R */
465 stb r7,0(r10) /* Set the register */
466 dcbf 0,r10 /* Force it out */
467 sync /* Make sure it's out there */
468 dcbi 0,r10
469 eieio
470
471 li r7,0x0C /* Set the register */
472 stb r7,0(r10) /* Set the register */
473 dcbf 0,r10 /* Force it out */
474 sync /* Make sure it's out there */
475 dcbi 0,r10
476 eieio
477
478 li r7,0x0A /* 9600 baud low */
479 stb r7,0(r10) /* Set the register */
480 dcbf 0,r10 /* Force it out */
481 sync /* Make sure it's out there */
482 dcbi 0,r10
483 eieio
484
485 li r7,0x0D /* Set the register */
486 stb r7,0(r10) /* Set the register */
487 dcbf 0,r10 /* Force it out */
488 sync /* Make sure it's out there */
489 dcbi 0,r10
490 eieio
491
492 li r7,0x00 /* 9600 baud high */
493 stb r7,0(r10) /* Set the register */
494 dcbf 0,r10 /* Force it out */
495 sync /* Make sure it's out there */
496 dcbi 0,r10
497 eieio
498
499 li r7,0x03 /* Set the register */
500 stb r7,0(r10) /* Set the register */
501 dcbf 0,r10 /* Force it out */
502 sync /* Make sure it's out there */
503 dcbi 0,r10
504 eieio
505
506 li r7,0xC1 /* 8 bits/char, Rx enable */
507 stb r7,0(r10) /* Set the register */
508 dcbf 0,r10 /* Force it out */
509 sync /* Make sure it's out there */
510 dcbi 0,r10
511 eieio
512
513 li r7,0x05 /* Set the register */
514 stb r7,0(r10) /* Set the register */
515 dcbf 0,r10 /* Force it out */
516 sync /* Make sure it's out there */
517 dcbi 0,r10
518 eieio
519
520 li r7,0xEA /* 8 bits/char, Tx enable */
521 stb r7,0(r10) /* Set the register */
522 dcbf 0,r10 /* Force it out */
523 sync /* Make sure it's out there */
524 dcbi 0,r10
525 eieio
526
527 li r7,0x0E /* Set the register */
528 stb r7,0(r10) /* Set the register */
529 dcbf 0,r10 /* Force it out */
530 sync /* Make sure it's out there */
531 dcbi 0,r10
532 eieio
533
534 li r7,0x01 /* BR rate gen enable */
535 stb r7,0(r10) /* Set the register */
536 dcbf 0,r10 /* Force it out */
537 sync /* Make sure it's out there */
538 dcbi 0,r10
539 eieio
540
541 li r7,0x0F /* Set the register */
542 stb r7,0(r10) /* Set the register */
543 dcbf 0,r10 /* Force it out */
544 sync /* Make sure it's out there */
545 dcbi 0,r10
546 eieio
547
548 li r7,0x00 /* ints off */
549 stb r7,0(r10) /* Set the register */
550 dcbf 0,r10 /* Force it out */
551 sync /* Make sure it's out there */
552 dcbi 0,r10
553 eieio
554
555 li r7,0x10 /* Reset ext/stat ints */
556 stb r7,0(r10) /* Set the register */
557 dcbf 0,r10 /* Force it out */
558 sync /* Make sure it's out there */
559 dcbi 0,r10
560 eieio
561
562 li r7,0x10 /* Reset ext/stat ints */
563 stb r7,0(r10) /* Set the register */
564 dcbf 0,r10 /* Force it out */
565 sync /* Make sure it's out there */
566 dcbi 0,r10
567 eieio
568
569 li r7,0x01 /* Set the register */
570 stb r7,0(r10) /* Set the register */
571 dcbf 0,r10 /* Force it out */
572 sync /* Make sure it's out there */
573 dcbi 0,r10
574 eieio
575
576 li r7,0x10 /* int on Rx, no Tx int enable */
577 stb r7,0(r10) /* Set the register */
578 dcbf 0,r10 /* Force it out */
579 sync /* Make sure it's out there */
580 dcbi 0,r10
581 eieio
582
583 li r7,0x09 /* Set the register */
584 stb r7,0(r10) /* Set the register */
585 dcbf 0,r10 /* Force it out */
586 sync /* Make sure it's out there */
587 dcbi 0,r10
588 eieio
589
590 li r7,0x0A /* int on Rx, Tx int enable */
591 stb r7,0(r10) /* Set the register */
592 dcbf 0,r10 /* Force it out */
593 sync /* Master enable, no vector */
594 dcbi 0,r10
595 eieio
596
597 li r7,0x09 /* Set the register */
598 stb r7,0(r10) /* Set the register */
599 dcbf 0,r10 /* Force it out */
600 sync /* Make sure it's out there */
601 dcbi 0,r10
602 eieio
603
604 li r7,0x02 /* No vector */
605 stb r7,0(r10) /* Set the register */
606 dcbf 0,r10 /* Force it out */
607 sync /* Master enable, no vector */
608 dcbi 0,r10
609 eieio
610
611 lbz r7,0(r10) /* Clear interrupts */
612 sync /* Master enable, no vector */
613 dcbi 0,r10
614 eieio
615
616 wSCCrdy: eieio /* Barricade it */
617 lbz r7,0(r10) /* Get current status */
618 dcbi 0,r10
619 sync
620 andi. r7,r7,0x04 /* Is transmitter empty? */
621 beq wSCCrdy /* Nope... */
622
623 eieio
624
625 #if 0
626 mtmsr r8 /* Restore 'rupts and TR */
627 isync
628 #endif
629 blr /* Leave... */
630
631 /*
632 * This routine is used to write debug output to either the modem or printer port.
633 * parm 1 is printer (0) or modem (1); parm 2 is ID (printed directly); parm 3 converted to hex
634 */
635
636 ENTRY(dbgDisp, TAG_NO_FRAME_USED)
637
638 mr r12,r0 /* Keep R0 pristene */
639 lis r0,HIGH_ADDR(dbgDispCall) /* Top half of dbgDispCall firmware call number */
640 ori r0,r0,LOW_ADDR(dbgDispCall) /* Bottom half */
641
642 sc /* Go display the stuff */
643
644 mr r0,r12 /* Restore R0 */
645 blr /* Return... */
646
647 /* Here's the low-level part of dbgDisp */
648
649 ENTRY(dbgDispLL, TAG_NO_FRAME_USED)
650
651 dbgDispInt: mfmsr r8 /* Save the MSR */
652
653 #if 0
654 lis r10,0xF301 /* (TEST/DEBUG) */
655 ori r10,r10,0x2002 /* (TEST/DEBUG) */
656 dcbf 0,r10 /* (TEST/DEBUG) */
657 sync /* (TEST/DEBUG) */
658 dcbi 0,r10 /* (TEST/DEBUG) */
659 eieio /* (TEST/DEBUG) */
660 li r7,0x35 /* (TEST/DEBUG) */
661 stb r7,4(r10) /* (TEST/DEBUG) */
662
663 lis r7,10 /* (TEST/DEBUG) */
664 spw6: addi r7,r7,-1 /* (TEST/DEBUG) */
665 mr. r7,r7 /* (TEST/DEBUG) */
666 bne- spw6 /* (TEST/DEBUG) */
667 dcbf 0,r10 /* (TEST/DEBUG) */
668 sync /* (TEST/DEBUG) */
669 dcbi 0,r10 /* (TEST/DEBUG) */
670 eieio /* (TEST/DEBUG) */
671 #endif
672
673 rlwinm r12,r8,0,28,25 /* Turn off translation */
674 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
675
676 mflr r11 /* Save the link register */
677
678 #if 0
679 mr r7,r12 /* (TEST/DEBUG) */
680 bl dumpr7 /* (TEST/DEBUG) */
681 #endif
682
683 mr. r3,r3 /* See if printer or modem */
684 lis r10,0xF301 /* Set the top part */
685 mr r3,r4 /* Copy the ID parameter */
686
687 #if 0
688 mr r9,r12 /* (TEST/DEBUG) */
689
690 mtmsr r12 /* (TEST/DEBUG) */
691 isync /* (TEST/DEBUG) */
692
693 #if 0
694 mtmsr r8 /* (TEST/DEBUG) */
695 isync /* (TEST/DEBUG) */
696 #endif
697
698 lis r12,0xF301 /* (TEST/DEBUG) */
699 ori r12,r12,0x2002 /* (TEST/DEBUG) */
700 #if 1
701 dcbf 0,r12 /* (TEST/DEBUG) */
702 sync /* (TEST/DEBUG) */
703 dcbi 0,r12 /* (TEST/DEBUG) */
704 #endif
705
706 xqrw1: eieio /* (TEST/DEBUG) */
707 lbz r7,0(r12) /* (TEST/DEBUG) */
708 dcbi 0,r12 /* (TEST/DEBUG) */
709 sync /* (TEST/DEBUG) */
710 andi. r7,r7,0x04 /* (TEST/DEBUG) */
711 beq xqrw1 /* (TEST/DEBUG) */
712
713 eieio /* (TEST/DEBUG) */
714 li r7,0x36 /* (TEST/DEBUG) */
715 stb r7,4(r12) /* (TEST/DEBUG) */
716 eieio
717 dcbf 0,r12 /* (TEST/DEBUG) */
718 sync /* (TEST/DEBUG) */
719 dcbi 0,r12 /* (TEST/DEBUG) */
720 eieio /* (TEST/DEBUG) */
721
722
723 lis r7,10 /* (TEST/DEBUG) */
724 spw7: addi r7,r7,-1 /* (TEST/DEBUG) */
725 mr. r7,r7 /* (TEST/DEBUG) */
726 bne- spw7 /* (TEST/DEBUG) */
727 dcbf 0,r12 /* (TEST/DEBUG) */
728 sync /* (TEST/DEBUG) */
729 dcbi 0,r12 /* (TEST/DEBUG) */
730 eieio /* (TEST/DEBUG) */
731 mr r12,r9 /* (TEST/DEBUG) */
732 #endif
733
734 mtmsr r12 /* Smash the MSR */
735 isync /* Make it clean */
736
737
738 #if SIMPLESCC && !NOTQUITEASSIMPLE
739 ori r10,r10,0x3010 /* Assume the printer (this is the normal one) */
740 #else
741 ori r10,r10,0x2000 /* Assume the printer (this is the normal one) */
742 #endif
743 beq+ dbgDprintr /* It sure are... */
744 #if SIMPLESCC && !NOTQUITEASSIMPLE
745 ori r10,r10,0x0020 /* Move it over to the modem port */
746 #else
747 ori r10,r10,0x0002 /* Move it over to the modem port */
748
749 #if !NOTQUITEASSIMPLE
750 lis r7,0xF300 /* Address of SCC rounded to 128k */
751 ori r7,r7,0x0032 /* Make it cache inhibited */
752 mtdbatl 3,r7 /* Load DBAT 3 low */
753 lis r7,0xF300 /* Address of SCC rounded to 128k */
754 ori r7,r7,0x0002 /* Make it supervisor only */
755 mtdbatu 3,r7 /* Load DBAT 3 high */
756 ori r12,r12,0x0010 /* Turn on DR */
757 mtmsr r12 /* Smash the MSR */
758 isync /* Make it clean */
759
760 #endif
761 #endif
762
763 dbgDprintr: sync
764 #if 0
765 mr r7,r10 /* (TEST/DEBUG) */
766 bl dumpr7 /* (TEST/DEBUG) */
767 #endif
768
769 dcbi 0,r10 /* Toss it */
770 eieio
771
772 #if 0
773 lis r12,0xF301 /* (TEST/DEBUG) */
774 ori r12,r12,0x2002 /* (TEST/DEBUG) */
775 dcbf 0,r12 /* (TEST/DEBUG) */
776 sync /* (TEST/DEBUG) */
777 dcbi 0,r12 /* (TEST/DEBUG) */
778 eieio /* (TEST/DEBUG) */
779 li r7,0x37 /* (TEST/DEBUG) */
780 stb r7,4(r12) /* (TEST/DEBUG) */
781
782 lis r7,12 /* (TEST/DEBUG) */
783 spw8: addi r7,r7,-1 /* (TEST/DEBUG) */
784 mr. r7,r7 /* (TEST/DEBUG) */
785 bne- spw8 /* (TEST/DEBUG) */
786 dcbf 0,r12 /* (TEST/DEBUG) */
787 sync /* (TEST/DEBUG) */
788 dcbi 0,r12 /* (TEST/DEBUG) */
789 eieio /* (TEST/DEBUG) */
790 #endif
791
792
793 /* Print the ID parameter */
794
795 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
796 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
797
798 lwarx r7,0,r12 ; ?
799
800 ddwait0: lwarx r7,0,r12 /* Get the lock */
801 mr. r7,r7 /* Is it locked? */
802 bne- ddwait0 /* Yup... */
803 stwcx. r12,0,r12 /* Try to get it */
804 bne- ddwait0 /* Nope, start all over... */
805
806 #if 0
807 dcbf 0,r10 /* (TEST/DEBUG) */
808 sync /* (TEST/DEBUG) */
809 dcbi 0,r10 /* (TEST/DEBUG) */
810 eieio /* (TEST/DEBUG) */
811 li r7,0x38 /* (TEST/DEBUG) */
812 stb r7,6(r10) /* (TEST/DEBUG) */
813
814 lis r7,10 /* (TEST/DEBUG) */
815 spwa: addi r7,r7,-1 /* (TEST/DEBUG) */
816 mr. r7,r7 /* (TEST/DEBUG) */
817 bne- spwa /* (TEST/DEBUG) */
818 dcbf 0,r10 /* (TEST/DEBUG) */
819 sync /* (TEST/DEBUG) */
820 dcbi 0,r10 /* (TEST/DEBUG) */
821 eieio /* (TEST/DEBUG) */
822 #endif
823
824 rlwinm r3,r3,8,0,31 /* Get the first character */
825 bl dbgDchar /* Print it */
826 rlwinm r3,r3,8,0,31 /* Get the second character */
827 bl dbgDchar /* Print it */
828 rlwinm r3,r3,8,0,31 /* Get the third character */
829 bl dbgDchar /* Print it */
830 rlwinm r3,r3,8,0,31 /* Get the fourth character */
831 bl dbgDchar /* Print it */
832
833 li r3,0x20 /* Get a space for a separator */
834 bl dbgDchar /* Print it */
835 bl dbg4byte /* Print register 5 in hex */
836
837 li r3,0x0A /* Linefeed */
838 bl dbgDchar /* Send it */
839 li r3,0x0D /* Carriage return */
840 bl dbgDchar /* Send it */
841
842 mtlr r11 /* Get back the return */
843 #if !SIMPLESCC && !NOTQUITEASSIMPLE
844 li r7,0 /* Get a zero */
845 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
846 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
847 #endif
848 lis r12,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
849 li r7,0 /* Get a zero */
850 ori r12,r12,LOW_ADDR(fwdisplock) /* Last part */
851 dcbi 0,r10 /* ? */
852 stw r7,0(r12) /* Release the display lock */
853 mtmsr r8 /* Restore the MSR */
854 isync /* Wait for it */
855 blr /* Leave... */
856
857
858 dbg4byte: mflr r12 /* Save the return */
859
860 lis r4,HIGH_ADDR(hexTab) /* Point to the top of table */
861 li r6,8 /* Set number of hex digits to dump */
862 ori r4,r4,LOW_ADDR(hexTab) /* Point to the bottom of table */
863
864 dbgDnext: rlwinm r5,r5,4,0,31 /* Rotate a nybble */
865 subi r6,r6,1 /* Back down the count */
866 rlwinm r3,r5,0,28,31 /* Isolate the last nybble */
867 lbzx r3,r4,r3 /* Convert to ascii */
868 bl dbgDchar /* Print it */
869 mr. r6,r6 /* Any more? */
870 bne+ dbgDnext /* Convert 'em all... */
871
872 li r3,0x20 /* Space */
873 bl dbgDchar /* Send it */
874 mtlr r12 /* Restore LR */
875 blr /* Return... */
876
877 /* Write to whichever serial port. Try to leave it clean, but not too hard (this is a hack) */
878
879 dbgDchar:
880 #if SIMPLESCC && !NOTQUITEASSIMPLE
881 stb r3,0(r10) /* ? */
882 dcbf 0,r10 /* Force it out */
883 sync /* Make sure it's out there */
884
885 lis r7,3 /* Get enough for about 1ms */
886
887 dbgDchar0: addi r7,r7,-1 /* Count down */
888 mr. r7,r7 /* Waited long enough? */
889 bgt+ dbgDchar0 /* Nope... */
890 #endif
891 #if NOTQUITEASSIMPLE
892 #if 0
893 li r7,0x01 /* ? */
894 stb r7,0(r10) /* ? */
895 dcbf 0,r10 /* Force it out */
896 sync /* Make sure it's out there */
897 dcbi 0,r10
898 eieio
899
900 lbz r7,0(r10) /* ? */
901 dcbi 0,r10 /* Force it out */
902 sync /* kill it off */
903 eieio
904
905 li r7,0x00 /* ? */
906 stb r7,0(r10) /* ? */
907 dcbf 0,r10 /* Force it out */
908 sync /* Make sure it's out there */
909 dcbi 0,r10
910 eieio
911
912 lbz r7,0(r10) /* ? */
913 dcbi 0,r10 /* Force it out */
914 sync /* kill it off */
915 eieio
916 #endif
917
918 qrw1: eieio /* Barricade it */
919 lbz r7,0(r10) /* ? */
920 dcbi 0,r10
921 sync
922 andi. r7,r7,0x04 /* ? */
923 beq qrw1 /* Nope... */
924
925 eieio
926
927 stb r3,4(r10) /* ? */
928 dcbf 0,r10 /* Force it out */
929 sync /* Make sure it's out there */
930 dcbi 0,r10
931 eieio
932
933 qrw2: eieio /* Barricade it */
934 lbz r7,0(r10) /* ? */
935 dcbi 0,r10
936 sync
937 andi. r7,r7,0x04 /* ? */
938 beq qrw2 /* Nope... */
939
940 #if 0
941 eieio
942 li r7,0x10 /* ? */
943 stb r7,0(r10) /* ? */
944 dcbf 0,r10 /* Force it out */
945 sync /* Make sure it's out there */
946 dcbi 0,r10
947 eieio
948
949 lbz r7,0(r10) /* ? */
950 dcbi 0,r10 /* Force it out */
951 sync /* kill it off */
952 eieio
953 #endif
954
955 lis r7,0x0080 /* ? */
956 lis r9,0xF300 /* ? */
957 ori r7,r7,0x010F /* ? */
958 stw r7,0x28(r9) /* ? */
959 dcbf 0,r10 /* Force it out */
960 sync /* Make sure it's out there */
961 dcbi 0,r10
962 eieio
963
964 #endif
965 #if !SIMPLESCC && !NOTQUITEASSIMPLE
966 rlwinm r9,r10,0,0,29 /* Get channel a */
967 eieio /* Barricade it */
968
969 li r7,0x03 /* ? */
970 stb r7,0(r9) /* ? */
971 eieio /* Barricade it */
972
973 lbz r7,0(r9) /* ? */
974
975 eieio /* Barricade it */
976 lbz r7,0(r9) /* ? */
977
978 dchrw1: eieio /* Barricade it */
979 lbz r7,0(r10) /* ? */
980 andi. r7,r7,0x04 /* ? */
981 beq dchrw1 /* Nope... */
982
983 stb r3,4(r10) /* ? */
984 sync /* Make sure it's there */
985 eieio /* Don't get confused */
986
987 dchrw2: eieio /* Barricade it */
988 lbz r7,0(r10) /* ? */
989 andi. r7,r7,0x04 /* ? */
990 beq dchrw2 /* Nope... */
991
992 eieio /* Avoid confusion */
993 lbz r7,0(r10) /* ? */
994 andi. r7,r7,0x40 /* ? */
995 beq+ nounder /* Nope... */
996
997 eieio /* Avoid confusion */
998 li r7,0xC0 /* ? */
999 stb r7,0(r10) /* ? */
1000
1001 nounder: eieio /* Avoid confusion */
1002 li r7,0x10 /* ? */
1003 stb r7,0(r10) /* ? */
1004
1005 eieio /* Avoid confusion */
1006 li r7,0x38 /* ? */
1007 stb r7,0(r9) /* ? */
1008
1009 eieio /* Avoid confusion */
1010 li r7,0x30 /* ? */
1011 stb r7,0(r10) /* ? */
1012
1013 eieio /* Avoid confusion */
1014 li r7,0x20 /* ? */
1015 stb r7,0(r10) /* ? */
1016 eieio /* Avoid confusion */
1017 sync
1018
1019 #endif
1020 blr /* Return */
1021
1022 .globl hexTab
1023
1024 hexTab: STRINGD "0123456789ABCDEF" /* Convert hex numbers to printable hex */
1025
1026
1027 /*
1028 * Dumps all the registers in the savearea in R13
1029 */
1030
1031
1032 ENTRY(dbgRegsLL, TAG_NO_FRAME_USED)
1033
1034 li r3,0 /* ? */
1035 bl dbgRegsCm /* Join on up... */
1036
1037 /*
1038 * Note that we bypass the normal return 'cause we don't wanna mess up R3
1039 */
1040 mfsprg r11,0 /* Get the per_proc */
1041 lwz r11,PP_TEMPWORK1(r11) /* Get our return point */
1042 li r3,T_IN_VAIN /* Tell the vector handler that we took care of it */
1043 mtlr r11 /* Set the return */
1044 blr /* Bye, dudes... */
1045
1046 ENTRY(dbgRegs, TAG_NO_FRAME_USED)
1047
1048 dbgRegsCm: mfmsr r8 /* Save the MSR */
1049 mr. r3,r3 /* ? */
1050 rlwinm r12,r8,0,28,25 /* Turn off translation */
1051 lis r10,0xF301 /* Set the top part */
1052 rlwinm r12,r12,0,17,15 /* Turn off interruptions */
1053 mtmsr r12 /* Smash the MSR */
1054 isync /* Make it clean */
1055 #if SIMPLESCC && !NOTQUITEASSIMPLE
1056 ori r10,r10,0x3010 /* ? */
1057 #else
1058 ori r10,r10,0x2000 /* ? */
1059 #endif
1060 mflr r11 /* Save the link register */
1061 beq+ dbgDprints /* It sure are... */
1062 #if SIMPLESCC && !NOTQUITEASSIMPLE
1063 ori r10,r10,0x0020 /* ? */
1064 #else
1065 ori r10,r10,0x0002 /* ? */
1066
1067 dcbf 0,r10 /* Insure it is out */
1068 sync
1069 dcbi 0,r10 /* Toss it */
1070 #if !NOTQUITEASSIMPLE
1071 lis r7,0xF300 /* ? */
1072 ori r7,r7,0x0032 /* ? */
1073 mtdbatl 3,r7 /* ? */
1074 lis r7,0xF300 /* ? */
1075 ori r7,r7,0x0002 /* ? */
1076 mtdbatu 3,r7 /* ? */
1077 ori r12,r12,0x0010 /* ? */
1078 mtmsr r12 /* ? */
1079 isync /* ? */
1080 #endif
1081 #endif
1082
1083 dbgDprints:
1084 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1085 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1086
1087 lwarx r5,0,r3 ; ?
1088 ddwait1: lwarx r5,0,r3 /* Get the lock */
1089 mr. r5,r5 /* Is it locked? */
1090 bne- ddwait1 /* Yup... */
1091 stwcx. r3,0,r3 /* Try to get it */
1092 bne- ddwait1 /* Nope, start all over... */
1093
1094 li r3,0x52 /* Print eyecatcher */
1095 bl dbgDchar /* Send it */
1096 li r3,0x65 /* Print eyecatcher */
1097 bl dbgDchar /* Send it */
1098 li r3,0x67 /* Print eyecatcher */
1099 bl dbgDchar /* Send it */
1100 li r3,0x73 /* Print eyecatcher */
1101 bl dbgDchar /* Send it */
1102 li r3,0x20 /* Print eyecatcher */
1103 bl dbgDchar /* Send it */
1104
1105 lwz r5,saver0(r13) /* Do register */
1106 bl dbg4byte /* Print */
1107 lwz r5,saver1(r13) /* Do register */
1108 bl dbg4byte /* Print */
1109 lwz r5,saver2(r13) /* Do register */
1110 bl dbg4byte /* Print */
1111 lwz r5,saver3(r13) /* Do register */
1112 bl dbg4byte /* Print */
1113 li r3,0x0A /* Linefeed */
1114 bl dbgDchar /* Send it */
1115 li r3,0x0D /* Carriage return */
1116 bl dbgDchar /* Send it */
1117
1118 li r3,0x20 /* Print eyecatcher */
1119 bl dbgDchar /* Send it */
1120 li r3,0x20 /* Print eyecatcher */
1121 bl dbgDchar /* Send it */
1122 li r3,0x20 /* Print eyecatcher */
1123 bl dbgDchar /* Send it */
1124 li r3,0x20 /* Print eyecatcher */
1125 bl dbgDchar /* Send it */
1126 li r3,0x20 /* Print eyecatcher */
1127 bl dbgDchar /* Send it */
1128 lwz r5,saver4(r13) /* Do register */
1129 bl dbg4byte /* Print */
1130 lwz r5,saver5(r13) /* Do register */
1131 bl dbg4byte /* Print */
1132 lwz r5,saver6(r13) /* Do register */
1133 bl dbg4byte /* Print */
1134 lwz r5,saver7(r13) /* Do register */
1135 bl dbg4byte /* Print */
1136 li r3,0x0A /* Linefeed */
1137 bl dbgDchar /* Send it */
1138 li r3,0x0D /* Carriage return */
1139 bl dbgDchar /* Send it */
1140
1141 li r3,0x20 /* Print eyecatcher */
1142 bl dbgDchar /* Send it */
1143 li r3,0x20 /* Print eyecatcher */
1144 bl dbgDchar /* Send it */
1145 li r3,0x20 /* Print eyecatcher */
1146 bl dbgDchar /* Send it */
1147 li r3,0x20 /* Print eyecatcher */
1148 bl dbgDchar /* Send it */
1149 li r3,0x20 /* Print eyecatcher */
1150 bl dbgDchar /* Send it */
1151 lwz r5,saver8(r13) /* Do register */
1152 bl dbg4byte /* Print */
1153 lwz r5,saver9(r13) /* Do register */
1154 bl dbg4byte /* Print */
1155 lwz r5,saver10(r13) /* Do register */
1156 bl dbg4byte /* Print */
1157 lwz r5,saver11(r13) /* Do register */
1158 bl dbg4byte /* Print */
1159 li r3,0x0A /* Linefeed */
1160 bl dbgDchar /* Send it */
1161 li r3,0x0D /* Carriage return */
1162 bl dbgDchar /* Send it */
1163
1164 li r3,0x20 /* Print eyecatcher */
1165 bl dbgDchar /* Send it */
1166 li r3,0x20 /* Print eyecatcher */
1167 bl dbgDchar /* Send it */
1168 li r3,0x20 /* Print eyecatcher */
1169 bl dbgDchar /* Send it */
1170 li r3,0x20 /* Print eyecatcher */
1171 bl dbgDchar /* Send it */
1172 li r3,0x20 /* Print eyecatcher */
1173 bl dbgDchar /* Send it */
1174 lwz r5,saver12(r13) /* Do register */
1175 bl dbg4byte /* Print */
1176 lwz r5,saver13(r13) /* Do register */
1177 bl dbg4byte /* Print */
1178 lwz r5,saver14(r13) /* Do register */
1179 bl dbg4byte /* Print */
1180 lwz r5,saver15(r13) /* Do register */
1181 bl dbg4byte /* Print */
1182 li r3,0x0A /* Linefeed */
1183 bl dbgDchar /* Send it */
1184 li r3,0x0D /* Carriage return */
1185 bl dbgDchar /* Send it */
1186
1187 li r3,0x20 /* Print eyecatcher */
1188 bl dbgDchar /* Send it */
1189 li r3,0x20 /* Print eyecatcher */
1190 bl dbgDchar /* Send it */
1191 li r3,0x20 /* Print eyecatcher */
1192 bl dbgDchar /* Send it */
1193 li r3,0x20 /* Print eyecatcher */
1194 bl dbgDchar /* Send it */
1195 li r3,0x20 /* Print eyecatcher */
1196 bl dbgDchar /* Send it */
1197 lwz r5,saver16(r13) /* Do register */
1198 bl dbg4byte /* Print */
1199 lwz r5,saver17(r13) /* Do register */
1200 bl dbg4byte /* Print */
1201 lwz r5,saver18(r13) /* Do register */
1202 bl dbg4byte /* Print */
1203 lwz r5,saver19(r13) /* Do register */
1204 bl dbg4byte /* Print */
1205 li r3,0x0A /* Linefeed */
1206 bl dbgDchar /* Send it */
1207 li r3,0x0D /* Carriage return */
1208 bl dbgDchar /* Send it */
1209
1210 li r3,0x20 /* Print eyecatcher */
1211 bl dbgDchar /* Send it */
1212 li r3,0x20 /* Print eyecatcher */
1213 bl dbgDchar /* Send it */
1214 li r3,0x20 /* Print eyecatcher */
1215 bl dbgDchar /* Send it */
1216 li r3,0x20 /* Print eyecatcher */
1217 bl dbgDchar /* Send it */
1218 li r3,0x20 /* Print eyecatcher */
1219 bl dbgDchar /* Send it */
1220 lwz r5,saver20(r13) /* Do register */
1221 bl dbg4byte /* Print */
1222 lwz r5,saver21(r13) /* Do register */
1223 bl dbg4byte /* Print */
1224 lwz r5,saver22(r13) /* Do register */
1225 bl dbg4byte /* Print */
1226 lwz r5,saver23(r13) /* Do register */
1227 bl dbg4byte /* Print */
1228 li r3,0x0A /* Linefeed */
1229 bl dbgDchar /* Send it */
1230 li r3,0x0D /* Carriage return */
1231 bl dbgDchar /* Send it */
1232
1233 li r3,0x20 /* Print eyecatcher */
1234 bl dbgDchar /* Send it */
1235 li r3,0x20 /* Print eyecatcher */
1236 bl dbgDchar /* Send it */
1237 li r3,0x20 /* Print eyecatcher */
1238 bl dbgDchar /* Send it */
1239 li r3,0x20 /* Print eyecatcher */
1240 bl dbgDchar /* Send it */
1241 li r3,0x20 /* Print eyecatcher */
1242 bl dbgDchar /* Send it */
1243 lwz r5,saver24(r13) /* Do register */
1244 bl dbg4byte /* Print */
1245 lwz r5,saver25(r13) /* Do register */
1246 bl dbg4byte /* Print */
1247 lwz r5,saver26(r13) /* Do register */
1248 bl dbg4byte /* Print */
1249 lwz r5,saver27(r13) /* Do register */
1250 bl dbg4byte /* Print */
1251 li r3,0x0A /* Linefeed */
1252 bl dbgDchar /* Send it */
1253 li r3,0x0D /* Carriage return */
1254 bl dbgDchar /* Send it */
1255
1256 li r3,0x20 /* Print eyecatcher */
1257 bl dbgDchar /* Send it */
1258 li r3,0x20 /* Print eyecatcher */
1259 bl dbgDchar /* Send it */
1260 li r3,0x20 /* Print eyecatcher */
1261 bl dbgDchar /* Send it */
1262 li r3,0x20 /* Print eyecatcher */
1263 bl dbgDchar /* Send it */
1264 li r3,0x20 /* Print eyecatcher */
1265 bl dbgDchar /* Send it */
1266 lwz r5,saver28(r13) /* Do register */
1267 bl dbg4byte /* Print */
1268 lwz r5,saver29(r13) /* Do register */
1269 bl dbg4byte /* Print */
1270 lwz r5,saver30(r13) /* Do register */
1271 bl dbg4byte /* Print */
1272 lwz r5,saver31(r13) /* Do register */
1273 bl dbg4byte /* Print */
1274 li r3,0x0A /* Linefeed */
1275 bl dbgDchar /* Send it */
1276 li r3,0x0D /* Carriage return */
1277 bl dbgDchar /* Send it */
1278
1279 /* Segment registers */
1280
1281 li r3,0x53 /* Print eyecatcher */
1282 bl dbgDchar /* Send it */
1283 li r3,0x65 /* Print eyecatcher */
1284 bl dbgDchar /* Send it */
1285 li r3,0x67 /* Print eyecatcher */
1286 bl dbgDchar /* Send it */
1287 li r3,0x73 /* Print eyecatcher */
1288 bl dbgDchar /* Send it */
1289 li r3,0x20 /* Print eyecatcher */
1290 bl dbgDchar /* Send it */
1291
1292 lwz r5,savesr0(r13) /* Do register */
1293 bl dbg4byte /* Print */
1294 lwz r5,savesr1(r13) /* Do register */
1295 bl dbg4byte /* Print */
1296 lwz r5,savesr2(r13) /* Do register */
1297 bl dbg4byte /* Print */
1298 lwz r5,savesr3(r13) /* Do register */
1299 bl dbg4byte /* Print */
1300 li r3,0x0A /* Linefeed */
1301 bl dbgDchar /* Send it */
1302 li r3,0x0D /* Carriage return */
1303 bl dbgDchar /* Send it */
1304
1305 li r3,0x20 /* Print eyecatcher */
1306 bl dbgDchar /* Send it */
1307 li r3,0x20 /* Print eyecatcher */
1308 bl dbgDchar /* Send it */
1309 li r3,0x20 /* Print eyecatcher */
1310 bl dbgDchar /* Send it */
1311 li r3,0x20 /* Print eyecatcher */
1312 bl dbgDchar /* Send it */
1313 li r3,0x20 /* Print eyecatcher */
1314 bl dbgDchar /* Send it */
1315 lwz r5,savesr4(r13) /* Do register */
1316 bl dbg4byte /* Print */
1317 lwz r5,savesr5(r13) /* Do register */
1318 bl dbg4byte /* Print */
1319 lwz r5,savesr6(r13) /* Do register */
1320 bl dbg4byte /* Print */
1321 lwz r5,savesr7(r13) /* Do register */
1322 bl dbg4byte /* Print */
1323 li r3,0x0A /* Linefeed */
1324 bl dbgDchar /* Send it */
1325 li r3,0x0D /* Carriage return */
1326 bl dbgDchar /* Send it */
1327
1328 li r3,0x20 /* Print eyecatcher */
1329 bl dbgDchar /* Send it */
1330 li r3,0x20 /* Print eyecatcher */
1331 bl dbgDchar /* Send it */
1332 li r3,0x20 /* Print eyecatcher */
1333 bl dbgDchar /* Send it */
1334 li r3,0x20 /* Print eyecatcher */
1335 bl dbgDchar /* Send it */
1336 li r3,0x20 /* Print eyecatcher */
1337 bl dbgDchar /* Send it */
1338 lwz r5,savesr8(r13) /* Do register */
1339 bl dbg4byte /* Print */
1340 lwz r5,savesr9(r13) /* Do register */
1341 bl dbg4byte /* Print */
1342 lwz r5,savesr10(r13) /* Do register */
1343 bl dbg4byte /* Print */
1344 lwz r5,savesr11(r13) /* Do register */
1345 bl dbg4byte /* Print */
1346 li r3,0x0A /* Linefeed */
1347 bl dbgDchar /* Send it */
1348 li r3,0x0D /* Carriage return */
1349 bl dbgDchar /* Send it */
1350
1351 li r3,0x20 /* Print eyecatcher */
1352 bl dbgDchar /* Send it */
1353 li r3,0x20 /* Print eyecatcher */
1354 bl dbgDchar /* Send it */
1355 li r3,0x20 /* Print eyecatcher */
1356 bl dbgDchar /* Send it */
1357 li r3,0x20 /* Print eyecatcher */
1358 bl dbgDchar /* Send it */
1359 li r3,0x20 /* Print eyecatcher */
1360 bl dbgDchar /* Send it */
1361 lwz r5,savesr12(r13) /* Do register */
1362 bl dbg4byte /* Print */
1363 lwz r5,savesr13(r13) /* Do register */
1364 bl dbg4byte /* Print */
1365 lwz r5,savesr14(r13) /* Do register */
1366 bl dbg4byte /* Print */
1367 lwz r5,savesr15(r13) /* Do register */
1368 bl dbg4byte /* Print */
1369 li r3,0x0A /* Linefeed */
1370 bl dbgDchar /* Send it */
1371 li r3,0x0D /* Carriage return */
1372 bl dbgDchar /* Send it */
1373
1374 li r3,0x30 /* Print eyecatcher */
1375 bl dbgDchar /* Send it */
1376 li r3,0x31 /* Print eyecatcher */
1377 bl dbgDchar /* Send it */
1378 li r3,0x64 /* Print eyecatcher */
1379 bl dbgDchar /* Send it */
1380 li r3,0x64 /* Print eyecatcher */
1381 bl dbgDchar /* Send it */
1382 li r3,0x20 /* Print eyecatcher */
1383 bl dbgDchar /* Send it */
1384 lwz r5,savesrr0(r13) /* Do register */
1385 bl dbg4byte /* Print */
1386 lwz r5,savesrr1(r13) /* Do register */
1387 bl dbg4byte /* Print */
1388 lwz r5,savedar(r13) /* Do register */
1389 bl dbg4byte /* Print */
1390 lwz r5,savedsisr(r13) /* Do register */
1391 bl dbg4byte /* Print */
1392 li r3,0x0A /* Linefeed */
1393 bl dbgDchar /* Send it */
1394 li r3,0x0D /* Carriage return */
1395 bl dbgDchar /* Send it */
1396
1397 li r3,0x20 /* Print eyecatcher */
1398 bl dbgDchar /* Send it */
1399 li r3,0x6C /* Print eyecatcher */
1400 bl dbgDchar /* Send it */
1401 li r3,0x63 /* Print eyecatcher */
1402 bl dbgDchar /* Send it */
1403 li r3,0x63 /* Print eyecatcher */
1404 bl dbgDchar /* Send it */
1405 li r3,0x20 /* Print eyecatcher */
1406 bl dbgDchar /* Send it */
1407 lwz r5,savelr(r13) /* Do register */
1408 bl dbg4byte /* Print */
1409 lwz r5,savecr(r13) /* Do register */
1410 bl dbg4byte /* Print */
1411 lwz r5,savectr(r13) /* Do register */
1412 bl dbg4byte /* Print */
1413 li r3,0x0A /* Linefeed */
1414 bl dbgDchar /* Send it */
1415 li r3,0x0D /* Carriage return */
1416 bl dbgDchar /* Send it */
1417 mtlr r11 /* Get back the return */
1418 dcbi 0,r10 /* ? */
1419 #if !SIMPLESCC && !NOTQUITEASSIMPLE
1420 li r7,0 /* Get a zero */
1421 mtdbatu 3,r7 /* Invalidate DBAT 3 upper */
1422 mtdbatl 3,r7 /* Invalidate DBAT 3 lower */
1423 #endif
1424 lis r3,HIGH_ADDR(fwdisplock) /* Get the display locker outer */
1425 li r7,0 /* Get a zero */
1426 ori r3,r3,LOW_ADDR(fwdisplock) /* Last part */
1427 stw r7,0(r3) /* Clear display lock */
1428 mtmsr r8 /* Restore the MSR */
1429 isync /* Wait for it */
1430 blr /* Leave... */
1431
1432
1433 /*
1434 * Used for debugging to leave stuff in 0x380-0x3FF (128 bytes).
1435 * Mapping is V=R. Stores and loads are real.
1436 */
1437
1438 ENTRY(dbgCkpt, TAG_NO_FRAME_USED)
1439
1440 mr r12,r0 /* Keep R0 pristene */
1441 lis r0,HIGH_ADDR(dbgCkptCall) /* Top half of dbgCkptCall firmware call number */
1442 ori r0,r0,LOW_ADDR(dbgCkptCall) /* Bottom half */
1443
1444 sc /* Go stash the stuff */
1445
1446 mr r0,r12 /* Restore R0 */
1447 blr /* Return... */
1448
1449 /* Here's the low-level part of dbgCkpt */
1450
1451 ENTRY(dbgCkptLL, TAG_NO_FRAME_USED)
1452
1453 li r12,0x380 /* Point to output area */
1454 li r1,32 /* Get line size */
1455 dcbz 0,r12 /* Make sure we don't fetch a cache line */
1456
1457 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1458
1459 dcbt r1,r3 /* Start in the next line */
1460
1461 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1462 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1463 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1464 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1465 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1466 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1467 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1468
1469 add r3,r3,r1 /* Bump input */
1470
1471 stw r4,0x00(r12) /* Store it */
1472 stw r5,0x04(r12) /* Store it */
1473 stw r6,0x08(r12) /* Store it */
1474 stw r7,0x0C(r12) /* Store it */
1475 stw r8,0x10(r12) /* Store it */
1476 stw r9,0x14(r12) /* Store it */
1477 stw r10,0x18(r12) /* Store it */
1478 stw r11,0x1C(r12) /* Store it */
1479
1480 dcbz r1,r12 /* Clear the next line */
1481 add r12,r12,r1 /* Point to next output line */
1482
1483 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1484 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1485 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1486 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1487 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1488 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1489 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1490 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1491
1492 dcbt r1,r3 /* Touch the next line */
1493 add r3,r3,r1 /* Point to next input line */
1494
1495 stw r4,0x00(r12) /* Store it */
1496 stw r5,0x04(r12) /* Store it */
1497 stw r6,0x08(r12) /* Store it */
1498 stw r7,0x0C(r12) /* Store it */
1499 stw r8,0x10(r12) /* Store it */
1500 stw r9,0x14(r12) /* Store it */
1501 stw r10,0x18(r12) /* Store it */
1502 stw r11,0x1C(r12) /* Store it */
1503
1504 dcbz r1,r12 /* Clear the next line */
1505 add r12,r12,r1 /* Point to next output line */
1506
1507 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1508 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1509 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1510 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1511 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1512 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1513 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1514 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1515
1516 dcbt r1,r3 /* Touch the next line */
1517 add r3,r3,r1 /* Point to next input line */
1518
1519 stw r4,0x00(r12) /* Store it */
1520 stw r5,0x04(r12) /* Store it */
1521 stw r6,0x08(r12) /* Store it */
1522 stw r7,0x0C(r12) /* Store it */
1523 stw r8,0x10(r12) /* Store it */
1524 stw r9,0x14(r12) /* Store it */
1525 stw r10,0x18(r12) /* Store it */
1526 stw r11,0x1C(r12) /* Store it */
1527
1528 dcbz r1,r12 /* Clear the next line */
1529 add r12,r12,r1 /* Point to next output line */
1530
1531 lwz r4,0x00(r3) /* Load up storage to checkpoint */
1532 lwz r5,0x04(r3) /* Load up storage to checkpoint */
1533 lwz r6,0x08(r3) /* Load up storage to checkpoint */
1534 lwz r7,0x0C(r3) /* Load up storage to checkpoint */
1535 lwz r8,0x10(r3) /* Load up storage to checkpoint */
1536 lwz r9,0x14(r3) /* Load up storage to checkpoint */
1537 lwz r10,0x18(r3) /* Load up storage to checkpoint */
1538 lwz r11,0x1C(r3) /* Load up storage to checkpoint */
1539
1540 stw r4,0x00(r12) /* Store it */
1541 stw r5,0x04(r12) /* Store it */
1542 stw r6,0x08(r12) /* Store it */
1543 stw r7,0x0C(r12) /* Store it */
1544 stw r8,0x10(r12) /* Store it */
1545 stw r9,0x14(r12) /* Store it */
1546 stw r10,0x18(r12) /* Store it */
1547 stw r11,0x1C(r12) /* Store it */
1548
1549 blr
1550
1551
1552 /*
1553 * Do Preemption. Forces a T_PREEMPT trap to allow a preemption to occur.
1554 */
1555
1556 ENTRY(DoPreemptLL, TAG_NO_FRAME_USED)
1557
1558 mfsprg r11,0 /* Get the per_proc address */
1559 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1560 li r3,T_PREEMPT /* Set preemption interrupt value */
1561 mtlr r11 /* Restore the LR */
1562 stw r3,saveexception(r13) /* Modify the exception type to preemption */
1563 blr /* Return to interrupt handler */
1564
1565
1566 /*
1567 * Force 'rupt handler to dispatch with new context
1568 * R3 at the call contains the new savearea.
1569 * R4 at the call contains a return code to pass back in R3.
1570 * Forces a T_CSWITCH
1571 */
1572
1573 ENTRY(SwitchContextLL, TAG_NO_FRAME_USED)
1574
1575 mfsprg r11,0 /* Get the per_proc address */
1576 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1577 li r3,T_CSWITCH /* Set context switch value */
1578 mtlr r11 /* Restore the LR */
1579 stw r3,saveexception(r13) /* Modify the exception type to switch context */
1580 blr /* Return to interrupt handler */
1581
1582
1583 /*
1584 * Create a fake I/O 'rupt.
1585 * Forces a T_INTERRUPT trap to pretend that an actual I/O interrupt occurred.
1586 */
1587
1588 ENTRY(CreateFakeIOLL, TAG_NO_FRAME_USED)
1589
1590 mfsprg r11,0 /* Get the per_proc address */
1591 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1592 li r3,T_INTERRUPT /* Set external interrupt value */
1593 mtlr r11 /* Restore the LR */
1594 stw r3,saveexception(r13) /* Modify the exception type to external */
1595 blr /* Return to interrupt handler */
1596
1597 /*
1598 * Create a shutdown context
1599 * Forces a T_SHUTDOWN trap.
1600 */
1601
1602 ENTRY(CreateShutdownCTXLL, TAG_NO_FRAME_USED)
1603
1604 mfsprg r11,0 /* Get the per_proc address */
1605 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1606 li r3,T_SHUTDOWN /* Set external interrupt value */
1607 mtlr r11 /* Restore the LR */
1608 stw r3,saveexception(r13) /* Modify the exception type to external */
1609 blr /* Return to interrupt handler */
1610
1611 /*
1612 * Create a fake decrementer 'rupt.
1613 * Forces a T_DECREMENTER trap to pretend that an actual decrementer interrupt occurred.
1614 */
1615
1616 ENTRY(CreateFakeDECLL, TAG_NO_FRAME_USED)
1617
1618 mfsprg r11,0 /* Get the per_proc address */
1619 lwz r11,PP_TEMPWORK1(r11) /* Restore the return address */
1620 li r3,T_DECREMENTER /* Set decrementer interrupt value */
1621 mtlr r11 /* Restore the LR */
1622 stw r3,saveexception(r13) /* Modify the exception type to external */
1623 blr /* Return to interrupt handler */
1624
1625 /*
1626 * Choke the system.
1627 */
1628
1629 ENTRY(DoChokeLL, TAG_NO_FRAME_USED)
1630
1631 mfsprg r11,0 ; Get the per_proc address
1632 lwz r11,PP_TEMPWORK1(r11) ; Restore the return address
1633 li r3,T_CHOKE ; Set external interrupt value
1634 mtlr r11 ; Restore the LR
1635 stw r3,saveexception(r13) ; Modify the exception type to external
1636 blr ; Return to interrupt handler
1637
1638 /*
1639 * Set the low level trace flags
1640 */
1641
1642 ENTRY(LLTraceSet, TAG_NO_FRAME_USED)
1643
1644 mfsprg r6,2 ; Get feature flags
1645 mfmsr r12 /* Get the MSR */
1646 mr r4,r3 /* Save the new value */
1647 andi. r3,r12,0x01C0 /* Clear interrupts and translation */
1648 mtcrf 0x04,r6 ; Set the features
1649 bt pfNoMSRirb,ltsNoMSR ; Use MSR...
1650
1651 mtmsr r3 ; Translation and all off
1652 isync ; Toss prefetch
1653 b ltsNoMSRx
1654
1655 ltsNoMSR: li r0,loadMSR ; Get the MSR setter SC
1656 sc ; Set it
1657
1658 ltsNoMSRx:
1659
1660 lis r5,hi16(EXT(trcWork)) ; Get trace area
1661 rlwinm r12,r12,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
1662 ori r5,r5,lo16(EXT(trcWork)) ; again
1663
1664 lwz r3,traceMask(r5) /* Get the old trace flags to pass back */
1665 rlwinm r12,r12,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
1666 stw r4,traceMask(r5) /* Replace with the new ones */
1667
1668 mtmsr r12 /* Restore the MSR */
1669 isync
1670
1671 blr /* Leave... */
1672
1673 #if 1
1674
1675 /*
1676 ; ***************************************************************************
1677 ;
1678 ; ----------------- Grateful Deb ----------------
1679 ;
1680 ; Debugging: direct draw into main screen menu bar
1681 ;
1682 ; Takes R4 value, converts it to hex characters and displays it.
1683 ;
1684 ; Gotta make sure the DCBST is done to force the pixels from the cache.
1685 ;
1686 ; Position is taken as column, row (0 based) from R3.
1687 ; Characters are from hexfont, and are 16x16 pixels.
1688 ;
1689 ; Only works with two processors so far
1690 ;
1691 ;
1692 ; ***************************************************************************
1693 */
1694
1695 #define GDfromright 20
1696 #define GDfontsize 16
1697
1698 ENTRY(GratefulDeb,TAG_NO_FRAME_USED)
1699 mfspr r6,pir /* Get the PIR */
1700 lis r5,HIGH_ADDR(EXT(GratefulDebWork)) /* Point to our work area */
1701 rlwinm r6,r6,8,23,23 /* Get part of the offset to our processors area */
1702 ori r5,r5,LOW_ADDR(EXT(GratefulDebWork)) /* Start building the address */
1703 rlwimi r6,r6,2,21,21 /* Get the rest of the offset to our processors area */
1704 add r6,r6,r5 /* Point at our CPU's work area */
1705 mfmsr r5 /* Get that MSR */
1706 stmw r0,GDsave(r6) /* Save all registers */
1707 lwz r10,GDready(r6) /* See if we're all ready to go */
1708 ori r0,r5,0x2000 /* Turn on the floating point */
1709 mr r31,r6 /* Get a more sane base register */
1710 mr. r10,r10 /* Are we all set? */
1711 mtmsr r0 /* Enable floating point */
1712 isync
1713
1714 stfd f0,GDfp0(r31) /* Save FP */
1715 stfd f1,GDfp1(r31) /* Save FP */
1716 stfd f2,GDfp2(r31) /* Save FP */
1717 stfd f3,GDfp3(r31) /* Save FP */
1718
1719 beq- GDbailout /* Go and bail... */
1720
1721 rlwinm r25,r3,0,16,31 /* Isolate just the row number */
1722 lwz r28,GDtopleft(r31) /* Get the physical address of our line 0 */
1723 rlwinm r3,r3,16,16,31 /* Isolate the column number */
1724 lwz r27,GDrowbytes(r31) /* Get the number of bytes per row */
1725 lwz r9,GDrowchar(r31) /* Get the number of bytes per row of full leaded charactrers */
1726 lwz r26,GDdepth(r31) /* Get the bit depth */
1727 mullw r25,r25,r9 /* get offset to the row to write in bytes */
1728 lwz r24,GDcollgn(r31) /* Get the size of columns in bytes */
1729 add r25,r28,r25 /* Physical address of row */
1730 mullw r3,r3,r24 /* Get byte offset to first output column */
1731
1732 li r9,32 /* Get the initial shift calc */
1733
1734 lis r20,HIGH_ADDR(hexfont) /* Point to the font */
1735
1736 li r18,GDfontsize /* Get the number of rows in the font */
1737 ori r20,r20,LOW_ADDR(hexfont) /* Point to the low part */
1738 add r21,r25,r3 /* Physical address of top left output pixel */
1739 sub r9,r9,r26 /* Get right shift justifier for pixel size */
1740 li r7,32 /* Number of bits per word */
1741
1742 startNybble:
1743 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1744 li r19,8 /* Get the number of characters in a row */
1745
1746 getNybble: rlwinm r10,r4,9,23,26 /* Get the top nybble * 32 */
1747 rlwinm r4,r4,4,0,31 /* Rotate a nybble */
1748 add r10,r20,r10 /* Point to the character in the font */
1749
1750 rlwinm r16,r26,4,0,27 /* Width of row in actual bits */
1751 lhz r15,0(r10) /* Get the next row of the font */
1752
1753 rendrow: rlwinm r17,r15,16,0,0 /* Get the next font pixel in the row */
1754 rlwinm r15,r15,1,16,31 /* Move in the next font pixel */
1755 srawi r17,r17,31 /* Fill with 1s if black and 0s if white (reversed) */
1756
1757 slw r14,r14,r26 /* Make room for our pixel in a register */
1758 srw r17,r17,r9 /* Isolate one pixels worth of black or white */
1759 sub. r7,r7,r26 /* See how may bits are left */
1760 sub r16,r16,r26 /* Count how many bits are left to store for this row */
1761 or r14,r14,r17 /* Put in the pixel */
1762 bne+ notfull /* Finish rendering this word */
1763
1764 not r14,r14 /* Invert to black on white */
1765 stw r14,0(r6) /* Write out the word */
1766 li r7,32 /* Bit per word count */
1767 addi r6,r6,4 /* Point to the next word */
1768
1769 notfull: mr. r16,r16 /* Have we finished the whole character row? */
1770 bne+ rendrow /* Finish rendering the row */
1771
1772 addic. r19,r19,-1 /* Are we finished with a whole display row yet? */
1773 bne+ getNybble /* Not yet... */
1774
1775 la r6,GDrowbuf1(r31) /* Point to the row buffer */
1776 rlwinm r19,r26,31,0,29 /* Number of cache lines (depth/2) */
1777 mr r14,r21 /* Get the frame buffer address */
1778
1779 // BREAKPOINT_TRAP
1780
1781 blitrow: lfd f0,0(r6) /* Load a line */
1782 lfd f1,8(r6)
1783 lfd f2,16(r6)
1784 lfd f3,24(r6)
1785
1786 stfd f0,0(r14) /* Blit a line */
1787 stfd f1,8(r14)
1788 stfd f2,16(r14)
1789 stfd f3,24(r14)
1790
1791 addi r6,r6,32 /* Next buffered line */
1792
1793 dcbst 0,r14 /* Force the line to the screen */
1794 sync /* Make sure the line is on it's way */
1795 eieio /* Make sure we beat the invalidate */
1796 dcbi 0,r14 /* Make sure we leave no paradox */
1797
1798 addic. r19,r19,-1 /* Done all lines yet? */
1799 addi r14,r14,32 /* Point to the next output */
1800 bne+ blitrow /* Nope, do it some more... */
1801
1802 addic. r18,r18,-1 /* Have we done all the rows in character yet? */
1803 addi r20,r20,2 /* Offset the font to the next row */
1804 add r21,r21,r27 /* Point to start of next row */
1805 bne+ startNybble /* Nope, go through the word one more time... */
1806
1807 GDbailout: mr r1,r31 /* Move the workarea base */
1808
1809 lfd f0,GDfp0(r31) /* Restore FP */
1810 lfd f1,GDfp1(r31) /* Restore FP */
1811 lfd f2,GDfp2(r31) /* Restore FP */
1812 lfd f3,GDfp3(r31) /* Restore FP */
1813
1814 mtmsr r5 /* Disable floating point */
1815 isync
1816
1817 lmw r3,GDsave+12(r1) /* Restore most registers */
1818 lwz r0,GDsave(r1) /* Restore R0 */
1819 lwz r1,GDsave+4(r1) /* Finally, R1 */
1820 blr /* Leave... */
1821
1822
1823 /*
1824 * void GratefulDebDisp(unsigned int coord, unsigned int data);
1825 */
1826
1827
1828 ENTRY(GratefulDebDisp,TAG_NO_FRAME_USED)
1829
1830 mfmsr r9 /* Save the current MSR */
1831 mflr r7 /* Save the return */
1832 andi. r8,r9,0x7FCF /* Clear interrupt and translation */
1833 mtmsr r8 /* Turn 'em really off */
1834 isync /* Make sure about the translation part */
1835 bl EXT(GratefulDeb) /* Display it */
1836 mtmsr r9 /* Restore interrupt and translation */
1837 mtlr r7 /* Restore return */
1838 isync /* Make sure */
1839 blr
1840
1841
1842 #endif
1843
1844 /*
1845 * void checkNMI(void);
1846 */
1847
1848
1849 ENTRY(checkNMI,TAG_NO_FRAME_USED)
1850
1851 mfmsr r9 /* Save it */
1852 andi. r8,r9,0x7FCF /* Clear it */
1853 mtmsr r8 /* Disable it */
1854 isync /* Fence it */
1855 lis r7,0xF300 /* Find it */
1856 ori r7,r7,0x0020 /* Find it */
1857 dcbi 0,r7 /* Toss it */
1858 sync /* Sync it */
1859 rlwinm r9,r9,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
1860 eieio /* Get it */
1861 lwz r6,0x000C(r7) /* Check it */
1862 eieio /* Fence it */
1863 dcbi 0,r7 /* Toss it */
1864 rlwinm r9,r9,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
1865 rlwinm. r4,r6,0,19,19 /* Check it */
1866 rlwinm r6,r6,0,20,18 /* Clear it */
1867 sync /* Sync it */
1868 eieio /* Fence it */
1869 beq+ xnonmi /* Branch on it */
1870
1871 stw r6,0x0008(r7) /* Reset it */
1872 sync /* Sync it */
1873 dcbi 0,r6 /* Toss it */
1874 eieio /* Fence it */
1875
1876 mtmsr r9 /* Restore it */
1877 isync /* Hold it */
1878
1879 BREAKPOINT_TRAP /* Kill it */
1880 blr /* Return from it */
1881
1882 xnonmi: /* Label it */
1883 mtmsr r9 /* Restore it */
1884 isync /* Hold it */
1885 blr /* Return from it */
1886
1887
1888 /*
1889 * Early debug code
1890 */
1891
1892 dumpr7: lis r9,HIGH_ADDR(hexTab) /* (TEST/DEBUG) */
1893 li r5,8 /* (TEST/DEBUG) */
1894 ori r9,r9,LOW_ADDR(hexTab) /* (TEST/DEBUG) */
1895
1896 dumpr7n: rlwinm r7,r7,4,0,31 /* (TEST/DEBUG) */
1897 mr r6,r7 /* (TEST/DEBUG) */
1898 andi. r6,r6,15 /* (TEST/DEBUG) */
1899 lbzx r6,r9,r6 /* (TEST/DEBUG) */
1900 lis r10,0xF301 /* (TEST/DEBUG) */
1901 ori r10,r10,0x2000 /* (TEST/DEBUG) */
1902
1903 #if 0
1904 xqrw2: eieio /* (TEST/DEBUG) */
1905 lbz r7,0(r10) /* (TEST/DEBUG) */
1906 dcbi 0,r10 /* (TEST/DEBUG) */
1907 sync /* (TEST/DEBUG) */
1908 andi. r7,r7,0x04 /* (TEST/DEBUG) */
1909 beq xqrw2 /* (TEST/DEBUG) */
1910 #endif
1911
1912 dcbf 0,r10 /* (TEST/DEBUG) */
1913 sync /* (TEST/DEBUG) */
1914 dcbi 0,r10 /* (TEST/DEBUG) */
1915 eieio /* (TEST/DEBUG) */
1916 stb r6,4(r10) /* (TEST/DEBUG) */
1917
1918 lis r6,10 /* (TEST/DEBUG) */
1919 dumpr7d: addi r6,r6,-1 /* (TEST/DEBUG) */
1920 mr. r6,r6 /* (TEST/DEBUG) */
1921 bne- dumpr7d /* (TEST/DEBUG) */
1922 dcbf 0,r10 /* (TEST/DEBUG) */
1923 sync /* (TEST/DEBUG) */
1924 dcbi 0,r10 /* (TEST/DEBUG) */
1925 eieio /* (TEST/DEBUG) */
1926
1927 addic. r5,r5,-1 /* (TEST/DEBUG) */
1928 bne+ dumpr7n /* (TEST/DEBUG) */
1929
1930 blr /* (TEST/DEBUG) */
1931
1932 ;
1933 ; Log a special entry in physical memory.
1934 ; This assumes that memory size has been significantly lowered using
1935 ; the maxmem boot option. The buffer starts just after the end of mem_size.
1936 ;
1937 ; This is absolutely for special tracing cases. Do not ever leave in...
1938 ;
1939
1940 ENTRY(dbgLog,TAG_NO_FRAME_USED)
1941
1942 li r11,0 ; Clear callers callers callers return
1943 li r10,0 ; Clear callers callers callers callers return
1944 li r9,0 ; Clear callers callers callers callers callers return
1945 lwz r2,0(r1) ; Get callers callers stack frame
1946 lis r0,0x4000 ; First invalid address
1947 lwz r12,8(r2) ; Get our callers return
1948 lwz r2,0(r2) ; Back chain
1949
1950 mr. r2,r2 ; End of chain?
1951 cmplw cr1,r2,r0 ; Valid kernel address?
1952 beq- nosavehere ; Yes, end of chain...
1953 bge- cr1,nosavehere ; No...
1954 lwz r11,8(r2) ; Get our callers return
1955 lwz r2,0(r2) ; Back chain
1956
1957 mr. r2,r2 ; End of chain?
1958 cmplw cr1,r2,r0 ; Valid kernel address?
1959 beq- nosavehere ; Yes, end of chain...
1960 bge- cr1,nosavehere ; No...
1961 lwz r10,8(r2) ; Get our callers return
1962 lwz r2,0(r2) ; Back chain
1963
1964 mr. r2,r2 ; End of chain?
1965 cmplw cr1,r2,r0 ; Valid kernel address?
1966 beq- nosavehere ; Yes, end of chain...
1967 bge- cr1,nosavehere ; No...
1968 lwz r9,8(r2) ; Get our callers return
1969
1970 nosavehere: mfmsr r8 ; Get the MSR
1971 lis r2,hi16(EXT(DebugWork)) ; High part of area
1972 lis r7,hi16(EXT(mem_actual)) ; High part of actual
1973 andi. r0,r8,0x7FCF ; Interrupts and translation off
1974 ori r2,r2,lo16(EXT(DebugWork)) ; Get the entry
1975 mtmsr r0 ; Turn stuff off
1976 ori r7,r7,lo16(EXT(mem_actual)) ; Get the actual
1977 isync
1978
1979 lwz r0,4(r2) ; Get the flag
1980 mr. r0,r0 ; Should we log?
1981 lwz r0,0(r7) ; Get the end of memory
1982 lwz r7,0(r2) ; Get the position
1983 bne- waytoofar ; No logging...
1984 mr. r7,r7 ; Is this the first?
1985 bne+ gotspot ; Nope...
1986
1987 lis r7,hi16(EXT(mem_size)) ; High part of defined memory
1988 ori r7,r7,lo16(EXT(mem_size)) ; Low part of defined memory
1989 lwz r7,0(r7) ; Make it end of defined
1990
1991 gotspot: cmplw r7,r0 ; Do we fit in memory
1992 addi r0,r7,0x0020 ; Next slot
1993 bge- waytoofar ; No fit...
1994
1995 stw r0,0(r2) ; Set next time slot
1996 dcbz 0,r7 ; Zap it
1997
1998 stw r3,0(r7) ; First data
1999 li r3,32 ; Disp to next line
2000 stw r4,4(r7) ; Second data
2001 dcbz r3,r7 ; Zap it
2002 stw r5,8(r7) ; Third data
2003 stw r6,12(r7) ; Fourth data
2004
2005 stw r12,16(r7) ; Callers callers
2006 stw r11,20(r7) ; Callers callers caller
2007 stw r10,24(r7) ; Callers callers callers caller
2008 stw r9,28(r7) ; Callers callers callers callers caller
2009
2010 waytoofar: mtmsr r8 ; Back to normal
2011 isync
2012 blr
2013
2014 ;
2015 ; Same as the other, but no traceback and 16 byte entry
2016 ; Trashes R0, R2, R10, R12
2017 ;
2018
2019 .align 5
2020 .globl EXT(dbgLog2)
2021
2022 LEXT(dbgLog2)
2023
2024
2025 mfmsr r10 ; Get the MSR
2026 lis r2,hi16(EXT(DebugWork)) ; High part of area
2027 lis r12,hi16(EXT(mem_actual)) ; High part of actual
2028 andi. r0,r10,0x7FCF ; Interrupts and translation off
2029 ori r2,r2,lo16(EXT(DebugWork)) ; Get the entry
2030 mtmsr r0 ; Turn stuff off
2031 ori r12,r12,lo16(EXT(mem_actual)) ; Get the actual
2032 isync
2033
2034 lwz r0,4(r2) ; Get the flag
2035 mr. r0,r0 ; Should we log?
2036 lwz r0,0(r12) ; Get the end of memory
2037 lwz r12,0(r2) ; Get the position
2038 bne- waytoofar2 ; No logging...
2039 mr. r12,r12 ; Is this the first?
2040 bne+ gotspot2 ; Nope...
2041
2042 lis r12,hi16(EXT(mem_size)) ; High part of defined memory
2043 ori r12,r12,lo16(EXT(mem_size)) ; Low part of defined memory
2044 lwz r12,0(r12) ; Make it end of defined
2045
2046 gotspot2: cmplw cr1,r12,r0 ; Do we fit in memory
2047 rlwinm. r0,r12,0,27,27 ; Are we on a new line?
2048 bge- cr1,waytoofar2 ; No fit...
2049 addi r0,r12,0x0010 ; Next slot
2050
2051 bne+ nonewline ; Not on a new line...
2052 dcbz br0,r12 ; Clear it so we do not fetch it
2053
2054 nonewline: cmplwi r3,68 ; Special place for time stamp?
2055
2056 stw r0,0(r2) ; Set next time slot
2057 bne+ nospcts ; Nope...
2058
2059 lwz r0,0x17C(br0) ; Get special saved time stamp
2060 b nospctt ; Skip...
2061
2062 nospcts: mftb r0 ; Get the current time
2063
2064 nospctt: stw r3,4(r12) ; First data
2065 stw r4,8(r12) ; Second data
2066 stw r5,12(r12) ; Third data
2067 stw r0,0(r12) ; Time stamp
2068
2069 waytoofar2: mtmsr r10 ; Back to normal
2070 isync
2071 blr
2072
2073
2074 ;
2075 ; Saves floating point registers
2076 ;
2077
2078 .align 5
2079 .globl EXT(stFloat)
2080
2081 LEXT(stFloat)
2082
2083 mfmsr r0 ; Save the MSR
2084 rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
2085 rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
2086 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2087 ori r4,r4,lo16(MASK(MSR_FP)) ; Enable floating point
2088 mtmsr r4
2089 isync
2090
2091 stfd f0,0x00(r3)
2092 stfd f1,0x08(r3)
2093 stfd f2,0x10(r3)
2094 stfd f3,0x18(r3)
2095 stfd f4,0x20(r3)
2096 stfd f5,0x28(r3)
2097 stfd f6,0x30(r3)
2098 stfd f7,0x38(r3)
2099 stfd f8,0x40(r3)
2100 stfd f9,0x48(r3)
2101 stfd f10,0x50(r3)
2102 stfd f11,0x58(r3)
2103 stfd f12,0x60(r3)
2104 stfd f13,0x68(r3)
2105 stfd f14,0x70(r3)
2106 stfd f15,0x78(r3)
2107 stfd f16,0x80(r3)
2108 stfd f17,0x88(r3)
2109 stfd f18,0x90(r3)
2110 stfd f19,0x98(r3)
2111 stfd f20,0xA0(r3)
2112 stfd f21,0xA8(r3)
2113 stfd f22,0xB0(r3)
2114 stfd f23,0xB8(r3)
2115 stfd f24,0xC0(r3)
2116 stfd f25,0xC8(r3)
2117 stfd f26,0xD0(r3)
2118 stfd f27,0xD8(r3)
2119 stfd f28,0xE0(r3)
2120 stfd f29,0xE8(r3)
2121 stfd f30,0xF0(r3)
2122 stfd f31,0xF8(r3)
2123 mffs f0
2124 stfd f0,0x100(r3)
2125 lfd f0,0x00(r3)
2126 mtmsr r0
2127 isync
2128 blr
2129
2130
2131 ;
2132 ; Saves vector registers. Returns 0 if non-Altivec machine.
2133 ;
2134
2135 .align 5
2136 .globl EXT(stVectors)
2137
2138 LEXT(stVectors)
2139
2140
2141 mfsprg r6,2 ; Get features
2142 mr r5,r3 ; Save area address
2143 rlwinm. r6,r6,0,pfAltivecb,pfAltivecb ; Do we have Altivec?
2144 li r3,0 ; Assume failure
2145 beqlr- ; No...
2146
2147 mfmsr r0 ; Save the MSR
2148 rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
2149 rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
2150 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2151 oris r4,r4,hi16(MASK(MSR_VEC)) ; Enable vectors
2152 mtmsr r4
2153 isync
2154
2155 stvxl v0,0,r5
2156 addi r5,r5,16
2157 stvxl v1,0,r5
2158 addi r5,r5,16
2159 stvxl v2,0,r5
2160 addi r5,r5,16
2161 stvxl v3,0,r5
2162 addi r5,r5,16
2163 stvxl v4,0,r5
2164 addi r5,r5,16
2165 stvxl v5,0,r5
2166 addi r5,r5,16
2167 stvxl v6,0,r5
2168 addi r5,r5,16
2169 stvxl v7,0,r5
2170 addi r5,r5,16
2171 stvxl v8,0,r5
2172 addi r5,r5,16
2173 stvxl v9,0,r5
2174 addi r5,r5,16
2175 stvxl v10,0,r5
2176 addi r5,r5,16
2177 stvxl v11,0,r5
2178 addi r5,r5,16
2179 stvxl v12,0,r5
2180 addi r5,r5,16
2181 stvxl v13,0,r5
2182 addi r5,r5,16
2183 stvxl v14,0,r5
2184 addi r5,r5,16
2185 stvxl v15,0,r5
2186 addi r5,r5,16
2187 stvxl v16,0,r5
2188 addi r5,r5,16
2189 stvxl v17,0,r5
2190 addi r5,r5,16
2191 stvxl v18,0,r5
2192 addi r5,r5,16
2193 stvxl v19,0,r5
2194 addi r5,r5,16
2195 stvxl v20,0,r5
2196 addi r5,r5,16
2197 stvxl v21,0,r5
2198 addi r5,r5,16
2199 stvxl v22,0,r5
2200 addi r5,r5,16
2201 stvxl v23,0,r5
2202 addi r5,r5,16
2203 stvxl v24,0,r5
2204 addi r5,r5,16
2205 stvxl v25,0,r5
2206 addi r5,r5,16
2207 stvxl v26,0,r5
2208 addi r5,r5,16
2209 stvxl v27,0,r5
2210 addi r5,r5,16
2211 stvxl v28,0,r5
2212 addi r5,r5,16
2213 stvxl v29,0,r5
2214 addi r5,r5,16
2215 stvxl v30,0,r5
2216 addi r5,r5,16
2217 stvxl v31,0,r5
2218 mfvscr v31
2219 addi r6,r5,16
2220 stvxl v31,0,r6
2221 li r3,1
2222 lvxl v31,0,r5
2223 mtmsr r0
2224 isync
2225
2226 blr
2227
2228
2229 ;
2230 ; Saves yet more registers
2231 ;
2232
2233 .align 5
2234 .globl EXT(stSpecrs)
2235
2236 LEXT(stSpecrs)
2237
2238 mfmsr r0 ; Save the MSR
2239 rlwinm r0,r0,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
2240 rlwinm r0,r0,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
2241 rlwinm r4,r0,0,MSR_EE_BIT,MSR_EE_BIT ; Turn off interruptions
2242 mtmsr r4
2243 isync
2244
2245 mfpvr r12
2246 stw r12,4(r3)
2247 rlwinm r12,r12,16,16,31
2248
2249 mfdbatu r4,0
2250 mfdbatl r5,0
2251 mfdbatu r6,1
2252 mfdbatl r7,1
2253 mfdbatu r8,2
2254 mfdbatl r9,2
2255 mfdbatu r10,3
2256 mfdbatl r11,3
2257 stw r4,8(r3)
2258 stw r5,12(r3)
2259 stw r6,16(r3)
2260 stw r7,20(r3)
2261 stw r8,24(r3)
2262 stw r9,28(r3)
2263 stw r10,32(r3)
2264 stw r11,36(r3)
2265
2266 mfibatu r4,0
2267 mfibatl r5,0
2268 mfibatu r6,1
2269 mfibatl r7,1
2270 mfibatu r8,2
2271 mfibatl r9,2
2272 mfibatu r10,3
2273 mfibatl r11,3
2274 stw r4,40(r3)
2275 stw r5,44(r3)
2276 stw r6,48(r3)
2277 stw r7,52(r3)
2278 stw r8,56(r3)
2279 stw r9,60(r3)
2280 stw r10,64(r3)
2281 stw r11,68(r3)
2282
2283 mfsprg r4,0
2284 mfsprg r5,1
2285 mfsprg r6,2
2286 mfsprg r7,3
2287 stw r4,72(r3)
2288 stw r5,76(r3)
2289 stw r6,80(r3)
2290 stw r7,84(r3)
2291
2292 mfsdr1 r4
2293 stw r4,88(r3)
2294
2295 la r4,92(r3)
2296 li r5,0
2297
2298 stSnsr: mfsrin r6,r5
2299 addis r5,r5,0x1000
2300 stw r6,0(r4)
2301 mr. r5,r5
2302 addi r4,r4,4
2303 bne+ stSnsr
2304
2305 cmplwi cr1,r12,PROCESSOR_VERSION_604e
2306 cmplwi cr5,r12,PROCESSOR_VERSION_604ev
2307 cror cr1_eq,cr1_eq,cr5_eq ; Set if 604 type
2308 cmplwi r12,PROCESSOR_VERSION_750
2309 mfspr r4,hid0
2310 stw r4,(39*4)(r3)
2311
2312 li r4,0
2313 li r5,0
2314 li r6,0
2315 li r7,0
2316 beq- cr1,before750
2317 blt- before750
2318
2319 mfspr r4,hid1
2320 mfspr r5,l2cr
2321 mfspr r6,msscr0
2322 mfspr r7,msscr1
2323
2324 before750: stw r4,(40*4)(r3)
2325 stw r6,(42*4)(r3)
2326 stw r5,(41*4)(r3)
2327 stw r7,(43*4)(r3)
2328
2329 li r4,0
2330 beq isis750
2331
2332 mfspr r4,pir
2333 isis750: stw r4,0(r3)
2334
2335 li r4,0
2336 li r5,0
2337 li r6,0
2338 li r7,0
2339 beq- cr1,b4750
2340 blt- b4750
2341
2342 mfspr r4,thrm1
2343 mfspr r5,thrm2
2344 mfspr r6,thrm3
2345 mfspr r7,ictc
2346
2347 b4750: stw r4,(44*4)(r3)
2348 stw r5,(45*4)(r3)
2349 stw r6,(46*4)(r3)
2350 stw r7,(47*4)(r3)
2351
2352 li r4,0
2353 cmplwi r12,PROCESSOR_VERSION_7400
2354 bne nnmax
2355
2356 mfpvr r5
2357 rlwinm r5,r5,0,16,31
2358 cmplwi r5,0x1101
2359 beq gnmax
2360 cmplwi r5,0x1102
2361 bne nnmax
2362
2363 gnmax: mfspr r4,1016
2364
2365 nnmax: stw r4,(48*4)(r3)
2366
2367 mtmsr r0
2368 isync
2369
2370 blr
mirror of XNU