osfmk/i386/cpuid.h

   1 /*
   2  * Copyright (c) 2000-2019 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28 /*
  29  * @OSF_COPYRIGHT@
  30  */
  31
  32 /*
  33  * x86 CPU identification
  34  *
  35  */
  36
  37 #ifndef _MACHINE_CPUID_H_
  38 #define _MACHINE_CPUID_H_
  39
  40 #include <sys/appleapiopts.h>
  41
  42 #if defined(MACH_KERNEL_PRIVATE) && !defined(ASSEMBLER)
  43 #include <i386/hw_defs.h>
  44 #include <i386/pio.h>
  45 #include <i386/machine_routines.h>
  46 #endif
  47
  48 #ifdef __APPLE_API_PRIVATE
  49
  50 #define CPUID_VID_INTEL         "GenuineIntel"
  51 #define CPUID_VID_AMD           "AuthenticAMD"
  52
  53 #define CPUID_VMM_ID_VMWARE             "VMwareVMware"
  54 #define CPUID_VMM_ID_PARALLELS  "Parallels\0\0\0"
  55
  56 #define CPUID_STRING_UNKNOWN    "Unknown CPU Typ"
  57
  58 #define _Bit(n)                 (1ULL << n)
  59 #define _HBit(n)                (1ULL << ((n)+32))
  60
  61 /*
  62  * The CPUID_FEATURE_XXX values define 64-bit values
  63  * returned in %ecx:%edx to a CPUID request with %eax of 1:
  64  */
  65 #define CPUID_FEATURE_FPU       _Bit(0)   /* Floating point unit on-chip */
  66 #define CPUID_FEATURE_VME       _Bit(1)   /* Virtual Mode Extension */
  67 #define CPUID_FEATURE_DE        _Bit(2)   /* Debugging Extension */
  68 #define CPUID_FEATURE_PSE       _Bit(3)   /* Page Size Extension */
  69 #define CPUID_FEATURE_TSC       _Bit(4)   /* Time Stamp Counter */
  70 #define CPUID_FEATURE_MSR       _Bit(5)   /* Model Specific Registers */
  71 #define CPUID_FEATURE_PAE       _Bit(6)   /* Physical Address Extension */
  72 #define CPUID_FEATURE_MCE       _Bit(7)   /* Machine Check Exception */
  73 #define CPUID_FEATURE_CX8       _Bit(8)   /* CMPXCHG8B */
  74 #define CPUID_FEATURE_APIC      _Bit(9)   /* On-chip APIC */
  75 #define CPUID_FEATURE_SEP       _Bit(11)  /* Fast System Call */
  76 #define CPUID_FEATURE_MTRR      _Bit(12)  /* Memory Type Range Register */
  77 #define CPUID_FEATURE_PGE       _Bit(13)  /* Page Global Enable */
  78 #define CPUID_FEATURE_MCA       _Bit(14)  /* Machine Check Architecture */
  79 #define CPUID_FEATURE_CMOV      _Bit(15)  /* Conditional Move Instruction */
  80 #define CPUID_FEATURE_PAT       _Bit(16)  /* Page Attribute Table */
  81 #define CPUID_FEATURE_PSE36     _Bit(17)  /* 36-bit Page Size Extension */
  82 #define CPUID_FEATURE_PSN       _Bit(18)  /* Processor Serial Number */
  83 #define CPUID_FEATURE_CLFSH     _Bit(19)  /* CLFLUSH Instruction supported */
  84 #define CPUID_FEATURE_DS        _Bit(21)  /* Debug Store */
  85 #define CPUID_FEATURE_ACPI      _Bit(22)  /* Thermal monitor and Clock Ctrl */
  86 #define CPUID_FEATURE_MMX       _Bit(23)  /* MMX supported */
  87 #define CPUID_FEATURE_FXSR      _Bit(24)  /* Fast floating pt save/restore */
  88 #define CPUID_FEATURE_SSE       _Bit(25)  /* Streaming SIMD extensions */
  89 #define CPUID_FEATURE_SSE2      _Bit(26)  /* Streaming SIMD extensions 2 */
  90 #define CPUID_FEATURE_SS        _Bit(27)  /* Self-Snoop */
  91 #define CPUID_FEATURE_HTT       _Bit(28)  /* Hyper-Threading Technology */
  92 #define CPUID_FEATURE_TM        _Bit(29)  /* Thermal Monitor (TM1) */
  93 #define CPUID_FEATURE_PBE       _Bit(31)  /* Pend Break Enable */
  94
  95 #define CPUID_FEATURE_SSE3      _HBit(0)  /* Streaming SIMD extensions 3 */
  96 #define CPUID_FEATURE_PCLMULQDQ _HBit(1)  /* PCLMULQDQ instruction */
  97 #define CPUID_FEATURE_DTES64    _HBit(2)  /* 64-bit DS layout */
  98 #define CPUID_FEATURE_MONITOR   _HBit(3)  /* Monitor/mwait */
  99 #define CPUID_FEATURE_DSCPL     _HBit(4)  /* Debug Store CPL */
 100 #define CPUID_FEATURE_VMX       _HBit(5)  /* VMX */
 101 #define CPUID_FEATURE_SMX       _HBit(6)  /* SMX */
 102 #define CPUID_FEATURE_EST       _HBit(7)  /* Enhanced SpeedsTep (GV3) */
 103 #define CPUID_FEATURE_TM2       _HBit(8)  /* Thermal Monitor 2 */
 104 #define CPUID_FEATURE_SSSE3     _HBit(9)  /* Supplemental SSE3 instructions */
 105 #define CPUID_FEATURE_CID       _HBit(10) /* L1 Context ID */
 106 #define CPUID_FEATURE_SEGLIM64  _HBit(11) /* 64-bit segment limit checking */
 107 #define CPUID_FEATURE_FMA       _HBit(12) /* Fused-Multiply-Add support */
 108 #define CPUID_FEATURE_CX16      _HBit(13) /* CmpXchg16b instruction */
 109 #define CPUID_FEATURE_xTPR      _HBit(14) /* Send Task PRiority msgs */
 110 #define CPUID_FEATURE_PDCM      _HBit(15) /* Perf/Debug Capability MSR */
 111
 112 #define CPUID_FEATURE_PCID      _HBit(17) /* ASID-PCID support */
 113 #define CPUID_FEATURE_DCA       _HBit(18) /* Direct Cache Access */
 114 #define CPUID_FEATURE_SSE4_1    _HBit(19) /* Streaming SIMD extensions 4.1 */
 115 #define CPUID_FEATURE_SSE4_2    _HBit(20) /* Streaming SIMD extensions 4.2 */
 116 #define CPUID_FEATURE_x2APIC    _HBit(21) /* Extended APIC Mode */
 117 #define CPUID_FEATURE_MOVBE     _HBit(22) /* MOVBE instruction */
 118 #define CPUID_FEATURE_POPCNT    _HBit(23) /* POPCNT instruction */
 119 #define CPUID_FEATURE_TSCTMR    _HBit(24) /* TSC deadline timer */
 120 #define CPUID_FEATURE_AES       _HBit(25) /* AES instructions */
 121 #define CPUID_FEATURE_XSAVE     _HBit(26) /* XSAVE instructions */
 122 #define CPUID_FEATURE_OSXSAVE   _HBit(27) /* XGETBV/XSETBV instructions */
 123 #define CPUID_FEATURE_AVX1_0    _HBit(28) /* AVX 1.0 instructions */
 124 #define CPUID_FEATURE_F16C      _HBit(29) /* Float16 convert instructions */
 125 #define CPUID_FEATURE_RDRAND    _HBit(30) /* RDRAND instruction */
 126 #define CPUID_FEATURE_VMM       _HBit(31) /* VMM (Hypervisor) present */
 127
 128 /*
 129  * Leaf 7, subleaf 0 additional features.
 130  * Bits returned in %ebx:%ecx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:
 131  */
 132 #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)    /* FS/GS base read/write */
 133 #define CPUID_LEAF7_FEATURE_TSCOFF   _Bit(1)    /* TSC thread offset */
 134 #define CPUID_LEAF7_FEATURE_SGX      _Bit(2)    /* Software Guard eXtensions */
 135 #define CPUID_LEAF7_FEATURE_BMI1     _Bit(3)    /* Bit Manipulation Instrs, set 1 */
 136 #define CPUID_LEAF7_FEATURE_HLE      _Bit(4)    /* Hardware Lock Elision*/
 137 #define CPUID_LEAF7_FEATURE_AVX2     _Bit(5)    /* AVX2 Instructions */
 138 #define CPUID_LEAF7_FEATURE_FDPEO    _Bit(6)    /* x87 FPU Data Pointer updated only on x87 exceptions */
 139 #define CPUID_LEAF7_FEATURE_SMEP     _Bit(7)    /* Supervisor Mode Execute Protect */
 140 #define CPUID_LEAF7_FEATURE_BMI2     _Bit(8)    /* Bit Manipulation Instrs, set 2 */
 141 #define CPUID_LEAF7_FEATURE_ERMS     _Bit(9)    /* Enhanced Rep Movsb/Stosb */
 142 #define CPUID_LEAF7_FEATURE_INVPCID  _Bit(10)   /* INVPCID intruction, TDB */
 143 #define CPUID_LEAF7_FEATURE_RTM      _Bit(11)   /* RTM */
 144 #define CPUID_LEAF7_FEATURE_PQM      _Bit(12)   /* Platform Qos Monitoring */
 145 #define CPUID_LEAF7_FEATURE_FPU_CSDS _Bit(13)   /* FPU CS/DS deprecation */
 146 #define CPUID_LEAF7_FEATURE_MPX      _Bit(14)   /* Memory Protection eXtensions */
 147 #define CPUID_LEAF7_FEATURE_PQE      _Bit(15)   /* Platform Qos Enforcement */
 148 #define CPUID_LEAF7_FEATURE_AVX512F  _Bit(16)   /* AVX512F instructions */
 149 #define CPUID_LEAF7_FEATURE_AVX512DQ _Bit(17)   /* AVX512DQ instructions */
 150 #define CPUID_LEAF7_FEATURE_RDSEED   _Bit(18)   /* RDSEED Instruction */
 151 #define CPUID_LEAF7_FEATURE_ADX      _Bit(19)   /* ADX Instructions */
 152 #define CPUID_LEAF7_FEATURE_SMAP     _Bit(20)   /* Supervisor Mode Access Protect */
 153 #define CPUID_LEAF7_FEATURE_AVX512IFMA _Bit(21) /* AVX512IFMA instructions */
 154 #define CPUID_LEAF7_FEATURE_CLFSOPT  _Bit(23)   /* CLFSOPT */
 155 #define CPUID_LEAF7_FEATURE_CLWB     _Bit(24)   /* CLWB */
 156 #define CPUID_LEAF7_FEATURE_IPT      _Bit(25)   /* Intel Processor Trace */
 157 #define CPUID_LEAF7_FEATURE_AVX512CD _Bit(28)   /* AVX512CD instructions */
 158 #define CPUID_LEAF7_FEATURE_SHA      _Bit(29)   /* SHA instructions */
 159 #define CPUID_LEAF7_FEATURE_AVX512BW _Bit(30)   /* AVX512BW instructions */
 160 #define CPUID_LEAF7_FEATURE_AVX512VL _Bit(31)   /* AVX512VL instructions */
 161
 162 #define CPUID_LEAF7_FEATURE_PREFETCHWT1 _HBit(0)/* Prefetch Write/T1 hint */
 163 #define CPUID_LEAF7_FEATURE_AVX512VBMI  _HBit(1)/* AVX512VBMI instructions */
 164 #define CPUID_LEAF7_FEATURE_UMIP        _HBit(2) /* User Mode Instruction Prevention */
 165 #define CPUID_LEAF7_FEATURE_PKU         _HBit(3) /* Protection Keys for Usermode */
 166 #define CPUID_LEAF7_FEATURE_OSPKE       _HBit(4) /* OS has enabled PKE */
 167 #define CPUID_LEAF7_FEATURE_WAITPKG     _HBit(5) /* WAITPKG instructions */
 168 #define CPUID_LEAF7_FEATURE_GFNI        _HBit(8) /* Galois Field New Instructions */
 169 #define CPUID_LEAF7_FEATURE_AVX512VPCDQ _HBit(14) /* AVX512 VPOPCNTDQ instruction */
 170 #define CPUID_LEAF7_FEATURE_RDPID       _HBit(22) /* RDPID and IA32_TSC_AUX */
 171 #define CPUID_LEAF7_FEATURE_CLDEMOTE    _HBit(25) /* Cache line demote */
 172 #define CPUID_LEAF7_FEATURE_MOVDIRI     _HBit(27) /* MOVDIRI instruction */
 173 #define CPUID_LEAF7_FEATURE_MOVDIRI64B  _HBit(28) /* MOVDIRI64B instruction */
 174 #define CPUID_LEAF7_FEATURE_SGXLC       _HBit(30) /* SGX Launch Configuration */
 175
 176 /*
 177  * Values in EDX returned by CPUID Leaf 7, subleaf 0
 178  */
 179 #define CPUID_LEAF7_EXTFEATURE_AVX5124VNNIW     _Bit(2)         /* AVX512_4VNNIW */
 180 #define CPUID_LEAF7_EXTFEATURE_AVX5124FMAPS     _Bit(3)         /* AVX512_4FMAPS */
 181 #define CPUID_LEAF7_EXTFEATURE_MDCLEAR          _Bit(10)        /* Overloaded VERW / L1D_FLUSH */
 182 #define CPUID_LEAF7_EXTFEATURE_TSXFA            _Bit(13)        /* TSX RTM_FORCE_ABORT MSR */
 183 #define CPUID_LEAF7_EXTFEATURE_IBRS             _Bit(26)        /* IBRS / IBPB */
 184 #define CPUID_LEAF7_EXTFEATURE_STIBP            _Bit(27)        /* Single Thread Indirect Branch Predictors */
 185 #define CPUID_LEAF7_EXTFEATURE_L1DF             _Bit(28)        /* L1D_FLUSH MSR */
 186 #define CPUID_LEAF7_EXTFEATURE_ACAPMSR          _Bit(29)        /* ARCH_CAP MSR */
 187 #define CPUID_LEAF7_EXTFEATURE_CCAPMSR          _Bit(30)        /* CORE_CAP MSR */
 188 #define CPUID_LEAF7_EXTFEATURE_SSBD             _Bit(31)        /* Speculative Store Bypass Disable */
 189
 190 /*
 191  * The CPUID_EXTFEATURE_XXX values define 64-bit values
 192  * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001:
 193  */
 194 #define CPUID_EXTFEATURE_SYSCALL   _Bit(11)     /* SYSCALL/sysret */
 195 #define CPUID_EXTFEATURE_XD        _Bit(20)     /* eXecute Disable */
 196
 197 #define CPUID_EXTFEATURE_1GBPAGE   _Bit(26)     /* 1GB pages */
 198 #define CPUID_EXTFEATURE_RDTSCP    _Bit(27)     /* RDTSCP */
 199 #define CPUID_EXTFEATURE_EM64T     _Bit(29)     /* Extended Mem 64 Technology */
 200
 201 #define CPUID_EXTFEATURE_LAHF      _HBit(0)     /* LAFH/SAHF instructions */
 202 #define CPUID_EXTFEATURE_LZCNT     _HBit(5)     /* LZCNT instruction */
 203 #define CPUID_EXTFEATURE_PREFETCHW _HBit(8)     /* PREFETCHW instruction */
 204
 205 /*
 206  * The CPUID_EXTFEATURE_XXX values define 64-bit values
 207  * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007:
 208  */
 209 #define CPUID_EXTFEATURE_TSCI      _Bit(8)      /* TSC Invariant */
 210
 211 /*
 212  * CPUID_X86_64_H_FEATURE_SUBSET and CPUID_X86_64_H_LEAF7_FEATURE_SUBSET
 213  * indicate the bitmask of features that must be present before the system
 214  * is eligible to run the "x86_64h" "Haswell feature subset" slice.
 215  */
 216 #define CPUID_X86_64_H_FEATURE_SUBSET ( CPUID_FEATURE_FMA    | \
 217                                         CPUID_FEATURE_SSE4_2 | \
 218                                         CPUID_FEATURE_MOVBE  | \
 219                                         CPUID_FEATURE_POPCNT | \
 220                                         CPUID_FEATURE_AVX1_0   \
 221                                       )
 222
 223 #define CPUID_X86_64_H_EXTFEATURE_SUBSET ( CPUID_EXTFEATURE_LZCNT \
 224                                          )
 225
 226 #define CPUID_X86_64_H_LEAF7_FEATURE_SUBSET ( CPUID_LEAF7_FEATURE_BMI1 | \
 227                                               CPUID_LEAF7_FEATURE_AVX2 | \
 228                                               CPUID_LEAF7_FEATURE_BMI2   \
 229                                             )
 230
 231 #define CPUID_CACHE_SIZE        16      /* Number of descriptor values */
 232
 233 #define CPUID_MWAIT_EXTENSION   _Bit(0) /* enumeration of WMAIT extensions */
 234 #define CPUID_MWAIT_BREAK       _Bit(1) /* interrupts are break events     */
 235
 236 #define CPUID_MODEL_PENRYN              0x17
 237 #define CPUID_MODEL_NEHALEM             0x1A
 238 #define CPUID_MODEL_FIELDS              0x1E    /* Lynnfield, Clarksfield */
 239 #define CPUID_MODEL_DALES               0x1F    /* Havendale, Auburndale */
 240 #define CPUID_MODEL_NEHALEM_EX          0x2E
 241 #define CPUID_MODEL_DALES_32NM          0x25    /* Clarkdale, Arrandale */
 242 #define CPUID_MODEL_WESTMERE            0x2C    /* Gulftown, Westmere-EP/-WS */
 243 #define CPUID_MODEL_WESTMERE_EX         0x2F
 244 #define CPUID_MODEL_SANDYBRIDGE         0x2A
 245 #define CPUID_MODEL_JAKETOWN            0x2D
 246 #define CPUID_MODEL_IVYBRIDGE           0x3A
 247 #define CPUID_MODEL_IVYBRIDGE_EP        0x3E
 248 #define CPUID_MODEL_CRYSTALWELL         0x46
 249 #define CPUID_MODEL_HASWELL             0x3C
 250 #define CPUID_MODEL_HASWELL_EP          0x3F
 251 #define CPUID_MODEL_HASWELL_ULT         0x45
 252 #define CPUID_MODEL_BROADWELL           0x3D
 253 #define CPUID_MODEL_BROADWELL_ULX       0x3D
 254 #define CPUID_MODEL_BROADWELL_ULT       0x3D
 255 #define CPUID_MODEL_BRYSTALWELL         0x47
 256 #define CPUID_MODEL_SKYLAKE             0x4E
 257 #define CPUID_MODEL_SKYLAKE_ULT         0x4E
 258 #define CPUID_MODEL_SKYLAKE_ULX         0x4E
 259 #define CPUID_MODEL_SKYLAKE_DT          0x5E
 260 #if !defined(RC_HIDE_XNU_J137)
 261 #define CPUID_MODEL_SKYLAKE_W           0x55
 262 #define PLATID_XEON_SP_1                0x00
 263 #define PLATID_XEON_SP_2                0x07
 264 #define PLATID_MAYBE_XEON_SP            0x01
 265 #endif /* not RC_HIDE_XNU_J137 */
 266 #define CPUID_MODEL_KABYLAKE            0x8E
 267 #define CPUID_MODEL_KABYLAKE_ULT        0x8E
 268 #define CPUID_MODEL_KABYLAKE_ULX        0x8E
 269 #define CPUID_MODEL_KABYLAKE_DT         0x9E
 270
 271 #define CPUID_VMM_FAMILY_UNKNOWN        0x0
 272 #define CPUID_VMM_FAMILY_VMWARE         0x1
 273 #define CPUID_VMM_FAMILY_PARALLELS      0x2
 274
 275 #ifndef ASSEMBLER
 276 #include <stdint.h>
 277 #include <mach/mach_types.h>
 278 #include <kern/kern_types.h>
 279 #include <mach/machine.h>
 280
 281
 282 typedef enum { eax, ebx, ecx, edx } cpuid_register_t;
 283 static inline void
 284 cpuid(uint32_t *data)
 285 {
 286         __asm__ volatile ("cpuid"
 287                 : "=a" (data[eax]),
 288                   "=b" (data[ebx]),
 289                   "=c" (data[ecx]),
 290                   "=d" (data[edx])
 291                 : "a"  (data[eax]),
 292                   "b"  (data[ebx]),
 293                   "c"  (data[ecx]),
 294                   "d"  (data[edx]));
 295 }
 296
 297 static inline void
 298 do_cpuid(uint32_t selector, uint32_t *data)
 299 {
 300         __asm__ volatile ("cpuid"
 301                 : "=a" (data[0]),
 302                   "=b" (data[1]),
 303                   "=c" (data[2]),
 304                   "=d" (data[3])
 305                 : "a"(selector),
 306                   "b" (0),
 307                   "c" (0),
 308                   "d" (0));
 309 }
 310
 311 /*
 312  * Cache ID descriptor structure, used to parse CPUID leaf 2.
 313  * Note: not used in kernel.
 314  */
 315 typedef enum { Lnone, L1I, L1D, L2U, L3U, LCACHE_MAX } cache_type_t;
 316 typedef struct {
 317         unsigned char   value;          /* Descriptor value */
 318         cache_type_t    type;           /* Cache type */
 319         unsigned int    size;           /* Cache size */
 320         unsigned int    linesize;       /* Cache line size */
 321 #ifdef KERNEL
 322         const char      *description;   /* Cache description */
 323 #endif /* KERNEL */
 324 } cpuid_cache_desc_t;
 325
 326 #ifdef KERNEL
 327 #define CACHE_DESC(value, type, size, linesize, text) \
 328         { value, type, size, linesize, text }
 329 #else
 330 #define CACHE_DESC(value, type, size, linesize, text) \
 331         { value, type, size, linesize }
 332 #endif /* KERNEL */
 333
 334 /* Monitor/mwait Leaf: */
 335 typedef struct {
 336         uint32_t        linesize_min;
 337         uint32_t        linesize_max;
 338         uint32_t        extensions;
 339         uint32_t        sub_Cstates;
 340 } cpuid_mwait_leaf_t;
 341
 342 /* Thermal and Power Management Leaf: */
 343 typedef struct {
 344         boolean_t       sensor;
 345         boolean_t       dynamic_acceleration;
 346         boolean_t       invariant_APIC_timer;
 347         boolean_t       core_power_limits;
 348         boolean_t       fine_grain_clock_mod;
 349         boolean_t       package_thermal_intr;
 350         uint32_t        thresholds;
 351         boolean_t       ACNT_MCNT;
 352         boolean_t       hardware_feedback;
 353         boolean_t       energy_policy;
 354 } cpuid_thermal_leaf_t;
 355
 356
 357 /* XSAVE Feature Leaf: */
 358 typedef struct {
 359         uint32_t        extended_state[4];      /* eax .. edx */
 360 } cpuid_xsave_leaf_t;
 361
 362
 363 /* Architectural Performance Monitoring Leaf: */
 364 typedef struct {
 365         uint8_t         version;
 366         uint8_t         number;
 367         uint8_t         width;
 368         uint8_t         events_number;
 369         uint32_t        events;
 370         uint8_t         fixed_number;
 371         uint8_t         fixed_width;
 372 } cpuid_arch_perf_leaf_t;
 373
 374 /* The TSC to Core Crystal (RefCLK) Clock Information leaf */
 375 typedef struct {
 376         uint32_t        numerator;
 377         uint32_t        denominator;
 378 } cpuid_tsc_leaf_t;
 379
 380 /* Physical CPU info - this is exported out of the kernel (kexts), so be wary of changes */
 381 typedef struct {
 382         char            cpuid_vendor[16];
 383         char            cpuid_brand_string[48];
 384         const char      *cpuid_model_string;
 385
 386         cpu_type_t      cpuid_type;     /* this is *not* a cpu_type_t in our <mach/machine.h> */
 387         uint8_t         cpuid_family;
 388         uint8_t         cpuid_model;
 389         uint8_t         cpuid_extmodel;
 390         uint8_t         cpuid_extfamily;
 391         uint8_t         cpuid_stepping;
 392         uint64_t        cpuid_features;
 393         uint64_t        cpuid_extfeatures;
 394         uint32_t        cpuid_signature;
 395         uint8_t         cpuid_brand;
 396         uint8_t         cpuid_processor_flag;
 397
 398         uint32_t        cache_size[LCACHE_MAX];
 399         uint32_t        cache_linesize;
 400
 401         uint8_t         cache_info[64];    /* list of cache descriptors */
 402
 403         uint32_t        cpuid_cores_per_package;
 404         uint32_t        cpuid_logical_per_package;
 405         uint32_t        cache_sharing[LCACHE_MAX];
 406         uint32_t        cache_partitions[LCACHE_MAX];
 407
 408         cpu_type_t      cpuid_cpu_type;                 /* <mach/machine.h> */
 409         cpu_subtype_t   cpuid_cpu_subtype;              /* <mach/machine.h> */
 410
 411         /* Per-vendor info */
 412         cpuid_mwait_leaf_t      cpuid_mwait_leaf;
 413 #define cpuid_mwait_linesize_max        cpuid_mwait_leaf.linesize_max
 414 #define cpuid_mwait_linesize_min        cpuid_mwait_leaf.linesize_min
 415 #define cpuid_mwait_extensions          cpuid_mwait_leaf.extensions
 416 #define cpuid_mwait_sub_Cstates         cpuid_mwait_leaf.sub_Cstates
 417         cpuid_thermal_leaf_t    cpuid_thermal_leaf;
 418         cpuid_arch_perf_leaf_t  cpuid_arch_perf_leaf;
 419         uint32_t        unused[4];                      /* cpuid_xsave_leaf */
 420
 421         /* Cache details: */
 422         uint32_t        cpuid_cache_linesize;
 423         uint32_t        cpuid_cache_L2_associativity;
 424         uint32_t        cpuid_cache_size;
 425
 426         /* Virtual and physical address aize: */
 427         uint32_t        cpuid_address_bits_physical;
 428         uint32_t        cpuid_address_bits_virtual;
 429
 430         uint32_t        cpuid_microcode_version;
 431
 432         /* Numbers of tlbs per processor [i|d, small|large, level0|level1] */
 433         uint32_t        cpuid_tlb[2][2][2];
 434                         #define TLB_INST        0
 435                         #define TLB_DATA        1
 436                         #define TLB_SMALL       0
 437                         #define TLB_LARGE       1
 438         uint32_t        cpuid_stlb;
 439
 440         uint32_t        core_count;
 441         uint32_t        thread_count;
 442
 443         /* Max leaf ids available from CPUID */
 444         uint32_t        cpuid_max_basic;
 445         uint32_t        cpuid_max_ext;
 446
 447         /* Family-specific info links */
 448         uint32_t                cpuid_cpufamily;
 449         cpuid_mwait_leaf_t      *cpuid_mwait_leafp;
 450         cpuid_thermal_leaf_t    *cpuid_thermal_leafp;
 451         cpuid_arch_perf_leaf_t  *cpuid_arch_perf_leafp;
 452         cpuid_xsave_leaf_t      *cpuid_xsave_leafp;
 453         uint64_t                cpuid_leaf7_features;
 454         uint64_t                cpuid_leaf7_extfeatures;
 455         cpuid_tsc_leaf_t        cpuid_tsc_leaf;
 456         cpuid_xsave_leaf_t      cpuid_xsave_leaf[2];
 457 } i386_cpu_info_t;
 458
 459 #if defined(MACH_KERNEL_PRIVATE) && !defined(ASSEMBLER)
 460 /* Only for 32bit values */
 461 #define bit32(n)                (1U << (n))
 462 #define bitmask32(h, l)          ((bit32(h)|(bit32(h)-1)) & ~(bit32(l)-1))
 463 #define bitfield32(x, h, l)       ((((x) & bitmask32(h,l)) >> l))
 464
 465 typedef struct {
 466         char            cpuid_vmm_vendor[16];
 467         uint32_t        cpuid_vmm_family;
 468         uint32_t        cpuid_vmm_bus_frequency;
 469         uint32_t        cpuid_vmm_tsc_frequency;
 470 } i386_vmm_info_t;
 471
 472 typedef enum {
 473         CPU_INTEL_SEGCHK = 1,
 474         CPU_INTEL_TSXFA
 475 } cpu_wa_e;
 476
 477 typedef enum {
 478         CWA_ON = 2,
 479         CWA_FORCE_ON = 3,       /* FORCE_ON shares bit 1 so consumers can test that for ON */
 480         CWA_OFF = 4,
 481         CWA_FORCE_OFF = 5       /* Similarly for FORCE_OFF sharing bit 2 */
 482 } cwa_classifier_e;
 483
 484 static inline int
 485 is_xeon_sp(uint8_t platid)
 486 {
 487         if (platid == PLATID_XEON_SP_1 || platid == PLATID_XEON_SP_2) {
 488                 return 1;
 489         }
 490         if (platid != PLATID_MAYBE_XEON_SP) {
 491                 return 0;
 492         }
 493         boolean_t intrs = ml_set_interrupts_enabled(FALSE);
 494         outl(cfgAdr, XeonCapID5);
 495         uint32_t cap5reg = inl(cfgDat);
 496         ml_set_interrupts_enabled(intrs);
 497         /* Read from PCI config space 1:30:3:0x98 [bits 13:9] */
 498         if (bitfield32(cap5reg, 13, 9) == 3) {
 499                 return 1;
 500         }
 501         return 0;
 502 }
 503
 504 extern int force_tecs_at_idle;
 505
 506 #endif /* defined(MACH_KERNEL_PRIVATE) && !defined(ASSEMBLER) */
 507
 508 #ifdef __cplusplus
 509 extern "C" {
 510 #endif
 511
 512 /*
 513  * External declarations
 514  */
 515 extern cpu_type_t       cpuid_cputype(void);
 516 extern cpu_subtype_t    cpuid_cpusubtype(void);
 517 extern void             cpuid_cpu_display(const char *);
 518 extern void             cpuid_feature_display(const char *);
 519 extern void             cpuid_extfeature_display(const char *);
 520 extern char *           cpuid_get_feature_names(uint64_t, char *, unsigned);
 521 extern char *           cpuid_get_extfeature_names(uint64_t, char *, unsigned);
 522 extern char *           cpuid_get_leaf7_feature_names(uint64_t, char *, unsigned);
 523 extern char *           cpuid_get_leaf7_extfeature_names(uint64_t, char *, unsigned);
 524
 525 extern uint64_t         cpuid_features(void);
 526 extern uint64_t         cpuid_extfeatures(void);
 527 extern uint64_t         cpuid_leaf7_features(void);
 528 extern uint64_t         cpuid_leaf7_extfeatures(void);
 529 extern uint32_t         cpuid_family(void);
 530 extern uint32_t         cpuid_cpufamily(void);
 531
 532 extern i386_cpu_info_t  *cpuid_info(void);
 533 extern void             cpuid_set_info(void);
 534
 535 #ifdef MACH_KERNEL_PRIVATE
 536 extern boolean_t        cpuid_vmm_present(void);
 537 extern i386_vmm_info_t  *cpuid_vmm_info(void);
 538 extern uint32_t         cpuid_vmm_family(void);
 539 extern cwa_classifier_e cpuid_wa_required(cpu_wa_e wa);
 540 extern void cpuid_do_was(void);
 541 #endif
 542
 543 #ifdef __cplusplus
 544 }
 545 #endif
 546
 547 #endif /* ASSEMBLER */
 548
 549 #endif /* __APPLE_API_PRIVATE */
 550 #endif /* _MACHINE_CPUID_H_ */