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31 #include <ppc/proc_reg.h>
34 #include <mach/ppc/vm_param.h>
35 #include <ppc/exception.h>
39 * ml_set_physical() -- turn off DR and (if 64-bit) turn SF on
40 * it is assumed that pf64Bit is already in cr6
41 * ml_set_physical_get_ffs() -- turn DR off, SF on, and get feature flags
42 * ml_set_physical_disabled() -- turn DR and EE off, SF on, get feature flags
43 * ml_set_translation_off() -- turn DR, IR, and EE off, SF on, get feature flags
45 * Callable only from assembler, these return:
48 * r10 -- feature flags (pf64Bit etc, ie SPRG 2)
49 * cr6 -- feature flags 24-27, ie pf64Bit, pf128Byte, and pf32Byte
51 * Uses r0 and r2. ml_set_translation_off also uses r3 and cr5.
55 .globl EXT(ml_set_translation_off)
56 LEXT(ml_set_translation_off)
57 mfsprg r10,2 // get feature flags
59 mtcrf 0x02,r10 // move pf64Bit etc to cr6
60 ori r0,r0,lo16(MASK(MSR_EE)+MASK(MSR_FP)+MASK(MSR_IR)+MASK(MSR_DR)) // turn off all 4
62 oris r0,r0,hi16(MASK(MSR_VEC)) // Turn off vector too
63 mtcrf 0x04,r10 // move pfNoMSRir etc to cr5
64 andc r2,r11,r0 // turn off EE, IR, and DR
65 bt++ pf64Bitb,ml_set_physical_64 // skip if 64-bit (only they take the hint)
66 bf pfNoMSRirb,ml_set_physical_32 // skip if we can load MSR directly
67 li r0,loadMSR // Get the MSR setter SC
68 mr r3,r2 // copy new MSR to r2
73 .globl EXT(ml_set_physical_disabled)
75 LEXT(ml_set_physical_disabled)
77 mfsprg r10,2 // get feature flags
78 ori r0,r0,lo16(MASK(MSR_EE)) // turn EE and fp off
79 mtcrf 0x02,r10 // move pf64Bit etc to cr6
80 b ml_set_physical_join
83 .globl EXT(ml_set_physical_get_ffs)
85 LEXT(ml_set_physical_get_ffs)
86 mfsprg r10,2 // get feature flags
87 mtcrf 0x02,r10 // move pf64Bit etc to cr6
89 .globl EXT(ml_set_physical)
92 li r0,0 // do not turn off interrupts
95 oris r0,r0,hi16(MASK(MSR_VEC)) // Always gonna turn of vectors
97 ori r0,r0,lo16(MASK(MSR_DR)+MASK(MSR_FP)) // always turn off DR and FP bit
98 andc r2,r11,r0 // turn off DR and maybe EE
99 bt++ pf64Bitb,ml_set_physical_64 // skip if 64-bit (only they take the hint)
101 mtmsr r2 // turn off translation
106 li r0,1 // get a 1 to slam into SF
107 rldimi r2,r0,63,MSR_SF_BIT // set SF bit (bit 0)
108 mtmsrd r2 // set 64-bit mode, turn off data relocation
114 * ml_restore(old_MSR)
116 * Callable only from assembler, restores the MSR in r11 saved by ml_set_physical.
117 * We assume cr6 and r11 are as set by ml_set_physical, ie:
118 * cr6 - pf64Bit flag (feature flags 24-27)
123 .globl EXT(ml_restore)
126 bt++ pf64Bitb,ml_restore_64 // handle 64-bit cpus (only they take the hint)
127 mtmsr r11 // restore a 32-bit MSR
132 mtmsrd r11 // restore a 64-bit MSR
137 /* PCI config cycle probing
139 * boolean_t ml_probe_read(vm_offset_t paddr, unsigned int *val)
141 * Read the memory location at physical address paddr.
142 * This is a part of a device probe, so there is a good chance we will
143 * have a machine check here. So we have to be able to handle that.
144 * We assume that machine checks are enabled both in MSR and HIDs
147 ; Force a line boundry here
149 .globl EXT(ml_probe_read)
153 mfsprg r9,2 ; Get feature flags
155 rlwinm. r0,r9,0,pf64Bitb,pf64Bitb ; Are we on a 64-bit machine?
156 rlwinm r3,r3,0,0,31 ; Clean up for 64-bit machines
157 bne++ mpr64bit ; Go do this the 64-bit way...
159 mpr32bit: lis r8,hi16(MASK(MSR_VEC)) ; Get the vector flag
160 mfmsr r0 ; Save the current MSR
161 ori r8,r8,lo16(MASK(MSR_FP)) ; Add the FP flag
163 neg r10,r3 ; Number of bytes to end of page
164 andc r0,r0,r8 ; Clear VEC and FP
165 rlwinm. r10,r10,0,20,31 ; Clear excess junk and test for page bndry
166 ori r8,r8,lo16(MASK(MSR_EE)|MASK(MSR_IR)|MASK(MSR_DR)) ; Drop EE, IR, and DR
167 mr r12,r3 ; Save the load address
168 andc r2,r0,r8 ; Clear VEC, FP, and EE
169 mtcrf 0x04,r9 ; Set the features
170 cmplwi cr1,r10,4 ; At least 4 bytes left in page?
171 beq- mprdoit ; We are right on the boundary...
173 bltlr- cr1 ; No, just return failure...
177 bt pfNoMSRirb,mprNoMSR ; No MSR...
179 mtmsr r2 ; Translation and all off
180 isync ; Toss prefetch
185 li r0,loadMSR ; Get the MSR setter SC
186 mr r3,r2 ; Get new MSR
192 mfspr r6, hid0 ; Get a copy of hid0
194 rlwinm. r5, r9, 0, pfNoMuMMCKb, pfNoMuMMCKb ; Check for NoMuMMCK
197 rlwinm r5, r6, 0, ice+1, ice-1 ; Turn off L1 I-Cache
199 isync ; Wait for I-Cache off
200 rlwinm r5, r6, 0, mum+1, mum-1 ; Turn off MuM w/ I-Cache on
205 ; We need to insure that there is no more than 1 BAT register that
206 ; can get a hit. There could be repercussions beyond the ken
207 ; of mortal man. It is best not to tempt fate.
210 ; Note: we will reload these from the shadow BATs later
212 li r10,0 ; Clear a register
214 sync ; Make sure all is well
216 mtdbatu 1,r10 ; Invalidate DBAT 1
217 mtdbatu 2,r10 ; Invalidate DBAT 2
218 mtdbatu 3,r10 ; Invalidate DBAT 3
220 rlwinm r10,r12,0,0,14 ; Round down to a 128k boundary
221 ori r11,r10,0x32 ; Set uncached, coherent, R/W
222 ori r10,r10,2 ; Make the upper half (128k, valid supervisor)
223 mtdbatl 0,r11 ; Set lower BAT first
224 mtdbatu 0,r10 ; Now the upper
225 sync ; Just make sure
227 dcbf 0,r12 ; Make sure we kill the cache to avoid paradoxes
230 ori r11,r2,lo16(MASK(MSR_DR)) ; Turn on data translation
231 mtmsr r11 ; Do it for real
232 isync ; Make sure of it
234 eieio ; Make sure of all previous accesses
235 sync ; Make sure it is all caught up
237 lwz r11,0(r12) ; Get it and maybe machine check here
239 eieio ; Make sure of ordering again
240 sync ; Get caught up yet again
241 isync ; Do not go further till we are here
243 mtmsr r2 ; Turn translation back off
246 lis r10,hi16(EXT(shadow_BAT)+shdDBAT) ; Get shadow address
247 ori r10,r10,lo16(EXT(shadow_BAT)+shdDBAT) ; Get shadow address
249 lwz r5,0(r10) ; Pick up DBAT 0 high
250 lwz r6,4(r10) ; Pick up DBAT 0 low
251 lwz r7,8(r10) ; Pick up DBAT 1 high
252 lwz r8,16(r10) ; Pick up DBAT 2 high
253 lwz r9,24(r10) ; Pick up DBAT 3 high
255 mtdbatu 0,r5 ; Restore DBAT 0 high
256 mtdbatl 0,r6 ; Restore DBAT 0 low
257 mtdbatu 1,r7 ; Restore DBAT 1 high
258 mtdbatu 2,r8 ; Restore DBAT 2 high
259 mtdbatu 3,r9 ; Restore DBAT 3 high
264 mtmsr r0 ; Restore translation and exceptions
265 isync ; Toss speculations
267 stw r11,0(r4) ; Save the loaded value
270 ; Force a line boundry here. This means we will be able to check addresses better
272 .globl EXT(ml_probe_read_mck)
273 LEXT(ml_probe_read_mck)
276 /* PCI config cycle probing - 64-bit
278 * boolean_t ml_probe_read_64(addr64_t paddr, unsigned int *val)
280 * Read the memory location at physical address paddr.
281 * This is a part of a device probe, so there is a good chance we will
282 * have a machine check here. So we have to be able to handle that.
283 * We assume that machine checks are enabled both in MSR and HIDs
286 ; Force a line boundry here
288 .globl EXT(ml_probe_read_64)
290 LEXT(ml_probe_read_64)
292 mfsprg r9,2 ; Get feature flags
293 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
294 rlwinm. r0,r9,0,pf64Bitb,pf64Bitb ; Are we on a 64-bit machine?
295 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
297 mr r4,r5 ; Move result to common register
298 beq-- mpr32bit ; Go do this the 32-bit way...
300 mpr64bit: andi. r0,r3,3 ; Check if we are on a word boundary
301 li r0,0 ; Clear the EE bit (and everything else for that matter)
302 bne-- mprFail ; Boundary not good...
303 mfmsr r11 ; Get the MSR
304 mtmsrd r0,1 ; Set the EE bit only (do not care about RI)
305 rlwinm r11,r11,0,MSR_EE_BIT,MSR_EE_BIT ; Isolate just the EE bit
306 mfmsr r10 ; Refresh our view of the MSR (VMX/FP may have changed)
307 or r12,r10,r11 ; Turn on EE if on before we turned it off
308 ori r0,r0,lo16(MASK(MSR_IR)|MASK(MSR_DR)) ; Get the IR and DR bits
310 sldi r2,r2,63 ; Get the 64-bit bit
311 andc r10,r10,r0 ; Clear IR and DR
312 or r10,r10,r2 ; Set 64-bit
315 mtmsrd r10 ; Translation and EE off, 64-bit on
318 sldi r0,r0,32+8 ; Get the right bit to inhibit caching
320 mfspr r8,hid4 ; Get HID4
321 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
323 mtspr hid4,r2 ; Make real accesses cache-inhibited
324 isync ; Toss prefetches
326 lis r7,0xE000 ; Get the unlikeliest ESID possible
327 srdi r7,r7,1 ; Make 0x7FFFFFFFF0000000
328 slbie r7 ; Make sure the ERAT is cleared
333 eieio ; Make sure of all previous accesses
335 lwz r11,0(r3) ; Get it and maybe machine check here
337 eieio ; Make sure of ordering again
338 sync ; Get caught up yet again
339 isync ; Do not go further till we are here
342 mtspr hid4,r8 ; Make real accesses not cache-inhibited
343 isync ; Toss prefetches
345 lis r7,0xE000 ; Get the unlikeliest ESID possible
346 srdi r7,r7,1 ; Make 0x7FFFFFFFF0000000
347 slbie r7 ; Make sure the ERAT is cleared
349 mtmsrd r12 ; Restore entry MSR
352 stw r11,0(r4) ; Pass back the result
353 li r3,1 ; Indicate success
356 mprFail: li r3,0 ; Set failure
359 ; Force a line boundry here. This means we will be able to check addresses better
361 .globl EXT(ml_probe_read_mck_64)
362 LEXT(ml_probe_read_mck_64)
365 /* Read physical address byte
367 * unsigned int ml_phys_read_byte(vm_offset_t paddr)
368 * unsigned int ml_phys_read_byte_64(addr64_t paddr)
370 * Read the byte at physical address paddr. Memory should not be cache inhibited.
373 ; Force a line boundry here
376 .globl EXT(ml_phys_read_byte_64)
378 LEXT(ml_phys_read_byte_64)
380 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
381 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
382 b ml_phys_read_byte_join
384 .globl EXT(ml_phys_read_byte)
386 LEXT(ml_phys_read_byte)
387 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
388 ml_phys_read_byte_join: ; r3 = address to read (reg64_t)
389 mflr r11 ; Save the return
390 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
392 lbz r3,0(r3) ; Get the byte
393 b rdwrpost ; Clean up and leave...
396 /* Read physical address half word
398 * unsigned int ml_phys_read_half(vm_offset_t paddr)
399 * unsigned int ml_phys_read_half_64(addr64_t paddr)
401 * Read the half word at physical address paddr. Memory should not be cache inhibited.
404 ; Force a line boundry here
407 .globl EXT(ml_phys_read_half_64)
409 LEXT(ml_phys_read_half_64)
411 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
412 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
413 b ml_phys_read_half_join
415 .globl EXT(ml_phys_read_half)
417 LEXT(ml_phys_read_half)
418 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
419 ml_phys_read_half_join: ; r3 = address to read (reg64_t)
420 mflr r11 ; Save the return
421 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
423 lhz r3,0(r3) ; Get the half word
424 b rdwrpost ; Clean up and leave...
427 /* Read physical address word
429 * unsigned int ml_phys_read(vm_offset_t paddr)
430 * unsigned int ml_phys_read_64(addr64_t paddr)
431 * unsigned int ml_phys_read_word(vm_offset_t paddr)
432 * unsigned int ml_phys_read_word_64(addr64_t paddr)
434 * Read the word at physical address paddr. Memory should not be cache inhibited.
437 ; Force a line boundry here
440 .globl EXT(ml_phys_read_64)
441 .globl EXT(ml_phys_read_word_64)
443 LEXT(ml_phys_read_64)
444 LEXT(ml_phys_read_word_64)
446 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
447 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
448 b ml_phys_read_word_join
450 .globl EXT(ml_phys_read)
451 .globl EXT(ml_phys_read_word)
454 LEXT(ml_phys_read_word)
455 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
456 ml_phys_read_word_join: ; r3 = address to read (reg64_t)
457 mflr r11 ; Save the return
458 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
460 lwz r3,0(r3) ; Get the word
461 b rdwrpost ; Clean up and leave...
464 /* Read physical address double word
466 * unsigned long long ml_phys_read_double(vm_offset_t paddr)
467 * unsigned long long ml_phys_read_double_64(addr64_t paddr)
469 * Read the double word at physical address paddr. Memory should not be cache inhibited.
472 ; Force a line boundry here
475 .globl EXT(ml_phys_read_double_64)
477 LEXT(ml_phys_read_double_64)
479 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
480 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
481 b ml_phys_read_double_join
483 .globl EXT(ml_phys_read_double)
485 LEXT(ml_phys_read_double)
486 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
487 ml_phys_read_double_join: ; r3 = address to read (reg64_t)
488 mflr r11 ; Save the return
489 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
491 lwz r4,4(r3) ; Get the low word
492 lwz r3,0(r3) ; Get the high word
493 b rdwrpost ; Clean up and leave...
496 /* Write physical address byte
498 * void ml_phys_write_byte(vm_offset_t paddr, unsigned int data)
499 * void ml_phys_write_byte_64(addr64_t paddr, unsigned int data)
501 * Write the byte at physical address paddr. Memory should not be cache inhibited.
505 .globl EXT(ml_phys_write_byte_64)
507 LEXT(ml_phys_write_byte_64)
509 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
510 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
511 mr r4,r5 ; Copy over the data
512 b ml_phys_write_byte_join
514 .globl EXT(ml_phys_write_byte)
516 LEXT(ml_phys_write_byte)
517 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
518 ml_phys_write_byte_join: ; r3 = address to write (reg64_t), r4 = data
519 mflr r11 ; Save the return
520 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
522 stb r4,0(r3) ; Set the byte
523 b rdwrpost ; Clean up and leave...
526 /* Write physical address half word
528 * void ml_phys_write_half(vm_offset_t paddr, unsigned int data)
529 * void ml_phys_write_half_64(addr64_t paddr, unsigned int data)
531 * Write the half word at physical address paddr. Memory should not be cache inhibited.
535 .globl EXT(ml_phys_write_half_64)
537 LEXT(ml_phys_write_half_64)
539 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
540 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
541 mr r4,r5 ; Copy over the data
542 b ml_phys_write_half_join
544 .globl EXT(ml_phys_write_half)
546 LEXT(ml_phys_write_half)
547 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
548 ml_phys_write_half_join: ; r3 = address to write (reg64_t), r4 = data
549 mflr r11 ; Save the return
550 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
552 sth r4,0(r3) ; Set the half word
553 b rdwrpost ; Clean up and leave...
556 /* Write physical address word
558 * void ml_phys_write(vm_offset_t paddr, unsigned int data)
559 * void ml_phys_write_64(addr64_t paddr, unsigned int data)
560 * void ml_phys_write_word(vm_offset_t paddr, unsigned int data)
561 * void ml_phys_write_word_64(addr64_t paddr, unsigned int data)
563 * Write the word at physical address paddr. Memory should not be cache inhibited.
567 .globl EXT(ml_phys_write_64)
568 .globl EXT(ml_phys_write_word_64)
570 LEXT(ml_phys_write_64)
571 LEXT(ml_phys_write_word_64)
573 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
574 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
575 mr r4,r5 ; Copy over the data
576 b ml_phys_write_word_join
578 .globl EXT(ml_phys_write)
579 .globl EXT(ml_phys_write_word)
582 LEXT(ml_phys_write_word)
583 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
584 ml_phys_write_word_join: ; r3 = address to write (reg64_t), r4 = data
585 mflr r11 ; Save the return
586 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
588 stw r4,0(r3) ; Set the word
589 b rdwrpost ; Clean up and leave...
592 /* Write physical address double word
594 * void ml_phys_write_double(vm_offset_t paddr, unsigned long long data)
595 * void ml_phys_write_double_64(addr64_t paddr, unsigned long long data)
597 * Write the double word at physical address paddr. Memory should not be cache inhibited.
601 .globl EXT(ml_phys_write_double_64)
603 LEXT(ml_phys_write_double_64)
605 rlwinm r3,r3,0,1,0 ; Copy low 32 bits to top 32
606 rlwimi r3,r4,0,0,31 ; Insert low part of 64-bit address in bottom 32 bits
607 mr r4,r5 ; Copy over the high data
608 mr r5,r6 ; Copy over the low data
609 b ml_phys_write_double_join
611 .globl EXT(ml_phys_write_double)
613 LEXT(ml_phys_write_double)
614 rlwinm r3,r3,0,0,31 ; truncate address to 32-bits
615 ml_phys_write_double_join: ; r3 = address to write (reg64_t), r4,r5 = data (long long)
616 mflr r11 ; Save the return
617 bl rdwrpre ; Get set up, translation/interrupts off, 64-bit on, etc.
619 stw r4,0(r3) ; Set the high word
620 stw r5,4(r3) ; Set the low word
621 b rdwrpost ; Clean up and leave...
626 rdwrpre: mfsprg r12,2 ; Get feature flags
627 lis r8,hi16(MASK(MSR_VEC)) ; Get the vector flag
628 mfmsr r10 ; Save the MSR
629 ori r8,r8,lo16(MASK(MSR_FP)) ; Add the FP flag
630 mtcrf 0x02,r12 ; move pf64Bit
631 andc r10,r10,r8 ; Clear VEC and FP
632 ori r9,r8,lo16(MASK(MSR_EE)|MASK(MSR_IR)|MASK(MSR_DR)) ; Drop EE, DR, and IR
633 li r2,1 ; Prepare for 64 bit
634 andc r9,r10,r9 ; Clear VEC, FP, DR, and EE
635 bf-- pf64Bitb,rdwrpre32 ; Join 32-bit code...
637 srdi r7,r3,31 ; Get a 1 if address is in I/O memory
638 rldimi r9,r2,63,MSR_SF_BIT ; set SF bit (bit 0)
639 cmpldi cr7,r7,1 ; Is source in I/O memory?
640 mtmsrd r9 ; set 64-bit mode, turn off EE, DR, and IR
643 sldi r0,r2,32+8 ; Get the right bit to turn off caching
645 bnelr++ cr7 ; We are not in the I/O area, all ready...
647 mfspr r8,hid4 ; Get HID4
648 or r2,r8,r0 ; Set bit to make real accesses cache-inhibited
650 mtspr hid4,r2 ; Make real accesses cache-inhibited
651 isync ; Toss prefetches
653 lis r7,0xE000 ; Get the unlikeliest ESID possible
654 srdi r7,r7,1 ; Make 0x7FFFFFFFF0000000
655 slbie r7 ; Make sure the ERAT is cleared
659 blr ; Finally, all ready...
663 rdwrpre32: rlwimi r9,r10,0,MSR_IR_BIT,MSR_IR_BIT ; Leave the IR bit unchanged
664 mtmsr r9 ; Drop EE, DR, and leave IR unchanged
666 blr ; All set up, leave...
670 rdwrpost: mtlr r11 ; Restore the return
671 bt++ pf64Bitb,rdwrpost64 ; Join 64-bit code...
673 mtmsr r10 ; Restore entry MSR (sans FP and VEC)
677 rdwrpost64: bne++ cr7,rdwrpcok ; Skip enabling real mode caching if we did not change it...
680 mtspr hid4,r8 ; Make real accesses not cache-inhibited
681 isync ; Toss prefetches
683 lis r7,0xE000 ; Get the unlikeliest ESID possible
684 srdi r7,r7,1 ; Make 0x7FFFFFFFF0000000
685 slbie r7 ; Make sure the ERAT is cleared
687 rdwrpcok: mtmsrd r10 ; Restore entry MSR (sans FP and VEC)
692 /* set interrupts enabled or disabled
694 * boolean_t set_interrupts_enabled(boolean_t enable)
696 * Set EE bit to "enable" and return old value as boolean
699 ; Force a line boundry here
701 .globl EXT(ml_set_interrupts_enabled)
703 LEXT(ml_set_interrupts_enabled)
705 andi. r4,r3,1 ; Are we turning interruptions on?
706 lis r0,hi16(MASK(MSR_VEC)) ; Get vector enable
707 mfmsr r5 ; Get the current MSR
708 ori r0,r0,lo16(MASK(MSR_EE)|MASK(MSR_FP)) ; Get float enable and EE enable
709 rlwinm r3,r5,17,31,31 ; Set return value
710 andc r5,r5,r0 ; Force VEC and FP off
711 bne CheckPreemption ; Interrupts going on, check ASTs...
713 mtmsr r5 ; Slam diable (always going disabled here)
714 isync ; Need this because FP/Vec might go off
720 mfsprg r9,1 ; Get current activation
721 lwz r7,ACT_PER_PROC(r9) ; Get the per_proc block
722 ori r5,r5,lo16(MASK(MSR_EE)) ; Turn on the enable
723 lwz r8,PP_PENDING_AST(r7) ; Get pending AST mask
724 li r6,AST_URGENT ; Get the type we will preempt for
725 lwz r7,ACT_PREEMPT_CNT(r9) ; Get preemption count
726 lis r0,hi16(DoPreemptCall) ; High part of Preempt FW call
727 cmpwi cr1,r7,0 ; Are preemptions masked off?
728 and. r8,r8,r6 ; Are we urgent?
729 crorc cr1_eq,cr0_eq,cr1_eq ; Remember if preemptions are masked or not urgent
730 ori r0,r0,lo16(DoPreemptCall) ; Bottome of FW call
732 mtmsr r5 ; Restore the MSR now, before we can preempt
733 isync ; Need this because FP/Vec might go off
735 beqlr++ cr1 ; Return if no premption...
739 ; Force a line boundry here
741 .globl EXT(timer_update)
744 stw r4,TIMER_HIGHCHK(r3)
748 stw r4,TIMER_HIGH(r3)
751 ; Force a line boundry here
753 .globl EXT(timer_grab)
756 0: lwz r11,TIMER_HIGH(r3)
759 lwz r9,TIMER_HIGHCHK(r3)
765 ; Force a line boundry here
767 .globl EXT(timer_event)
770 mfsprg r10,1 ; Get the current activation
771 lwz r10,ACT_PER_PROC(r10) ; Get the per_proc block
772 addi r10,r10,PP_PROCESSOR
773 lwz r11,CURRENT_TIMER(r10)
775 lwz r9,TIMER_LOW(r11)
776 lwz r2,TIMER_TSTAMP(r11)
782 lwz r6,TIMER_HIGH(r11)
784 stw r6,TIMER_HIGHCHK(r11)
786 stw r5,TIMER_LOW(r11)
788 stw r6,TIMER_HIGH(r11)
791 0: stw r5,TIMER_LOW(r11)
793 1: stw r4,CURRENT_TIMER(r10)
794 stw r3,TIMER_TSTAMP(r4)
797 /* Set machine into idle power-saving mode.
799 * void machine_idle(void)
801 * We will use the PPC NAP or DOZE for this.
802 * This call always returns. Must be called with spllo (i.e., interruptions
807 ; Force a line boundry here
809 .globl EXT(machine_idle)
813 mfsprg r12,1 ; Get the current activation
814 lwz r12,ACT_PER_PROC(r12) ; Get the per_proc block
815 lhz r10,PP_CPU_FLAGS(r12) ; Get the flags
816 lwz r11,PP_INTS_ENABLED(r12) ; Get interrupt enabled state
817 andi. r10,r10,SignalReady ; Are Signal ready?
818 cmpwi cr1,r11,0 ; Are interrupt disabled?
819 cror cr0_eq, cr1_eq, cr0_eq ; Interrupt disabled or Signal not ready?
820 mfmsr r3 ; Save the MSR
822 beq-- nonap ; Yes, return after re-enabling interrupts
823 lis r0,hi16(MASK(MSR_VEC)) ; Get the vector flag
824 ori r0,r0,lo16(MASK(MSR_FP)) ; Add the FP flag
825 andc r3,r3,r0 ; Clear VEC and FP
826 ori r0,r0,lo16(MASK(MSR_EE)) ; Drop EE also
827 andc r5,r3,r0 ; Clear VEC, FP, DR, and EE
829 mtmsr r5 ; Hold up interruptions for now
830 isync ; May have messed with fp/vec
831 mfsprg r11,2 ; Get CPU specific features
832 mfspr r6,hid0 ; Get the current power-saving mode
833 mtcrf 0xC7,r11 ; Get the facility flags
835 lis r4,hi16(napm) ; Assume we can nap
836 bt pfWillNapb,yesnap ; Yeah, nap is ok...
838 lis r4,hi16(dozem) ; Assume we can doze
839 bt pfCanDozeb,yesnap ; We can sleep or doze one this machine...
841 nonap: ori r3,r3,lo16(MASK(MSR_EE)) ; Flip on EE
843 mtmsr r3 ; Turn interruptions back on
846 yesnap: mftbu r9 ; Get the upper timebase
847 mftb r7 ; Get the lower timebase
848 mftbu r8 ; Get the upper one again
849 cmplw r9,r8 ; Did the top tick?
850 bne-- yesnap ; Yeah, need to get it again...
851 stw r8,napStamp(r12) ; Set high order time stamp
852 stw r7,napStamp+4(r12) ; Set low order nap stamp
854 rlwinm. r0,r11,0,pfAltivecb,pfAltivecb ; Do we have altivec?
855 beq-- minovec ; No...
856 dssall ; Stop the streams before we nap/doze
858 lwz r8,napStamp(r12) ; Reload high order time stamp
864 minovec: rlwinm. r7,r11,0,pfNoL2PFNapb,pfNoL2PFNapb ; Turn off L2 Prefetch before nap?
867 mfspr r7,msscr0 ; Get currect MSSCR0 value
868 rlwinm r7,r7,0,0,l2pfes-1 ; Disable L2 Prefetch
869 mtspr msscr0,r7 ; Updates MSSCR0 value
874 rlwinm. r7,r11,0,pfSlowNapb,pfSlowNapb ; Should nap at slow speed?
877 mfspr r7,hid1 ; Get current HID1 value
878 oris r7,r7,hi16(hid1psm) ; Select PLL1
879 mtspr hid1,r7 ; Update HID1 value
883 ; We have to open up interruptions here because book 4 says that we should
884 ; turn on only the POW bit and that we should have interrupts enabled.
885 ; The interrupt handler will detect that nap or doze is set if an interrupt
886 ; is taken and set everything up to return directly to machine_idle_ret.
887 ; So, make sure everything we need there is already set up...
891 lis r10,hi16(dozem|napm|sleepm) ; Mask of power management bits
893 bf-- pf64Bitb,mipNSF1 ; skip if 32-bit...
895 sldi r4,r4,32 ; Position the flags
896 sldi r10,r10,32 ; Position the masks
898 mipNSF1: li r2,lo16(MASK(MSR_DR)|MASK(MSR_IR)) ; Get the translation mask
899 andc r6,r6,r10 ; Clean up the old power bits
900 ori r7,r5,lo16(MASK(MSR_EE)) ; Flip on EE to make exit msr
901 andc r5,r5,r2 ; Clear IR and DR from current MSR
902 or r6,r6,r4 ; Set nap or doze
903 ori r5,r5,lo16(MASK(MSR_EE)) ; Flip on EE to make nap msr
904 oris r2,r5,hi16(MASK(MSR_POW)) ; Turn on power management in next MSR
907 mtspr hid0,r6 ; Set up the HID for nap/doze
908 mfspr r6,hid0 ; Yes, this is silly, keep it here
909 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
910 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
911 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
912 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
913 mfspr r6,hid0 ; Yes, this is a duplicate, keep it here
914 isync ; Make sure it is set
918 ; Turn translation off to nap
921 bt pfNoMSRirb,miNoMSR ; Jump if we need to use SC for this...
922 mtmsr r5 ; Turn translation off, interrupts on
924 b miNoMSRx ; Jump back in line...
926 miNoMSR: mr r3,r5 ; Pass in the new MSR value
927 li r0,loadMSR ; MSR setter ultrafast
928 sc ; Do it to it like you never done before...
930 miNoMSRx: bf-- pf64Bitb,mipowloop ; skip if 32-bit...
932 li r3,0x10 ; Fancy nap threshold is 0x10 ticks
933 mftb r8 ; Get the low half of the time base
934 mfdec r4 ; Get the decrementer ticks
935 cmplw r4,r3 ; Less than threshold?
938 mtdec r3 ; Load decrementer with threshold
939 isync ; and make sure,
940 mfdec r3 ; really sure, it gets there
942 rlwinm r6,r2,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Clear out the EE bit
943 sync ; Make sure queues are clear
944 mtmsr r6 ; Set MSR with EE off but POW on
945 isync ; Make sure this takes before we proceed
947 mftb r9 ; Get the low half of the time base
948 sub r9,r9,r8 ; Get the number of ticks spent waiting
949 sub r4,r4,r9 ; Adjust the decrementer value
951 mtdec r4 ; Load decrementer with the rest of the timeout
952 isync ; and make sure,
953 mfdec r4 ; really sure, it gets there
956 sync ; Make sure queues are clear
957 mtmsr r2 ; Nap or doze, MSR with POW, EE set, translation off
958 isync ; Make sure this takes before we proceed
959 b mipowloop ; loop if POW does not take
962 ; Note that the interrupt handler will turn off the nap/doze bits in the hid.
963 ; Also remember that the interrupt handler will force return to here whenever
964 ; the nap/doze bits are set.
966 .globl EXT(machine_idle_ret)
967 LEXT(machine_idle_ret)
968 mtmsr r7 ; Make sure the MSR is what we want
969 isync ; In case we turn on translation
971 ; Protect against a lost decrementer trap if the current decrementer value is negative
972 ; by more than 10 ticks, re-arm it since it is unlikely to fire at this point...
973 ; A hardware interrupt got us out of machine_idle and may also be contributing to this state
975 mfdec r6 ; Get decrementer
976 cmpwi cr0,r6,-10 ; Compare decrementer with -10
977 bgelr++ ; Return if greater
979 mtdec r0 ; Set decrementer to 1
982 /* Put machine to sleep.
983 * This call never returns. We always exit sleep via a soft reset.
984 * All external interruptions must be drained at this point and disabled.
986 * void ml_ppc_do_sleep(void)
988 * We will use the PPC SLEEP for this.
990 * There is one bit of hackery in here: we need to enable for
991 * interruptions when we go to sleep and there may be a pending
992 * decrimenter rupt. So we make the decrimenter 0x7FFFFFFF and enable for
993 * interruptions. The decrimenter rupt vector recognizes this and returns
994 * directly back here.
998 ; Force a line boundry here
1000 .globl EXT(ml_ppc_do_sleep)
1002 LEXT(ml_ppc_do_sleep)
1005 mfmsr r5 ; Hack to spin instead of sleep
1006 rlwinm r5,r5,0,MSR_DR_BIT+1,MSR_IR_BIT-1 ; Turn off translation
1007 rlwinm r5,r5,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Turn off interruptions
1008 mtmsr r5 ; No talking
1011 deadsleep: addi r3,r3,1 ; Make analyzer happy
1014 b deadsleep ; Die the death of 1000 joys...
1017 mfsprg r12,1 ; Get the current activation
1018 lwz r12,ACT_PER_PROC(r12) ; Get the per_proc block
1019 mfsprg r11,2 ; Get CPU specific features
1020 eqv r10,r10,r10 ; Get all foxes
1021 mtcrf 0x04,r11 ; move pfNoMSRirb to cr5
1022 mfspr r4,hid0 ; Get the current power-saving mode
1023 mtcrf 0x02,r11 ; move pf64Bit to cr6
1025 rlwinm. r5,r11,0,pfNoL2PFNapb,pfNoL2PFNapb ; Turn off L2 Prefetch before sleep?
1028 mfspr r5,msscr0 ; Get currect MSSCR0 value
1029 rlwinm r5,r5,0,0,l2pfes-1 ; Disable L2 Prefetch
1030 mtspr msscr0,r5 ; Updates MSSCR0 value
1035 bt++ pf64Bitb,mpsPF64bit ; PM bits are shifted on 64bit systems.
1037 rlwinm r4,r4,0,sleep+1,doze-1 ; Clear all possible power-saving modes (not DPM though)
1038 oris r4,r4,hi16(sleepm) ; Set sleep
1042 lis r5, hi16(dozem|napm|sleepm) ; Clear all possible power-saving modes (not DPM though)
1045 lis r5, hi16(napm) ; Set sleep
1050 mfmsr r5 ; Get the current MSR
1051 rlwinm r10,r10,0,1,31 ; Make 0x7FFFFFFF
1052 mtdec r10 ; Load decrimenter with 0x7FFFFFFF
1053 isync ; and make sure,
1054 mfdec r9 ; really sure, it gets there
1056 li r2,1 ; Prepare for 64 bit
1057 rlwinm r5,r5,0,MSR_DR_BIT+1,MSR_IR_BIT-1 ; Turn off translation
1059 ; Note that we need translation off before we set the HID to sleep. Otherwise
1060 ; we will ignore any PTE misses that occur and cause an infinite loop.
1062 bf++ pf64Bitb,mpsCheckMSR ; check 64-bit processor
1063 rldimi r5,r2,63,MSR_SF_BIT ; set SF bit (bit 0)
1064 mtmsrd r5 ; set 64-bit mode, turn off EE, DR, and IR
1065 isync ; Toss prefetch
1069 bt pfNoMSRirb,mpsNoMSR ; No MSR...
1071 mtmsr r5 ; Translation off
1072 isync ; Toss prefetch
1076 li r0,loadMSR ; Get the MSR setter SC
1077 mr r3,r5 ; Get new MSR
1081 ori r3,r5,lo16(MASK(MSR_EE)) ; Flip on EE
1083 mtspr hid0,r4 ; Set up the HID to sleep
1084 mfspr r4,hid0 ; Yes, this is silly, keep it here
1085 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1086 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1087 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1088 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1089 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1091 mtmsr r3 ; Enable for interrupts to drain decrimenter
1093 add r6,r4,r5 ; Just waste time
1094 add r6,r6,r4 ; A bit more
1095 add r6,r6,r5 ; A bit more
1097 mtmsr r5 ; Interruptions back off
1098 isync ; Toss prefetch
1101 ; We are here with translation off, interrupts off, all possible
1102 ; interruptions drained off, and a decrimenter that will not pop.
1105 bl EXT(cacheInit) ; Clear out the caches. This will leave them on
1106 bl EXT(cacheDisable) ; Turn off all caches
1108 mfmsr r5 ; Get the current MSR
1109 oris r5,r5,hi16(MASK(MSR_POW)) ; Turn on power management in next MSR
1110 ; Leave EE off because power goes off shortly
1111 mfsprg r12,0 ; Get the per_proc_info
1113 lhz r11,PP_CPU_FLAGS(r12) ; Get the flags
1114 ori r11,r11,SleepState ; Marked SleepState
1115 sth r11,PP_CPU_FLAGS(r12) ; Set the flags
1118 mfsprg r11,2 ; Get CPU specific features
1119 rlwinm. r0,r11,0,pf64Bitb,pf64Bitb ; Test for 64 bit processor
1120 eqv r4,r4,r4 ; Get all foxes
1121 rlwinm r4,r4,0,1,31 ; Make 0x7FFFFFFF
1122 beq slSleepNow ; skip if 32-bit...
1123 li r3, 0x4000 ; Cause decrimenter to roll over soon
1124 mtdec r3 ; Load decrimenter with 0x00004000
1125 isync ; and make sure,
1126 mfdec r3 ; really sure, it gets there
1129 sync ; Sync it all up
1130 mtmsr r5 ; Do sleep with interruptions enabled
1132 mtdec r4 ; Load decrimenter with 0x7FFFFFFF
1133 isync ; and make sure,
1134 mfdec r3 ; really sure, it gets there
1135 b slSleepNow ; Go back to sleep if we wake up...
1139 /* Initialize all caches including the TLBs
1141 * void cacheInit(void)
1143 * This is used to force the caches to an initial clean state. First, we
1144 * check if the cache is on, if so, we need to flush the contents to memory.
1145 * Then we invalidate the L1. Next, we configure and invalidate the L2 etc.
1146 * Finally we turn on all of the caches
1148 * Note that if translation is not disabled when this is called, the TLB will not
1149 * be completely clear after return.
1153 ; Force a line boundry here
1155 .globl EXT(cacheInit)
1159 mfsprg r12,0 ; Get the per_proc_info
1160 mfspr r9,hid0 ; Get the current power-saving mode
1162 mfsprg r11,2 ; Get CPU specific features
1163 mfmsr r7 ; Get the current MSR
1164 rlwinm r7,r7,0,MSR_FP_BIT+1,MSR_FP_BIT-1 ; Force floating point off
1165 rlwinm r7,r7,0,MSR_VEC_BIT+1,MSR_VEC_BIT-1 ; Force vectors off
1166 rlwimi r11,r11,pfLClckb+1,31,31 ; Move pfLClck to another position (to keep from using non-volatile CRs)
1167 rlwinm r5,r7,0,MSR_DR_BIT+1,MSR_IR_BIT-1 ; Turn off translation
1168 rlwinm r5,r5,0,MSR_EE_BIT+1,MSR_EE_BIT-1 ; Turn off interruptions
1169 mtcrf 0x87,r11 ; Get the feature flags
1170 lis r10,hi16(dozem|napm|sleepm|dpmm) ; Mask of power management bits
1171 bf-- pf64Bitb,cIniNSF1 ; Skip if 32-bit...
1173 sldi r10,r10,32 ; Position the masks
1175 cIniNSF1: andc r4,r9,r10 ; Clean up the old power bits
1176 mtspr hid0,r4 ; Set up the HID
1177 mfspr r4,hid0 ; Yes, this is silly, keep it here
1178 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1179 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1180 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1181 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1182 mfspr r4,hid0 ; Yes, this is a duplicate, keep it here
1184 bt pfNoMSRirb,ciNoMSR ; No MSR...
1186 mtmsr r5 ; Translation and all off
1187 isync ; Toss prefetch
1191 li r0,loadMSR ; Get the MSR setter SC
1192 mr r3,r5 ; Get new MSR
1196 bf pfAltivecb,cinoDSS ; No Altivec here...
1198 dssall ; Stop streams
1201 cinoDSS: li r5,tlbieLock ; Get the TLBIE lock
1202 li r0,128 ; Get number of TLB entries
1204 li r6,0 ; Start at 0
1205 bf-- pf64Bitb,citlbhang ; Skip if 32-bit...
1206 li r0,1024 ; Get the number of TLB entries
1208 citlbhang: lwarx r2,0,r5 ; Get the TLBIE lock
1209 mr. r2,r2 ; Is it locked?
1210 bne- citlbhang ; It is locked, go wait...
1211 stwcx. r0,0,r5 ; Try to get it
1212 bne- citlbhang ; We was beat...
1214 mtctr r0 ; Set the CTR
1216 cipurgeTLB: tlbie r6 ; Purge this entry
1217 addi r6,r6,4096 ; Next page
1218 bdnz cipurgeTLB ; Do them all...
1220 mtcrf 0x80,r11 ; Set SMP capability
1221 sync ; Make sure all TLB purges are done
1222 eieio ; Order, order in the court
1224 bf pfSMPcapb,cinoSMP ; SMP incapable...
1226 tlbsync ; Sync all TLBs
1230 bf-- pf64Bitb,cinoSMP ; Skip if 32-bit...
1231 ptesync ; Wait for quiet again
1234 cinoSMP: stw r2,tlbieLock(0) ; Unlock TLBIE lock
1236 bt++ pf64Bitb,cin64 ; Skip if 64-bit...
1238 rlwinm. r0,r9,0,ice,dce ; Were either of the level 1s on?
1239 beq- cinoL1 ; No, no need to flush...
1241 rlwinm. r0,r11,0,pfL1fab,pfL1fab ; do we have L1 flush assist?
1242 beq ciswdl1 ; If no hw flush assist, go do by software...
1244 mfspr r8,msscr0 ; Get the memory system control register
1245 oris r8,r8,hi16(dl1hwfm) ; Turn on the hardware flush request
1247 mtspr msscr0,r8 ; Start the flush operation
1249 ciwdl1f: mfspr r8,msscr0 ; Get the control register again
1251 rlwinm. r8,r8,0,dl1hwf,dl1hwf ; Has the flush request been reset yet?
1252 bne ciwdl1f ; No, flush is still in progress...
1253 b ciinvdl1 ; Go invalidate l1...
1256 ; We need to either make this very complicated or to use ROM for
1257 ; the flush. The problem is that if during the following sequence a
1258 ; snoop occurs that invalidates one of the lines in the cache, the
1259 ; PLRU sequence will be altered making it possible to miss lines
1260 ; during the flush. So, we either need to dedicate an area of RAM
1261 ; to each processor, lock use of a RAM area, or use ROM. ROM is
1262 ; by far the easiest. Note that this is not an issue for machines
1263 ; that have harware flush assists.
1266 ciswdl1: lwz r0,pfl1dSize(r12) ; Get the level 1 cache size
1268 bf 31,cisnlck ; Skip if pfLClck not set...
1271 rlwinm r6,r4,0,0,l2pfes-1 ; ?
1272 mtspr msscr0,r6 ; Set it
1276 mfspr r8,ldstcr ; Save the LDSTCR
1277 li r2,1 ; Get a mask of 0x01
1278 lis r3,0xFFF0 ; Point to ROM
1279 rlwinm r11,r0,29,3,31 ; Get the amount of memory to handle all indexes
1281 li r6,0 ; Start here
1283 cisiniflsh: dcbf r6,r3 ; Flush each line of the range we use
1284 addi r6,r6,32 ; Bump to the next
1285 cmplw r6,r0 ; Have we reached the end?
1286 blt+ cisiniflsh ; Nope, continue initial flush...
1288 sync ; Make sure it is done
1290 addi r11,r11,-1 ; Get mask for index wrap
1291 li r6,0 ; Get starting offset
1293 cislckit: not r5,r2 ; Lock all but 1 way
1294 rlwimi r5,r8,0,0,23 ; Build LDSTCR
1295 mtspr ldstcr,r5 ; Lock a way
1296 sync ; Clear out memory accesses
1297 isync ; Wait for all
1300 cistouch: lwzx r10,r3,r6 ; Pick up some trash
1301 addi r6,r6,32 ; Go to the next index
1302 and. r0,r6,r11 ; See if we are about to do next index
1303 bne+ cistouch ; Nope, do more...
1305 sync ; Make sure it is all done
1308 sub r6,r6,r11 ; Back up to start + 1
1309 addi r6,r6,-1 ; Get it right
1311 cisflush: dcbf r3,r6 ; Flush everything out
1312 addi r6,r6,32 ; Go to the next index
1313 and. r0,r6,r11 ; See if we are about to do next index
1314 bne+ cisflush ; Nope, do more...
1316 sync ; Make sure it is all done
1320 rlwinm. r2,r2,1,24,31 ; Shift to next way
1321 bne+ cislckit ; Do this for all ways...
1323 mtspr ldstcr,r8 ; Slam back to original
1331 b cinoL1 ; Go on to level 2...
1334 cisnlck: rlwinm r2,r0,0,1,30 ; Double cache size
1335 add r0,r0,r2 ; Get 3 times cache size
1336 rlwinm r0,r0,26,6,31 ; Get 3/2 number of cache lines
1337 lis r3,0xFFF0 ; Dead recon ROM address for now
1338 mtctr r0 ; Number of lines to flush
1340 ciswfldl1a: lwz r2,0(r3) ; Flush anything else
1341 addi r3,r3,32 ; Next line
1342 bdnz ciswfldl1a ; Flush the lot...
1344 ciinvdl1: sync ; Make sure all flushes have been committed
1346 mfspr r8,hid0 ; Get the HID0 bits
1347 rlwinm r8,r8,0,dce+1,ice-1 ; Clear cache enables
1348 mtspr hid0,r8 ; and turn off L1 cache
1349 sync ; Make sure all is done
1352 ori r8,r8,lo16(icem|dcem|icfim|dcfim) ; Set the HID0 bits for enable, and invalidate
1356 mtspr hid0,r8 ; Start the invalidate and turn on cache
1357 rlwinm r8,r8,0,dcfi+1,icfi-1 ; Turn off the invalidate bits
1358 mtspr hid0,r8 ; Turn off the invalidate (needed for some older machines)
1364 ; Flush and disable the level 2
1366 mfsprg r10,2 ; need to check 2 features we did not put in CR
1367 rlwinm. r0,r10,0,pfL2b,pfL2b ; do we have L2?
1368 beq cinol2 ; No level 2 cache to flush
1370 mfspr r8,l2cr ; Get the L2CR
1371 lwz r3,pfl2cr(r12) ; Get the L2CR value
1372 rlwinm. r0,r8,0,l2e,l2e ; Was the L2 enabled?
1373 bne ciflushl2 ; Yes, force flush
1374 cmplwi r8, 0 ; Was the L2 all the way off?
1375 beq ciinvdl2 ; Yes, force invalidate
1376 lis r0,hi16(l2sizm|l2clkm|l2ramm|l2ohm) ; Get confiuration bits
1377 xor r2,r8,r3 ; Get changing bits?
1378 ori r0,r0,lo16(l2slm|l2dfm|l2bypm) ; More config bits
1379 and. r0,r0,r2 ; Did any change?
1380 bne- ciinvdl2 ; Yes, just invalidate and get PLL synced...
1383 rlwinm. r0,r10,0,pfL2fab,pfL2fab ; hardware-assisted L2 flush?
1384 beq ciswfl2 ; Flush not in hardware...
1386 mr r10,r8 ; Take a copy now
1388 bf 31,cinol2lck ; Skip if pfLClck not set...
1390 oris r10,r10,hi16(l2ionlym|l2donlym) ; Set both instruction- and data-only
1392 mtspr l2cr,r10 ; Lock out the cache
1396 cinol2lck: ori r10,r10,lo16(l2hwfm) ; Request flush
1397 sync ; Make sure everything is done
1399 mtspr l2cr,r10 ; Request flush
1401 cihwfl2: mfspr r10,l2cr ; Get back the L2CR
1402 rlwinm. r10,r10,0,l2hwf,l2hwf ; Is the flush over?
1403 bne+ cihwfl2 ; Nope, keep going...
1404 b ciinvdl2 ; Flush done, go invalidate L2...
1407 lwz r0,pfl2Size(r12) ; Get the L2 size
1408 oris r2,r8,hi16(l2dom) ; Set L2 to data only mode
1410 b ciswfl2doa ; Branch to next line...
1414 mtspr l2cr,r2 ; Disable L2
1417 b ciswfl2dod ; It is off, go invalidate it...
1420 b ciswfl2dob ; Branch to next...
1423 sync ; Finish memory stuff
1424 isync ; Stop speculation
1425 b ciswfl2doc ; Jump back up and turn on data only...
1427 rlwinm r0,r0,27,5,31 ; Get the number of lines
1428 lis r10,0xFFF0 ; Dead recon ROM for now
1429 mtctr r0 ; Set the number of lines
1431 ciswfldl2a: lwz r0,0(r10) ; Load something to flush something
1432 addi r10,r10,32 ; Next line
1433 bdnz ciswfldl2a ; Do the lot...
1435 ciinvdl2: rlwinm r8,r3,0,l2e+1,31 ; Clear the enable bit
1436 b cinla ; Branch to next line...
1439 cinlc: mtspr l2cr,r8 ; Disable L2
1442 b ciinvl2 ; It is off, go invalidate it...
1444 cinla: b cinlb ; Branch to next...
1446 cinlb: sync ; Finish memory stuff
1447 isync ; Stop speculation
1448 b cinlc ; Jump back up and turn off cache...
1453 cmplwi r3, 0 ; Should the L2 be all the way off?
1454 beq cinol2 ; Yes, done with L2
1456 oris r2,r8,hi16(l2im) ; Get the invalidate flag set
1458 mtspr l2cr,r2 ; Start the invalidate
1461 ciinvdl2a: mfspr r2,l2cr ; Get the L2CR
1462 mfsprg r0,2 ; need to check a feature in "non-volatile" set
1463 rlwinm. r0,r0,0,pfL2ib,pfL2ib ; flush in HW?
1464 beq ciinvdl2b ; Flush not in hardware...
1465 rlwinm. r2,r2,0,l2i,l2i ; Is the invalidate still going?
1466 bne+ ciinvdl2a ; Assume so, this will take a looong time...
1468 b cinol2 ; No level 2 cache to flush
1470 rlwinm. r2,r2,0,l2ip,l2ip ; Is the invalidate still going?
1471 bne+ ciinvdl2a ; Assume so, this will take a looong time...
1473 mtspr l2cr,r8 ; Turn off the invalidate request
1478 ; Flush and enable the level 3
1480 bf pfL3b,cinol3 ; No level 3 cache to flush
1482 mfspr r8,l3cr ; Get the L3CR
1483 lwz r3,pfl3cr(r12) ; Get the L3CR value
1484 rlwinm. r0,r8,0,l3e,l3e ; Was the L3 enabled?
1485 bne ciflushl3 ; Yes, force flush
1486 cmplwi r8, 0 ; Was the L3 all the way off?
1487 beq ciinvdl3 ; Yes, force invalidate
1488 lis r0,hi16(l3pem|l3sizm|l3dxm|l3clkm|l3spom|l3ckspm) ; Get configuration bits
1489 xor r2,r8,r3 ; Get changing bits?
1490 ori r0,r0,lo16(l3pspm|l3repm|l3rtm|l3cyam|l3dmemm|l3dmsizm) ; More config bits
1491 and. r0,r0,r2 ; Did any change?
1492 bne- ciinvdl3 ; Yes, just invalidate and get PLL synced...
1495 sync ; 7450 book says do this even though not needed
1496 mr r10,r8 ; Take a copy now
1498 bf 31,cinol3lck ; Skip if pfL23lck not set...
1500 oris r10,r10,hi16(l3iom) ; Set instruction-only
1501 ori r10,r10,lo16(l3donlym) ; Set data-only
1503 mtspr l3cr,r10 ; Lock out the cache
1507 cinol3lck: ori r10,r10,lo16(l3hwfm) ; Request flush
1508 sync ; Make sure everything is done
1510 mtspr l3cr,r10 ; Request flush
1512 cihwfl3: mfspr r10,l3cr ; Get back the L3CR
1513 rlwinm. r10,r10,0,l3hwf,l3hwf ; Is the flush over?
1514 bne+ cihwfl3 ; Nope, keep going...
1516 ciinvdl3: rlwinm r8,r3,0,l3e+1,31 ; Clear the enable bit
1517 sync ; Make sure of life, liberty, and justice
1518 mtspr l3cr,r8 ; Disable L3
1521 cmplwi r3, 0 ; Should the L3 be all the way off?
1522 beq cinol3 ; Yes, done with L3
1524 ori r8,r8,lo16(l3im) ; Get the invalidate flag set
1526 mtspr l3cr,r8 ; Start the invalidate
1528 ciinvdl3b: mfspr r8,l3cr ; Get the L3CR
1529 rlwinm. r8,r8,0,l3i,l3i ; Is the invalidate still going?
1530 bne+ ciinvdl3b ; Assume so...
1533 lwz r10, pfBootConfig(r12) ; ?
1534 rlwinm. r10, r10, 24, 28, 31 ; ?
1535 beq ciinvdl3nopdet ; ?
1539 rlwimi r2, r8, 0, 24, 31 ; ?
1540 subfic r10, r10, 32 ; ?
1542 ori r2, r2, 0x0080 ; ?
1545 mtspr l3pdet, r8 ; ?
1549 mfspr r8,l3cr ; Get the L3CR
1550 rlwinm r8,r8,0,l3clken+1,l3clken-1 ; Clear the clock enable bit
1551 mtspr l3cr,r8 ; Disable the clock
1554 ciinvdl3c: addi r2,r2,-1 ; ?
1558 mfspr r10,msssr0 ; ?
1559 rlwinm r10,r10,0,vgL3TAG+1,vgL3TAG-1 ; ?
1560 mtspr msssr0,r10 ; ?
1563 mtspr l3cr,r3 ; Enable it as desired
1566 mfsprg r0,2 ; need to check a feature in "non-volatile" set
1567 rlwinm. r0,r0,0,pfL2b,pfL2b ; is there an L2 cache?
1568 beq cinol2a ; No level 2 cache to enable
1570 lwz r3,pfl2cr(r12) ; Get the L2CR value
1571 cmplwi r3, 0 ; Should the L2 be all the way off?
1572 beq cinol2a : Yes, done with L2
1573 mtspr l2cr,r3 ; Enable it as desired
1577 ; Invalidate and turn on L1s
1581 bt 31,cinoexit ; Skip if pfLClck set...
1583 rlwinm r8,r9,0,dce+1,ice-1 ; Clear the I- and D- cache enables
1584 mtspr hid0,r8 ; Turn off dem caches
1587 ori r8,r9,lo16(icem|dcem|icfim|dcfim) ; Set the HID0 bits for enable, and invalidate
1588 rlwinm r9,r8,0,dcfi+1,icfi-1 ; Turn off the invalidate bits
1592 mtspr hid0,r8 ; Start the invalidate and turn on L1 cache
1594 cinoexit: mtspr hid0,r9 ; Turn off the invalidate (needed for some older machines) and restore entry conditions
1596 mtmsr r7 ; Restore MSR to entry
1602 ; Handle 64-bit architecture
1603 ; This processor can not run without caches, so we just push everything out
1604 ; and flush. It will be relativily clean afterwards
1610 mfspr r10,hid1 ; Save hid1
1611 mfspr r4,hid4 ; Save hid4
1612 mr r12,r10 ; Really save hid1
1613 mr r11,r4 ; Get a working copy of hid4
1616 eqv r2,r2,r2 ; Get all foxes
1618 rldimi r10,r0,55,7 ; Clear I$ prefetch bits (7:8)
1621 mtspr hid1,r10 ; Stick it
1622 mtspr hid1,r10 ; Stick it again
1625 rldimi r11,r2,38,25 ; Disable D$ prefetch (25:25)
1628 mtspr hid4,r11 ; Stick it
1631 li r3,8 ; Set bit 28+32
1632 sldi r3,r3,32 ; Make it bit 28
1633 or r3,r3,r11 ; Turn on the flash invalidate L1D$
1635 oris r5,r11,0x0600 ; Set disable L1D$ bits
1637 mtspr hid4,r3 ; Invalidate
1640 mtspr hid4,r5 ; Un-invalidate and disable L1D$
1643 lis r8,GUSModeReg ; Get the GUS mode ring address
1644 mfsprg r0,2 ; Get the feature flags
1645 ori r8,r8,0x8000 ; Set to read data
1646 rlwinm. r0,r0,pfSCOMFixUpb+1,31,31 ; Set shift if we need a fix me up
1650 mtspr scomc,r8 ; Request the GUS mode
1651 mfspr r11,scomd ; Get the GUS mode
1652 mfspr r8,scomc ; Get back the status (we just ignore it)
1656 sld r11,r11,r0 ; Fix up if needed
1658 ori r6,r11,lo16(GUSMdmapen) ; Set the bit that means direct L2 cache address
1659 lis r8,GUSModeReg ; Get GUS mode register address
1663 mtspr scomd,r6 ; Set that we want direct L2 mode
1664 mtspr scomc,r8 ; Tell GUS we want direct L2 mode
1665 mfspr r3,scomc ; Get back the status
1669 li r3,0 ; Clear start point
1671 cflushlp: lis r6,0x0040 ; Pick 4MB line as our target
1672 or r6,r6,r3 ; Put in the line offset
1673 lwz r5,0(r6) ; Load a line
1674 addis r6,r6,8 ; Roll bit 42:44
1675 lwz r5,0(r6) ; Load a line
1676 addis r6,r6,8 ; Roll bit 42:44
1677 lwz r5,0(r6) ; Load a line
1678 addis r6,r6,8 ; Roll bit 42:44
1679 lwz r5,0(r6) ; Load a line
1680 addis r6,r6,8 ; Roll bit 42:44
1681 lwz r5,0(r6) ; Load a line
1682 addis r6,r6,8 ; Roll bit 42:44
1683 lwz r5,0(r6) ; Load a line
1684 addis r6,r6,8 ; Roll bit 42:44
1685 lwz r5,0(r6) ; Load a line
1686 addis r6,r6,8 ; Roll bit 42:44
1687 lwz r5,0(r6) ; Load a line
1689 addi r3,r3,128 ; Next line
1690 andis. r5,r3,8 ; Have we done enough?
1691 beq++ cflushlp ; Not yet...
1695 lis r6,0x0040 ; Pick 4MB line as our target
1697 cflushx: dcbf 0,r6 ; Flush line and invalidate
1698 addi r6,r6,128 ; Next line
1699 andis. r5,r6,0x0080 ; Have we done enough?
1700 beq++ cflushx ; Keep on flushing...
1702 mr r3,r10 ; Copy current hid1
1703 rldimi r3,r2,54,9 ; Set force icbi match mode
1705 li r6,0 ; Set start if ICBI range
1707 mtspr hid1,r3 ; Stick it
1708 mtspr hid1,r3 ; Stick it again
1711 cflicbi: icbi 0,r6 ; Kill I$
1712 addi r6,r6,128 ; Next line
1713 andis. r5,r6,1 ; Have we done them all?
1714 beq++ cflicbi ; Not yet...
1716 lis r8,GUSModeReg ; Get GUS mode register address
1720 mtspr scomd,r11 ; Set that we do not want direct mode
1721 mtspr scomc,r8 ; Tell GUS we do not want direct mode
1722 mfspr r3,scomc ; Get back the status
1727 mtspr hid0,r9 ; Restore entry hid0
1728 mfspr r9,hid0 ; Yes, this is silly, keep it here
1729 mfspr r9,hid0 ; Yes, this is a duplicate, keep it here
1730 mfspr r9,hid0 ; Yes, this is a duplicate, keep it here
1731 mfspr r9,hid0 ; Yes, this is a duplicate, keep it here
1732 mfspr r9,hid0 ; Yes, this is a duplicate, keep it here
1733 mfspr r9,hid0 ; Yes, this is a duplicate, keep it here
1737 mtspr hid1,r12 ; Restore entry hid1
1738 mtspr hid1,r12 ; Stick it again
1742 mtspr hid4,r4 ; Restore entry hid4
1746 mtmsr r7 ; Restore MSR to entry
1752 /* Disables all caches
1754 * void cacheDisable(void)
1756 * Turns off all caches on the processor. They are not flushed.
1760 ; Force a line boundry here
1762 .globl EXT(cacheDisable)
1766 mfsprg r11,2 ; Get CPU specific features
1767 mtcrf 0x83,r11 ; Set feature flags
1769 bf pfAltivecb,cdNoAlt ; No vectors...
1771 dssall ; Stop streams
1775 btlr pf64Bitb ; No way to disable a 64-bit machine...
1777 mfspr r5,hid0 ; Get the hid
1778 rlwinm r5,r5,0,dce+1,ice-1 ; Clear the I- and D- cache enables
1779 mtspr hid0,r5 ; Turn off dem caches
1782 rlwinm. r0,r11,0,pfL2b,pfL2b ; is there an L2?
1783 beq cdNoL2 ; Skip if no L2...
1785 mfspr r5,l2cr ; Get the L2
1786 rlwinm r5,r5,0,l2e+1,31 ; Turn off enable bit
1788 b cinlaa ; Branch to next line...
1791 cinlcc: mtspr l2cr,r5 ; Disable L2
1794 b cdNoL2 ; It is off, we are done...
1796 cinlaa: b cinlbb ; Branch to next...
1798 cinlbb: sync ; Finish memory stuff
1799 isync ; Stop speculation
1800 b cinlcc ; Jump back up and turn off cache...
1804 bf pfL3b,cdNoL3 ; Skip down if no L3...
1806 mfspr r5,l3cr ; Get the L3
1807 rlwinm r5,r5,0,l3e+1,31 ; Turn off enable bit
1808 rlwinm r5,r5,0,l3clken+1,l3clken-1 ; Turn off cache enable bit
1809 mtspr l3cr,r5 ; Disable the caches
1816 /* Initialize processor thermal monitoring
1817 * void ml_thrm_init(void)
1819 * Obsolete, deprecated and will be removed.
1822 ; Force a line boundry here
1824 .globl EXT(ml_thrm_init)
1829 /* Set thermal monitor bounds
1830 * void ml_thrm_set(unsigned int low, unsigned int high)
1832 * Obsolete, deprecated and will be removed.
1835 ; Force a line boundry here
1837 .globl EXT(ml_thrm_set)
1842 /* Read processor temprature
1843 * unsigned int ml_read_temp(void)
1845 * Obsolete, deprecated and will be removed.
1848 ; Force a line boundry here
1850 .globl EXT(ml_read_temp)
1856 /* Throttle processor speed up or down
1857 * unsigned int ml_throttle(unsigned int step)
1859 * Returns old speed and sets new. Both step and return are values from 0 to
1860 * 255 that define number of throttle steps, 0 being off and "ictcfim" is max * 2.
1862 * Obsolete, deprecated and will be removed.
1865 ; Force a line boundry here
1867 .globl EXT(ml_throttle)
1874 ** ml_get_timebase()
1876 ** Entry - R3 contains pointer to 64 bit structure.
1878 ** Exit - 64 bit structure filled in.
1881 ; Force a line boundry here
1883 .globl EXT(ml_get_timebase)
1885 LEXT(ml_get_timebase)
1900 * unsigned int cpu_number(void)
1902 * Returns the current cpu number.
1906 .globl EXT(cpu_number)
1909 mfsprg r4,1 ; Get the current activation
1910 lwz r4,ACT_PER_PROC(r4) ; Get the per_proc block
1911 lhz r3,PP_CPU_NUMBER(r4) ; Get CPU number
1915 * processor_t current_processor(void)
1917 * Returns the current processor.
1921 .globl EXT(current_processor)
1923 LEXT(current_processor)
1924 mfsprg r3,1 ; Get the current activation
1925 lwz r3,ACT_PER_PROC(r3) ; Get the per_proc block
1926 addi r3,r3,PP_PROCESSOR
1929 #if PROCESSOR_SIZE > PP_PROCESSOR_SIZE
1930 #error processor overflows per_proc
1934 * ast_t *ast_pending(void)
1936 * Returns the address of the pending AST mask for the current processor.
1940 .globl EXT(ast_pending)
1943 mfsprg r3,1 ; Get the current activation
1944 lwz r3,ACT_PER_PROC(r3) ; Get the per_proc block
1945 addi r3,r3,PP_PENDING_AST
1949 * void machine_set_current_thread(thread_t)
1951 * Set the current thread
1954 .globl EXT(machine_set_current_thread)
1956 LEXT(machine_set_current_thread)
1958 mfsprg r4,1 ; Get spr1
1959 lwz r5,ACT_PER_PROC(r4) ; Get the PerProc from the previous active thread
1960 stw r5,ACT_PER_PROC(r3) ; Set the PerProc in the active thread
1961 mtsprg 1,r3 ; Set spr1 with the active thread
1965 * thread_t current_thread(void)
1966 * thread_t current_act(void)
1969 * Return the current thread for outside components.
1972 .globl EXT(current_thread)
1973 .globl EXT(current_act)
1975 LEXT(current_thread)
1982 .globl EXT(clock_get_uptime)
1983 LEXT(clock_get_uptime)
1995 .globl EXT(mach_absolute_time)
1996 LEXT(mach_absolute_time)
2008 ; Force a line boundry here
2010 .globl EXT(ml_sense_nmi)
2017 ** ml_set_processor_speed_powertune()
2020 ; Force a line boundry here
2022 .globl EXT(ml_set_processor_speed_powertune)
2024 LEXT(ml_set_processor_speed_powertune)
2025 mflr r0 ; Save the link register
2026 stwu r1, -(FM_ALIGN(4*4)+FM_SIZE)(r1) ; Make some space on the stack
2027 stw r28, FM_ARG0+0x00(r1) ; Save a register
2028 stw r29, FM_ARG0+0x04(r1) ; Save a register
2029 stw r30, FM_ARG0+0x08(r1) ; Save a register
2030 stw r31, FM_ARG0+0x0C(r1) ; Save a register
2031 stw r0, (FM_ALIGN(4*4)+FM_SIZE+FM_LR_SAVE)(r1) ; Save the return
2033 mfsprg r31,1 ; Get the current activation
2034 lwz r31,ACT_PER_PROC(r31) ; Get the per_proc block
2036 rlwinm r28, r3, 31-dnap, dnap, dnap ; Shift the 1 bit to the dnap+32 bit
2037 rlwinm r3, r3, 2, 29, 29 ; Shift the 1 to a 4 and mask
2038 addi r3, r3, pfPowerTune0 ; Add in the pfPowerTune0 offset
2039 lwzx r29, r31, r3 ; Load the PowerTune number 0 or 1
2041 sldi r28, r28, 32 ; Shift to the top half
2042 ld r3, pfHID0(r31) ; Load the saved hid0 value
2043 and r28, r28, r3 ; Save the dnap bit
2044 lis r4, hi16(dnapm) ; Make a mask for the dnap bit
2045 sldi r4, r4, 32 ; Shift to the top half
2046 andc r3, r3, r4 ; Clear the dnap bit
2047 or r28, r28, r3 ; Insert the dnap bit as needed for later
2050 mtspr hid0, r3 ; Turn off dnap in hid0
2051 mfspr r3, hid0 ; Yes, this is silly, keep it here
2052 mfspr r3, hid0 ; Yes, this is a duplicate, keep it here
2053 mfspr r3, hid0 ; Yes, this is a duplicate, keep it here
2054 mfspr r3, hid0 ; Yes, this is a duplicate, keep it here
2055 mfspr r3, hid0 ; Yes, this is a duplicate, keep it here
2056 mfspr r3, hid0 ; Yes, this is a duplicate, keep it here
2057 isync ; Make sure it is set
2059 lis r3, hi16(PowerTuneControlReg) ; Write zero to the PCR
2060 ori r3, r3, lo16(PowerTuneControlReg)
2065 lis r3, hi16(PowerTuneControlReg) ; Write the PowerTune value to the PCR
2066 ori r3, r3, lo16(PowerTuneControlReg)
2071 rlwinm r29, r29, 13-6, 6, 7 ; Move to PSR speed location and isolate the requested speed
2073 lis r3, hi16(PowerTuneStatusReg) ; Read the status from the PSR
2074 ori r3, r3, lo16(PowerTuneStatusReg)
2078 rlwinm r0, r5, 0, 6, 7 ; Isolate the current speed
2079 rlwimi r0, r5, 0, 2, 2 ; Copy in the change in progress bit
2080 cmpw r0, r29 ; Compare the requested and current speeds
2081 beq spsPowerTuneDone
2082 rlwinm. r0, r5, 0, 3, 3
2083 beq spsPowerTuneLoop
2087 mtspr hid0, r28 ; Turn on dnap in hid0 if needed
2088 mfspr r28, hid0 ; Yes, this is silly, keep it here
2089 mfspr r28, hid0 ; Yes, this is a duplicate, keep it here
2090 mfspr r28, hid0 ; Yes, this is a duplicate, keep it here
2091 mfspr r28, hid0 ; Yes, this is a duplicate, keep it here
2092 mfspr r28, hid0 ; Yes, this is a duplicate, keep it here
2093 mfspr r28, hid0 ; Yes, this is a duplicate, keep it here
2094 isync ; Make sure it is set
2096 lwz r0, (FM_ALIGN(4*4)+FM_SIZE+FM_LR_SAVE)(r1) ; Get the return
2097 lwz r28, FM_ARG0+0x00(r1) ; Restore a register
2098 lwz r29, FM_ARG0+0x04(r1) ; Restore a register
2099 lwz r30, FM_ARG0+0x08(r1) ; Restore a register
2100 lwz r31, FM_ARG0+0x0C(r1) ; Restore a register
2101 lwz r1, FM_BACKPTR(r1) ; Pop the stack
2106 ** ml_set_processor_speed_dpll()
2109 ; Force a line boundry here
2111 .globl EXT(ml_set_processor_speed_dpll)
2113 LEXT(ml_set_processor_speed_dpll)
2114 mfsprg r5,1 ; Get the current activation
2115 lwz r5,ACT_PER_PROC(r5) ; Get the per_proc block
2117 cmplwi r3, 0 ; Turn off BTIC before low speed
2119 mfspr r4, hid0 ; Get the current hid0 value
2120 rlwinm r4, r4, 0, btic+1, btic-1 ; Clear the BTIC bit
2122 mtspr hid0, r4 ; Set the new hid0 value
2127 mfspr r4, hid1 ; Get the current PLL settings
2128 rlwimi r4, r3, 31-hid1ps, hid1ps, hid1ps ; Copy the PLL Select bit
2129 stw r4, pfHID1(r5) ; Save the new hid1 value
2130 mtspr hid1, r4 ; Select desired PLL
2132 cmplwi r3, 0 ; Restore BTIC after high speed
2134 lwz r4, pfHID0(r5) ; Load the hid0 value
2136 mtspr hid0, r4 ; Set the hid0 value
2144 ** ml_set_processor_speed_dfs(divideby)
2145 ** divideby == 0 then divide by 1 (full speed)
2146 ** divideby == 1 then divide by 2 (half speed)
2147 ** divideby == 2 then divide by 4 (quarter speed)
2148 ** divideby == 3 then divide by 4 (quarter speed) - preferred
2151 ; Force a line boundry here
2153 .globl EXT(ml_set_processor_speed_dfs)
2155 LEXT(ml_set_processor_speed_dfs)
2157 mfspr r4,hid1 ; Get the current HID1
2158 mfsprg r5,0 ; Get the per_proc_info
2159 rlwimi r4,r3,31-hid1dfs1,hid1dfs0,hid1dfs1 ; Stick the new divider bits in
2160 stw r4,pfHID1(r5) ; Save the new hid1 value
2162 mtspr hid1,r4 ; Set the new HID1
2169 ** ml_set_processor_voltage()
2172 ; Force a line boundry here
2174 .globl EXT(ml_set_processor_voltage)
2176 LEXT(ml_set_processor_voltage)
2177 mfsprg r5,1 ; Get the current activation
2178 lwz r5,ACT_PER_PROC(r5) ; Get the per_proc block
2180 lwz r6, pfPowerModes(r5) ; Get the supported power modes
2182 rlwinm. r0, r6, 0, pmDPLLVminb, pmDPLLVminb ; Is DPLL Vmin supported
2185 mfspr r4, hid2 ; Get HID2 value
2186 rlwimi r4, r3, 31-hid2vmin, hid2vmin, hid2vmin ; Insert the voltage mode bit
2187 mtspr hid2, r4 ; Set the voltage mode
2188 sync ; Make sure it is done
2195 ; unsigned int ml_scom_write(unsigned int reg, unsigned long long data)
2196 ; 64-bit machines only
2201 .globl EXT(ml_scom_write)
2205 rldicr r3,r3,8,47 ; Align register it correctly
2206 rldimi r5,r4,32,0 ; Merge the high part of data
2207 sync ; Clean up everything
2209 mtspr scomd,r5 ; Stick in the data
2210 mtspr scomc,r3 ; Set write to register
2214 mfspr r3,scomc ; Read back status
2218 ; unsigned int ml_read_scom(unsigned int reg, unsigned long long *data)
2219 ; 64-bit machines only
2221 ; ASM Callers: data (r4) can be zero and the 64 bit data will be returned in r5
2225 .globl EXT(ml_scom_read)
2229 mfsprg r0,2 ; Get the feature flags
2230 rldicr r3,r3,8,47 ; Align register it correctly
2231 rlwinm r0,r0,pfSCOMFixUpb+1,31,31 ; Set shift if we need a fix me up
2233 ori r3,r3,0x8000 ; Set to read data
2236 mtspr scomc,r3 ; Request the register
2237 mfspr r5,scomd ; Get the register contents
2238 mfspr r3,scomc ; Get back the status
2242 sld r5,r5,r0 ; Fix up if needed
2244 cmplwi r4, 0 ; If data pointer is null, just return
2245 beqlr ; the received data in r5
2246 std r5,0(r4) ; Pass back the received data
2250 ; Calculates the hdec to dec ratio
2254 .globl EXT(ml_hdec_ratio)
2258 li r0,0 ; Clear the EE bit (and everything else for that matter)
2259 mfmsr r11 ; Get the MSR
2260 mtmsrd r0,1 ; Set the EE bit only (do not care about RI)
2261 rlwinm r11,r11,0,MSR_EE_BIT,MSR_EE_BIT ; Isolate just the EE bit
2262 mfmsr r10 ; Refresh our view of the MSR (VMX/FP may have changed)
2263 or r12,r10,r11 ; Turn on EE if on before we turned it off
2265 mftb r9 ; Get time now
2266 mfspr r2,hdec ; Save hdec
2268 mhrcalc: mftb r8 ; Get time now
2269 sub r8,r8,r9 ; How many ticks?
2270 cmplwi r8,10000 ; 10000 yet?
2271 blt mhrcalc ; Nope...
2273 mfspr r9,hdec ; Get hdec now
2274 sub r3,r2,r9 ; How many ticks?
2275 mtmsrd r12,1 ; Flip EE on if needed
2282 ; Calculates the number of ticks to the supplied event and
2283 ; sets the decrementer. Never set the time for less that the
2284 ; minimum, which is 10, nor more than maxDec, which is usually 0x7FFFFFFF
2285 ; and never more than that but can be set by root.
2296 spOver: mftbu r8 ; Get upper time
2297 addic r2,r4,-kMin ; Subtract minimum from target
2299 addme r11,r3 ; Do you have any bits I could borrow?
2300 mftbu r10 ; Get upper again
2301 subfe r0,r0,r0 ; Get -1 if we went negative 0 otherwise
2302 subc r7,r2,r9 ; Subtract bottom and get carry
2303 cmplw r8,r10 ; Did timebase upper tick?
2304 subfe r6,r8,r11 ; Get the upper difference accounting for borrow
2305 lwz r12,maxDec(0) ; Get the maximum decrementer size
2306 addme r0,r0 ; Get -1 or -2 if anything negative, 0 otherwise
2307 addic r2,r6,-1 ; Set carry if diff < 2**32
2308 srawi r0,r0,1 ; Make all foxes
2309 subi r10,r12,kMin ; Adjust maximum for minimum adjust
2310 andc r7,r7,r0 ; Pin time at 0 if under minimum
2311 subfe r2,r2,r2 ; 0 if diff > 2**32, -1 otherwise
2312 sub r7,r7,r10 ; Negative if duration is less than (max - min)
2313 or r2,r2,r0 ; If the duration is negative, it is not too big
2314 srawi r0,r7,31 ; -1 if duration is too small
2315 and r7,r7,r2 ; Clear duration if high part too big
2316 and r7,r7,r0 ; Clear duration if low part too big
2317 bne-- spOver ; Timer ticked...
2318 add r3,r7,r12 ; Add back the max for total
2319 mtdec r3 ; Set the decrementer
projects / apple / xnu.git / blob