pexpert/pexpert/arm64/board_config.h

   1 /*
   2  * Copyright (c) 2007-2020 Apple Inc. All rights reserved.
   3  * Copyright (c) 2005-2006 Apple Computer, Inc. All rights reserved.
   4  */
   5 #ifndef _PEXPERT_ARM_BOARD_CONFIG_H
   6 #define _PEXPERT_ARM_BOARD_CONFIG_H
   7
   8 #include <mach/machine.h>
   9
  10 /*
  11  * Per-SoC configuration.  General order is:
  12  *
  13  * CPU type
  14  * CPU configuration
  15  * CPU feature disables / workarounds
  16  * CPU topology
  17  * Other platform configuration (e.g. DARTs, PPL)
  18  *
  19  * This should answer the question: "what's unique about this SoC?"
  20  *
  21  * arm64/H*.h should answer the question: "what's unique about this CPU core?"
  22  *
  23  * For __ARM_AMP__ systems that have different cache line sizes on different
  24  * clusters, MAX_L2_CLINE must reflect the largest L2 cache line size
  25  * across all clusters.
  26  */
  27
  28
  29 #ifdef ARM64_BOARD_CONFIG_T7000
  30 #include <pexpert/arm64/H7.h>
  31
  32 #define MAX_L2_CLINE                   6
  33 #define MAX_CPUS                       3
  34 #define MAX_CPU_CLUSTERS               1
  35 #endif  /* ARM64_BOARD_CONFIG_T7000 */
  36
  37 #ifdef ARM64_BOARD_CONFIG_T7001
  38 #include <pexpert/arm64/H7.h>
  39
  40 #define MAX_L2_CLINE                   6
  41 #define MAX_CPUS                       3
  42 #define MAX_CPU_CLUSTERS               1
  43 #endif  /* ARM64_BOARD_CONFIG_T7001 */
  44
  45 #ifdef ARM64_BOARD_CONFIG_S8000
  46 #include <pexpert/arm64/H8.h>
  47 #define MAX_CPUS                       2
  48 #define MAX_CPU_CLUSTERS               1
  49 /*
  50  * The L2 size for twister is in fact 3MB, not 4MB; we round up due
  51  * to the code being architected for power of 2 cache sizes, and rely
  52  * on the expected behavior that out of bounds operations will be
  53  * ignored.
  54  */
  55 #define MAX_L2_CLINE                   6
  56 #endif  /* ARM64_BOARD_CONFIG_S8000 */
  57
  58 #ifdef ARM64_BOARD_CONFIG_S8001
  59 #include <pexpert/arm64/H8.h>
  60 #define MAX_CPUS                       2
  61 #define MAX_CPU_CLUSTERS               1
  62 /*
  63  * The L2 size for twister is in fact 3MB, not 4MB; we round up due
  64  * to the code being architected for power of 2 cache sizes, and rely
  65  * on the expect behavior that out of bounds operations will be
  66  * ignored.
  67  */
  68 #define MAX_L2_CLINE                   6
  69 #endif  /* ARM64_BOARD_CONFIG_S8001 */
  70
  71 #ifdef ARM64_BOARD_CONFIG_T8010
  72 #include <pexpert/arm64/H9.h>
  73 #define MAX_CPUS                       3
  74 #define MAX_CPU_CLUSTERS               1
  75 /*
  76  * The L2 size for hurricane/zephyr is in fact 3MB, not 4MB; we round up due
  77  * to the code being architected for power of 2 cache sizes, and rely
  78  * on the expect behavior that out of bounds operations will be
  79  * ignored.
  80  */
  81 #define MAX_L2_CLINE                   7
  82
  83 #if DEVELOPMENT || DEBUG
  84 #define PMAP_CS                        1
  85 #define PMAP_CS_ENABLE                 0
  86 #endif
  87 #endif  /* ARM64_BOARD_CONFIG_T8010 */
  88
  89 #ifdef ARM64_BOARD_CONFIG_T8011
  90 #include <pexpert/arm64/H9.h>
  91
  92 #define MAX_L2_CLINE                   7
  93 #define MAX_CPUS                       3
  94 #define MAX_CPU_CLUSTERS               1
  95
  96 #if DEVELOPMENT || DEBUG
  97 #define PMAP_CS                        1
  98 #define PMAP_CS_ENABLE                 0
  99 #endif
 100 #endif  /* ARM64_BOARD_CONFIG_T8011 */
 101
 102 #ifdef ARM64_BOARD_CONFIG_T8015
 103 #include <pexpert/arm64/H10.h>
 104
 105 #define MAX_L2_CLINE                   7
 106 #define MAX_CPUS                       6
 107 #define MAX_CPU_CLUSTERS               2
 108
 109 #define BROKEN_FRIGGING_SLEEP          1 /* Spurious wake: See rdar://problem/29762505 */
 110
 111 #if DEVELOPMENT || DEBUG
 112 #define PMAP_CS                        1
 113 #define PMAP_CS_ENABLE                 0
 114 #endif
 115 #endif  /* ARM64_BOARD_CONFIG_T8015 */
 116
 117 #ifdef ARM64_BOARD_CONFIG_T8020
 118 #include <pexpert/arm64/H11.h>
 119
 120 #define MAX_L2_CLINE                   7
 121 #define MAX_CPUS                       8
 122 #define MAX_CPU_CLUSTERS               2
 123
 124 #define XNU_MONITOR                    1 /* Secure pmap runtime */
 125 #endif  /* ARM64_BOARD_CONFIG_T8020 */
 126
 127 #ifdef ARM64_BOARD_CONFIG_T8006
 128 /*
 129  * The T8006 consists of 2 Tempest cores (i.e. T8020 eCores) and for most
 130  * of our purposes here may be considered a functional subset of T8020.
 131  */
 132 #include <pexpert/arm64/H11.h>
 133
 134 #undef HAS_UNCORE_CTRS
 135 #ifdef XNU_TARGET_OS_WATCH // This check might be redundant
 136 #undef __APRR_SHADOW_SUPPORTED__
 137 #endif
 138
 139 #define MAX_L2_CLINE                   7
 140 #define MAX_CPUS                       2
 141 #define MAX_CPU_CLUSTERS               1
 142
 143 #define XNU_MONITOR                    1 /* Secure pmap runtime */
 144 #define XNU_MONITOR_T8020_DART         1 /* T8020 DART plugin for secure pmap runtime */
 145 #define T8020_DART_ALLOW_BYPASS        (1 << 1) /* DART allows translation bypass in certain cases */
 146 #define XNU_MONITOR_NVME_PPL           1 /* NVMe PPL plugin for secure pmap runtime */
 147 #define XNU_MONITOR_ANS2_SART          1 /* ANS2 SART plugin for secure pmap runtime */
 148 #define PMAP_CS                        1
 149 #define PMAP_CS_ENABLE                 1
 150 #define PREFER_ARM64_32_BINARIES
 151 #define PEXPERT_NO_3X_IMAGES           1
 152 #endif /* ARM64_BOARD_CONFIG_T8006 */
 153
 154 #ifdef ARM64_BOARD_CONFIG_T8027
 155 #include <pexpert/arm64/H11.h>
 156
 157 #define MAX_L2_CLINE                   7
 158 #define MAX_CPUS                       8
 159 #define MAX_CPU_CLUSTERS               2
 160
 161 #define XNU_MONITOR                    1 /* Secure pmap runtime */
 162 #define XNU_MONITOR_T8020_DART         1 /* T8020 DART plugin for secure pmap runtime */
 163 #define T8020_DART_ALLOW_BYPASS        (1 << 1) /* DART allows translation bypass in certain cases */
 164 #define XNU_MONITOR_NVME_PPL           1 /* NVMe PPL plugin for secure pmap runtime */
 165 #define XNU_MONITOR_ANS2_SART          1 /* ANS2 SART plugin for secure pmap runtime */
 166 #define PMAP_CS                        1
 167 #define PMAP_CS_ENABLE                 1
 168 #endif  /* ARM64_BOARD_CONFIG_T8027 */
 169
 170 #ifdef ARM64_BOARD_CONFIG_T8028
 171 #include <pexpert/arm64/H11.h>
 172
 173 #define MAX_L2_CLINE                   7
 174 #define MAX_CPUS                       8
 175 #define MAX_CPU_CLUSTERS               2
 176
 177 #define XNU_MONITOR                    1 /* Secure pmap runtime */
 178 #define XNU_MONITOR_T8020_DART         1 /* T8020 DART plugin for secure pmap runtime */
 179 #define T8020_DART_ALLOW_BYPASS        (1 << 1) /* DART allows translation bypass in certain cases */
 180 #define XNU_MONITOR_NVME_PPL           1 /* NVMe PPL plugin for secure pmap runtime */
 181 #define XNU_MONITOR_ANS2_SART          1 /* ANS2 SART plugin for secure pmap runtime */
 182 #define PMAP_CS                        1
 183 #define PMAP_CS_ENABLE                 1
 184 #endif  /* ARM64_BOARD_CONFIG_T8028 */
 185
 186 #ifdef ARM64_BOARD_CONFIG_T8030
 187 #include <pexpert/arm64/H12.h>
 188
 189 #define MAX_L2_CLINE                   7
 190 #define MAX_CPUS                       6
 191 #define MAX_CPU_CLUSTERS               2
 192
 193 #define XNU_MONITOR                    1 /* Secure pmap runtime */
 194 #define XNU_MONITOR_T8020_DART         1 /* T8020 DART plugin for secure pmap runtime */
 195 #define T8020_DART_ALLOW_BYPASS        (1 << 1) /* DART allows translation bypass in certain cases */
 196 #define XNU_MONITOR_NVME_PPL           1 /* NVMe PPL plugin for secure pmap runtime */
 197 #define XNU_MONITOR_ANS2_SART          1 /* ANS2 SART plugin for secure pmap runtime */
 198 #define XNU_MONITOR_UAT_PPL            1 /* UAT PPL plugin for secure pmap runtime */
 199 #define PMAP_CS                        1
 200 #define PMAP_CS_ENABLE                 1
 201 #endif  /* ARM64_BOARD_CONFIG_T8030 */
 202
 203 #ifdef ARM64_BOARD_CONFIG_T8101
 204 #include <pexpert/arm64/H13.h>
 205 #include <pexpert/arm64/spr_locks.h>
 206
 207 #define MAX_L2_CLINE                   7
 208 #define MAX_CPUS                       8
 209 #define MAX_CPU_CLUSTERS               2
 210
 211 #define XNU_MONITOR                    1 /* Secure pmap runtime */
 212 #endif  /* ARM64_BOARD_CONFIG_T8101 */
 213
 214 #ifdef ARM64_BOARD_CONFIG_T8103
 215 #include <pexpert/arm64/H13.h>
 216 #include <pexpert/arm64/spr_locks.h>
 217
 218 #define MAX_L2_CLINE                   7
 219 #define MAX_CPUS                       8
 220 #define MAX_CPU_CLUSTERS               2
 221
 222 #define XNU_MONITOR                    1 /* Secure pmap runtime */
 223 #endif  /* ARM64_BOARD_CONFIG_T8103 */
 224
 225
 226
 227
 228 #ifdef ARM64_BOARD_CONFIG_BCM2837
 229 #include <pexpert/arm64/BCM2837.h>
 230
 231 #define MAX_L2_CLINE                   6
 232 #define MAX_CPUS                       4
 233 #define MAX_CPU_CLUSTERS               1
 234
 235 #define CORE_NCTRS                     8 /* Placeholder; KPC is not enabled for this target */
 236 #endif  /* ARM64_BOARD_CONFIG_BCM2837 */
 237
 238 #ifndef HAS_UNCORE_CTRS
 239 #undef UNCORE_VERSION
 240 #undef UNCORE_PER_CLUSTER
 241 #undef UNCORE_NCTRS
 242 #endif
 243
 244 #if MAX_CPU_CLUSTERS == 1
 245 #undef __ARM_AMP__
 246 #endif
 247
 248 #ifndef MAX_CPU_CLUSTER_PHY_ID
 249 #define MAX_CPU_CLUSTER_PHY_ID (MAX_CPU_CLUSTERS - 1)
 250 #endif
 251
 252 #ifdef PREFER_ARM64_32_BINARIES
 253 #define PREFERRED_USER_CPU_TYPE CPU_TYPE_ARM64_32
 254 #define PREFERRED_USER_CPU_SUBTYPE CPU_SUBTYPE_ARM64_32_V8
 255 #endif
 256
 257 #endif /* ! _PEXPERT_ARM_BOARD_CONFIG_H */