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1 /*
2 * Copyright (c) 2007-2016 Apple Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28 /*
29 * @OSF_COPYRIGHT@
30 */
31 /* CMU_ENDHIST */
32 /*
33 * Mach Operating System
34 * Copyright (c) 1991,1990 Carnegie Mellon University
35 * All Rights Reserved.
36 *
37 * Permission to use, copy, modify and distribute this software and its
38 * documentation is hereby granted, provided that both the copyright
39 * notice and this permission notice appear in all copies of the
40 * software, derivative works or modified versions, and any portions
41 * thereof, and that both notices appear in supporting documentation.
42 *
43 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
44 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
45 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
46 *
47 * Carnegie Mellon requests users of this software to return to
48 *
49 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
50 * School of Computer Science
51 * Carnegie Mellon University
52 * Pittsburgh PA 15213-3890
53 *
54 * any improvements or extensions that they make and grant Carnegie Mellon
55 * the rights to redistribute these changes.
56 */
57
58 /*
59 */
60
61 /*
62 * Processor registers for ARM
63 */
64 #ifndef _ARM_PROC_REG_H_
65 #define _ARM_PROC_REG_H_
66
67 #if __ARM_KERNEL_PROTECT__
68 /*
69 * This feature is not currently implemented for 32-bit ARM CPU architectures.
70 * A discussion of this feature for 64-bit ARM CPU architectures can be found
71 * in the ARM64 version of this file.
72 */
73 #if __arm__
74 #error __ARM_KERNEL_PROTECT__ is not supported on ARM32
75 #endif
76 #endif /* __ARM_KERNEL_PROTECT__ */
77
78 #if defined (__arm64__)
79 #include <pexpert/arm64/board_config.h>
80 #elif defined (__arm__)
81 #include <pexpert/arm/board_config.h>
82 #endif
83
84 #if defined (ARMA7)
85 #define __ARM_ARCH__ 7
86 #define __ARM_SUB_ARCH__ CPU_ARCH_ARMv7k
87 #define __ARM_VMSA__ 7
88 #define __ARM_VFP__ 3
89 #if defined(__XNU_UP__)
90 #define __ARM_SMP__ 0
91 #else
92 #define __ARM_SMP__ 1
93 /* For SMP kernels, force physical aperture to be mapped at PTE level so that its mappings
94 * can be updated to reflect cache attribute changes on alias mappings. This prevents
95 * prefetched physical aperture cachelines from becoming dirty in L1 due to a write to
96 * an uncached alias mapping on the same core. Subsequent uncached writes from another
97 * core may not snoop this line, and the dirty line may end up being evicted later to
98 * effectively overwrite the uncached writes from other cores. */
99 #define __ARM_PTE_PHYSMAP__ 1
100 #endif
101 /* __ARMA7_SMP__ controls whether we are consistent with the A7 MP_CORE spec; needed because entities other than
102 * the xnu-managed processors may need to snoop our cache operations.
103 */
104 #define __ARMA7_SMP__ 1
105 #define __ARM_COHERENT_CACHE__ 1
106 #define __ARM_L1_PTW__ 1
107 #define __ARM_DEBUG__ 7
108 #define __ARM_USER_PROTECT__ 1
109 #define __ARM_TIME_TIMEBASE_ONLY__ 1
110
111 #elif defined (APPLECYCLONE)
112 #define __ARM_ARCH__ 8
113 #define __ARM_VMSA__ 8
114 #define __ARM_SMP__ 1
115 #define __ARM_VFP__ 4
116 #define __ARM_COHERENT_CACHE__ 1
117 #define __ARM_COHERENT_IO__ 1
118 #define __ARM_IC_NOALIAS_ICACHE__ 1
119 #define __ARM_L1_PTW__ 1
120 #define __ARM_DEBUG__ 7
121 #define __ARM_ENABLE_SWAP__ 1
122 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
123 #define __ARM64_PMAP_SUBPAGE_L1__ 1
124 #define __ARM_KERNEL_PROTECT__ 1
125
126 #elif defined (APPLETYPHOON)
127 #define __ARM_ARCH__ 8
128 #define __ARM_VMSA__ 8
129 #define __ARM_SMP__ 1
130 #define __ARM_VFP__ 4
131 #define __ARM_COHERENT_CACHE__ 1
132 #define __ARM_COHERENT_IO__ 1
133 #define __ARM_IC_NOALIAS_ICACHE__ 1
134 #define __ARM_L1_PTW__ 1
135 #define __ARM_DEBUG__ 7
136 #define __ARM_ENABLE_SWAP__ 1
137 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
138 #define __ARM64_PMAP_SUBPAGE_L1__ 1
139 #define __ARM_KERNEL_PROTECT__ 1
140
141 #elif defined (APPLETWISTER)
142 #define __ARM_ARCH__ 8
143 #define __ARM_VMSA__ 8
144 #define __ARM_SMP__ 1
145 #define __ARM_VFP__ 4
146 #define __ARM_COHERENT_CACHE__ 1
147 #define __ARM_COHERENT_IO__ 1
148 #define __ARM_IC_NOALIAS_ICACHE__ 1
149 #define __ARM_L1_PTW__ 1
150 #define __ARM_DEBUG__ 7
151 #define __ARM_ENABLE_SWAP__ 1
152 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
153 #define __ARM_16K_PG__ 1
154 #define __ARM64_PMAP_SUBPAGE_L1__ 1
155 #define __ARM_KERNEL_PROTECT__ 1
156
157 #elif defined (APPLEHURRICANE)
158 #define __ARM_ARCH__ 8
159 #define __ARM_VMSA__ 8
160 #define __ARM_SMP__ 1
161 #define __ARM_VFP__ 4
162 #define __ARM_COHERENT_CACHE__ 1
163 #define __ARM_COHERENT_IO__ 1
164 #define __ARM_IC_NOALIAS_ICACHE__ 1
165 #define __ARM_L1_PTW__ 1
166 #define __ARM_DEBUG__ 7
167 #define __ARM_ENABLE_SWAP__ 1
168 #define __ARM_V8_CRYPTO_EXTENSIONS__ 1
169 #define __ARM_16K_PG__ 1
170 #define __ARM64_PMAP_SUBPAGE_L1__ 1
171 #define __ARM_KERNEL_PROTECT__ 1
172 #define __ARM_GLOBAL_SLEEP_BIT__ 1
173 #define __ARM_PAN_AVAILABLE__ 1
174
175 #else
176 #error processor not supported
177 #endif
178
179 #if defined(ARM_BOARD_WFE_TIMEOUT_NS)
180 #define __ARM_ENABLE_WFE_ 1
181 #else
182 #define __ARM_ENABLE_WFE_ 0
183 #endif
184
185 #define CONFIG_THREAD_GROUPS 0
186
187
188 #ifdef XNU_KERNEL_PRIVATE
189
190 #if __ARM_VFP__
191 #define ARM_VFP_DEBUG 0
192 #endif
193
194 #endif
195
196
197
198 /*
199 * FSR registers
200 *
201 * CPSR: Current Program Status Register
202 * SPSR: Saved Program Status Registers
203 *
204 * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0
205 * +-----------------------------------------------------------+
206 * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE |
207 * +-----------------------------------------------------------+
208 */
209
210 /*
211 * Flags
212 */
213 #define PSR_NF 0x80000000 /* Negative/Less than */
214 #define PSR_ZF 0x40000000 /* Zero */
215 #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */
216 #define PSR_VF 0x10000000 /* Overflow */
217 #define PSR_QF 0x08000000 /* saturation flag (QADD ARMv5) */
218
219 /*
220 * Modified execution mode flags
221 */
222 #define PSR_JF 0x01000000 /* Jazelle flag (BXJ ARMv5) */
223 #define PSR_EF 0x00000200 /* mixed-endian flag (SETEND ARMv6) */
224 #define PSR_AF 0x00000100 /* precise abort flag (ARMv6) */
225 #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */
226 #define PSR_TFb 5 /* thumb flag (BX ARMv4T) */
227
228 /*
229 * Interrupts
230 */
231 #define PSR_IRQFb 7 /* IRQ : 0 = IRQ enable */
232 #define PSR_IRQF 0x00000080 /* IRQ : 0 = IRQ enable */
233 #define PSR_FIQF 0x00000040 /* FIQ : 0 = FIQ enable */
234
235 /*
236 * CPU mode
237 */
238 #define PSR_USER_MODE 0x00000010 /* User mode */
239 #define PSR_FIQ_MODE 0x00000011 /* FIQ mode */
240 #define PSR_IRQ_MODE 0x00000012 /* IRQ mode */
241 #define PSR_SVC_MODE 0x00000013 /* Supervisor mode */
242 #define PSR_ABT_MODE 0x00000017 /* Abort mode */
243 #define PSR_UND_MODE 0x0000001B /* Undefined mode */
244
245 #define PSR_MODE_MASK 0x0000001F
246 #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE)
247 #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE)
248
249 #define PSR_USERDFLT PSR_USER_MODE
250 #define PSR_USER_MASK (PSR_AF | PSR_IRQF | PSR_FIQF | PSR_MODE_MASK)
251 #define PSR_USER_SET PSR_USER_MODE
252
253 #define PSR_INTMASK PSR_IRQF /* Interrupt disable */
254
255 /*
256 * FPEXC: Floating-Point Exception Register
257 */
258
259 #define FPEXC_EX 0x80000000 /* Exception status */
260 #define FPEXC_EX_BIT 31
261 #define FPEXC_EN 0x40000000 /* VFP : 1 = EN enable */
262 #define FPEXC_EN_BIT 30
263
264
265 /*
266 * FPSCR: Floating-point Status and Control Register
267 */
268
269 #define FPSCR_DN 0x02000000 /* Default NaN */
270 #define FPSCR_FZ 0x01000000 /* Flush to zero */
271
272 #define FPSCR_DEFAULT FPSCR_DN | FPSCR_FZ
273
274
275 /*
276 * FSR registers
277 *
278 * IFSR: Instruction Fault Status Register
279 * DFSR: Data Fault Status Register
280 */
281 #define FSR_ALIGN 0x00000001 /* Alignment */
282 #define FSR_DEBUG 0x00000002 /* Debug (watch/break) */
283 #define FSR_ICFAULT 0x00000004 /* Fault on instruction cache maintenance */
284 #define FSR_SFAULT 0x00000005 /* Translation Section */
285 #define FSR_PFAULT 0x00000007 /* Translation Page */
286 #define FSR_SACCESS 0x00000003 /* Section access */
287 #define FSR_PACCESS 0x00000006 /* Page Access */
288 #define FSR_SDOM 0x00000009 /* Domain Section */
289 #define FSR_PDOM 0x0000000B /* Domain Page */
290 #define FSR_SPERM 0x0000000D /* Permission Section */
291 #define FSR_PPERM 0x0000000F /* Permission Page */
292 #define FSR_EXT 0x00001000 /* External (Implementation Defined Classification) */
293
294 #define FSR_MASK 0x0000040F /* Valid bits */
295 #define FSR_ALIGN_MASK 0x0000040D /* Valid bits to check align */
296
297 #define DFSR_WRITE 0x00000800 /* write data abort fault */
298
299 #if defined (ARMA7) || defined (APPLE_ARM64_ARCH_FAMILY)
300
301 #define TEST_FSR_VMFAULT(status) \
302 (((status) == FSR_PFAULT) \
303 || ((status) == FSR_PPERM) \
304 || ((status) == FSR_SFAULT) \
305 || ((status) == FSR_SPERM) \
306 || ((status) == FSR_ICFAULT) \
307 || ((status) == FSR_SACCESS) \
308 || ((status) == FSR_PACCESS))
309
310 #else
311
312 #error Incompatible CPU type configured
313
314 #endif
315
316 /*
317 * Cache configuration
318 */
319
320 #if defined (ARMA7)
321
322 /* I-Cache */
323 #define MMU_I_CLINE 5 /* cache line size as 1<<MMU_I_CLINE (32) */
324
325 /* D-Cache */
326 #define MMU_CSIZE 15 /* cache size as 1<<MMU_CSIZE (32K) */
327 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
328 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
329 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
330 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
331
332 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
333 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
334
335 #define __ARM_L2CACHE__ 1
336
337 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<MMU_CSIZE */
338 #define L2_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
339 #define L2_NWAY 3 /* set associativity 1<<MMU_NWAY (8) */
340 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
341 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
342 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
343
344 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<MMU_SWAY */
345 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<MMU_NSET */
346
347 #elif defined (APPLECYCLONE)
348
349 /* I-Cache */
350 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
351
352 /* D-Cache */
353 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
354 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
355 #define MMU_NWAY 1 /* set associativity 1<<MMU_NWAY (2) */
356 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
357 #define MMU_I7WAY 31 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
358 #define MMU_I9WAY 31 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
359
360 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
361 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
362
363 #define __ARM_L2CACHE__ 1
364
365 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
366 #define L2_CLINE 6 /* cache line size as 1<<L2_CLINE (64) */
367 #define L2_NWAY 3 /* set associativity 1<<L2_NWAY (8) */
368 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
369 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<L2_I7WAY */
370 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<L2_I9WAY */
371
372 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
373 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
374
375 #elif defined (APPLETYPHOON)
376
377 /* I-Cache */
378 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
379
380 /* D-Cache */
381 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
382 #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */
383 #define MMU_NWAY 1 /* set associativity 1<<MMU_NWAY (2) */
384 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
385 #define MMU_I7WAY 31 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
386 #define MMU_I9WAY 31 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
387
388 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
389 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
390
391 #define __ARM_L2CACHE__ 1
392
393 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
394 #define L2_CLINE 6 /* cache line size as 1<<L2_CLINE (64) */
395 #define L2_NWAY 3 /* set associativity 1<<L2_NWAY (8) */
396 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
397 #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<L2_I7WAY */
398 #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<L2_I9WAY */
399
400 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
401 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
402
403 #elif defined (APPLETWISTER)
404
405 /* I-Cache */
406 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
407
408 /* D-Cache */
409 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
410 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
411 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
412 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
413 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
414 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
415
416 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
417 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
418
419 /* L2-Cache */
420 #define __ARM_L2CACHE__ 1
421
422 /*
423 * For reasons discussed in the platform expert code, we round the reported
424 * L2 size to 4MB, and adjust the other parameters accordingly.
425 */
426 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
427 #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */
428 #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */
429 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
430 #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */
431 #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */
432
433 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
434 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
435
436 #elif defined (APPLEHURRICANE)
437
438 /* I-Cache */
439 #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */
440
441 /* D-Cache */
442 #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */
443 #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */
444 #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */
445 #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */
446 #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */
447 #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */
448
449 #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */
450 #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */
451
452 /* L2-Cache */
453 #define __ARM_L2CACHE__ 1
454
455 /*
456 * For reasons discussed in the platform expert code, we round the reported
457 * L2 size to 4MB, and adjust the other parameters accordingly.
458 */
459 #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */
460 #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */
461 #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */
462 #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */
463 #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */
464 #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */
465
466 #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */
467 #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */
468
469 #else
470 #error processor not supported
471 #endif
472
473
474 #if (__ARM_VMSA__ <= 7)
475
476 /*
477 * SCTLR: System Control Register
478 */
479 /*
480 * System Control Register (SCTLR)
481 *
482 * 31 30 29 28 27 25 24 22 21 20 19 17 15 14 13 12 11 10 5 2 1 0
483 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
484 * |0|TE|AFE|TRE|NMFI|0|EE|VE|11|FI|UWXN|WXN|1|HA|1|0|RR| V| I| Z|SW|000|1|C15BEN|11|C|A|M|
485 * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+
486 *
487 * TE Thumb Exception enable
488 * AFE Access flag enable
489 * TRE TEX remap enable
490 * NMFI Non-maskable FIQ (NMFI) support
491 * EE Exception Endianness
492 * VE Interrupt Vectors Enable
493 * FI Fast interrupts configuration enable
494 * ITD IT Disable
495 * UWXN Unprivileged write permission implies PL1 XN
496 * WXN Write permission implies XN
497 * HA Hardware Access flag enable
498 * RR Round Robin select
499 * V High exception vectors
500 * I Instruction cache enable
501 * Z Branch prediction enable
502 * SW SWP/SWPB enable
503 * C15BEN CP15 barrier enable
504 * C Cache enable
505 * A Alignment check enable
506 * M MMU enable
507 */
508
509 #define SCTLR_RESERVED 0x82DD8394
510
511 #define SCTLR_ENABLE 0x00000001 /* MMU enable */
512 #define SCTLR_ALIGN 0x00000002 /* Alignment check enable */
513 #define SCTLR_DCACHE 0x00000004 /* Data or Unified Cache enable */
514 #define SCTLR_BEN 0x00000040 /* CP15 barrier enable */
515 #define SCTLR_SW 0x00000400 /* SWP/SWPB Enable */
516 #define SCTLR_PREDIC 0x00000800 /* Branch prediction enable */
517 #define SCTLR_ICACHE 0x00001000 /* Instruction cache enabled. */
518 #define SCTLR_HIGHVEC 0x00002000 /* Vector table at 0xffff0000 */
519 #define SCTLR_RROBIN 0x00004000 /* Round Robin replacement */
520 #define SCTLR_HA 0x00020000 /* Hardware Access flag enable */
521 #define SCTLR_NMFI 0x08000000 /* Non-maskable FIQ */
522 #define SCTLR_TRE 0x10000000 /* TEX remap enable */
523 #define SCTLR_AFE 0x20000000 /* Access flag enable */
524 #define SCTLR_TE 0x40000000 /* Thumb Exception enable */
525
526 #define SCTLR_DEFAULT (SCTLR_AFE|SCTLR_TRE|SCTLR_HIGHVEC|SCTLR_ICACHE|SCTLR_PREDIC|SCTLR_DCACHE|SCTLR_ENABLE)
527
528
529 /*
530 * PRRR: Primary Region Remap Register
531 *
532 * 31 24 20 19 18 17 16 0
533 * +---------------------------------------------------------------+
534 * | NOSn | Res |NS1|NS0|DS1|DS0| TRn |
535 * +---------------------------------------------------------------+
536 */
537
538 #define PRRR_NS1 0x00080000
539 #define PRRR_NS0 0x00040000
540 #define PRRR_DS1 0x00020000
541 #define PRRR_DS0 0x00010000
542 #define PRRR_NOSn_ISH(region) (0x1<<((region)+24))
543
544 #if defined (ARMA7)
545 #define PRRR_SETUP (0x1F08022A)
546 #else
547 #error processor not supported
548 #endif
549
550 /*
551 * NMRR, Normal Memory Remap Register
552 *
553 * 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0
554 * +---------------------------------------------------------------+
555 * |OR7|OR6|OR5|OR4|OR3|OR2|OR1|OR0|IR7|IR6|IR5|IR4|IR3|IR2|IR1|IR0|
556 * +---------------------------------------------------------------+
557 */
558
559 #define NMRR_DISABLED 0x0 /* Non-cacheable */
560 #define NMRR_WRITEBACK 0x1 /* Write-Back, Write-Allocate */
561 #define NMRR_WRITETHRU 0x2 /* Write-Through, no Write-Allocate */
562 #define NMRR_WRITEBACKNO 0x3 /* Write-Back, no Write-Allocate */
563
564 #if defined (ARMA7)
565 #define NMRR_SETUP (0x01210121)
566 #else
567 #error processor not supported
568 #endif
569
570 /*
571 * TTBR: Translation Table Base Register
572 *
573 */
574
575 #define TTBR_IRGN_DISBALED 0x00000000 /* inner non-cacheable */
576 #define TTBR_IRGN_WRITEBACK 0x00000040 /* inner write back and allocate */
577 #define TTBR_IRGN_WRITETHRU 0x00000001 /* inner write thru */
578 #define TTBR_IRGN_WRITEBACKNO 0x00000041 /* inner write back no allocate */
579
580 #define TTBR_RGN_DISBALED 0x00000000 /* outer non-cacheable */
581 #define TTBR_RGN_WRITEBACK 0x00000008 /* outer write back and allocate */
582 #define TTBR_RGN_WRITETHRU 0x00000010 /* outer write thru outer cache */
583 #define TTBR_RGN_WRITEBACKNO 0x00000018 /* outer write back no allocate */
584
585 #define TTBR_SHARED 0x00000002 /* Shareable memory atribute */
586 #define TTBR_SHARED_NOTOUTER 0x00000020 /* Outer not shareable memory atribute */
587
588 #if defined (ARMA7)
589 #define TTBR_SETUP (TTBR_RGN_WRITEBACK|TTBR_IRGN_WRITEBACK|TTBR_SHARED)
590 #else
591 #error processor not supported
592 #endif
593
594 /*
595 * TTBCR: Translation Table Base Control register
596 *
597 * 31 3 2 0
598 * +----------+
599 * | zero | N |
600 * +----------+
601 *
602 * If N=0, always use translation table base register 0. Otherwise, if
603 * bits [31:32-N] of the address are all zero use base register 0. Otherwise,
604 * use base register 1.
605 *
606 * Reading from this register also returns the page table boundary for TTB0.
607 * Writing to it updates the boundary for TTB0. (0=16KB, 1=8KB, 2=4KB, etc...)
608 */
609
610 #define TTBCR_N_1GB_TTB0 0x2 /* 1 GB TTB0, 3GB TTB1 */
611 #define TTBCR_N_2GB_TTB0 0x1 /* 2 GB TTB0, 2GB TTB1 */
612 #define TTBCR_N_4GB_TTB0 0x0 /* 4 GB TTB0 */
613 #define TTBCR_N_MASK 0x3
614
615
616
617 /*
618 * ARM Page Granule
619 */
620 #define ARM_PGSHIFT 12
621 #define ARM_PGBYTES (1 << ARM_PGSHIFT)
622 #define ARM_PGMASK (ARM_PGBYTES-1)
623
624 /*
625 * DACR: Domain Access Control register
626 */
627
628 #define DAC_FAULT 0x0 /* invalid domain - everyone loses */
629 #define DAC_CLIENT 0x1 /* client domain - use AP bits */
630 #define DAC_RESERVE 0x2 /* reserved domain - undefined */
631 #define DAC_MANAGER 0x3 /* manager domain - all access */
632 #define DACR_SET(dom, x) ((x)<<((dom)<<1))
633
634
635 #define ARM_DOM_DEFAULT 0 /* domain that forces AP use */
636 #define ARM_DAC_SETUP 0x1
637
638 /*
639 * ARM 2-level Page Table support
640 */
641
642 /*
643 * Memory Attribute Index
644 */
645 #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled */
646 #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes */
647 #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled */
648 #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer */
649 #define CACHE_ATTRINDX_INNERWRITEBACK 0x4 /* inner cache enabled, buffer enabled, write allocate */
650 #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE
651 #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK
652
653
654 /*
655 * Access protection bit values
656 */
657 #define AP_RWNA 0x0 /* priv=read-write, user=no-access */
658 #define AP_RWRW 0x1 /* priv=read-write, user=read-write */
659 #define AP_RONA 0x2 /* priv=read-only , user=no-access */
660 #define AP_RORO 0x3 /* priv=read-only , user=read-only */
661
662 /*
663 * L1 Translation table
664 *
665 * Each translation table is up to 16KB
666 * 4096 32-bit entries of 1MB of address space.
667 */
668
669 #define ARM_TT_L1_SIZE 0x00100000 /* size of area covered by a tte */
670 #define ARM_TT_L1_OFFMASK 0x000FFFFF /* offset within an L1 entry */
671 #define ARM_TT_L1_TABLE_OFFMASK 0x000FFFFF /* offset within an L1 entry */
672 #define ARM_TT_L1_BLOCK_OFFMASK 0x000FFFFF /* offset within an L1 entry */
673 #define ARM_TT_L1_SUPER_OFFMASK 0x00FFFFFF /* offset within an L1 entry */
674 #define ARM_TT_L1_SHIFT 20 /* page descriptor shift */
675 #define ARM_TT_L1_INDEX_MASK 0xfff00000 /* mask for getting index in L1 table from virtual address */
676
677 #define ARM_TT_L1_PT_SIZE (4 * ARM_TT_L1_SIZE) /* 4 L1 table entries required to consume 1 L2 pagetable page */
678 #define ARM_TT_L1_PT_OFFMASK (ARM_TT_L1_PT_SIZE - 1)
679
680 /*
681 * L2 Translation table
682 *
683 * Each translation table is up to 1KB
684 * 4096 32-bit entries of 1MB (2^30) of address space.
685 */
686
687 #define ARM_TT_L2_SIZE 0x00001000 /* size of area covered by a tte */
688 #define ARM_TT_L2_OFFMASK 0x00000FFF /* offset within an L2 entry */
689 #define ARM_TT_L2_SHIFT 12 /* page descriptor shift */
690 #define ARM_TT_L2_INDEX_MASK 0x000ff000 /* mask for getting index in L2 table from virtual address */
691
692 /*
693 * Convenience definitions for:
694 * ARM_TT_LEAF: The last level of the configured page table format.
695 * ARM_TT_TWIG: The second to last level of the configured page table format.
696 * ARM_TT_ROOT: The first level of the configured page table format.
697 *
698 * My apologies to any botanists who may be reading this.
699 */
700 #define ARM_TT_LEAF_SIZE ARM_TT_L2_SIZE
701 #define ARM_TT_LEAF_OFFMASK ARM_TT_L2_OFFMASK
702 #define ARM_TT_LEAF_SHIFT ARM_TT_L2_SHIFT
703 #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L2_INDEX_MASK
704
705 #define ARM_TT_TWIG_SIZE ARM_TT_L1_SIZE
706 #define ARM_TT_TWIG_OFFMASK ARM_TT_L1_OFFMASK
707 #define ARM_TT_TWIG_SHIFT ARM_TT_L1_SHIFT
708 #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L1_INDEX_MASK
709
710 #define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE
711 #define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK
712 #define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT
713 #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK
714
715 /*
716 * Level 1 Translation Table Entry
717 *
718 * page table entry
719 *
720 * 31 10 9 8 5 4 2 0
721 * +----------------------+-+----+--+--+--+
722 * | page table base addr | |dom |XN|00|01|
723 * +----------------------+-+----+--+--+--+
724 *
725 * direct (1MB) section entry
726 *
727 * 31 20 18 15 12 10 9 8 5 4 2 0
728 * +------------+--+-+-+-+---+--+-+----+--+--+--+
729 * | base addr |00|G|S|A|TEX|AP| |dom |XN|CB|10|
730 * +------------+--+-+-+-+---+--+-+----+--+--+--+
731 *
732 * super (16MB) section entry
733 *
734 * 31 24 23 18 15 12 10 9 8 5 4 2 0
735 * +---------+------+-+-+-+---+--+-+----+--+--+--+
736 * |base addr|000001|G|S|A|TEX|AP| |dom |XN|CB|10|
737 * +---------+------+-+-+-+---+--+-+----+--+--+--+
738 *
739 * where:
740 * 'G' is the notGlobal bit
741 * 'S' is the shared bit
742 * 'A' in the access permission extension (APX) bit
743 * 'TEX' remap register control bits
744 * 'AP' is the access protection
745 * 'dom' is the domain for the translation
746 * 'XN' is the eXecute Never bit
747 * 'CB' is the cache/buffer attribute
748 */
749
750 #define ARM_TTE_EMPTY 0x00000000 /* unasigned entry */
751
752 #define ARM_TTE_TYPE_FAULT 0x00000000 /* fault entry type */
753 #define ARM_TTE_TYPE_TABLE 0x00000001 /* page table type */
754 #define ARM_TTE_TYPE_BLOCK 0x00000002 /* section entry type */
755 #define ARM_TTE_TYPE_MASK 0x00000003 /* mask for extracting the type */
756
757 #define ARM_TTE_BLOCK_NGSHIFT 17
758 #define ARM_TTE_BLOCK_NG_MASK 0x00020000 /* mask to determine notGlobal bit */
759 #define ARM_TTE_BLOCK_NG 0x00020000 /* value for a per-process mapping */
760
761 #define ARM_TTE_BLOCK_SHSHIFT 16
762 #define ARM_TTE_BLOCK_SH_MASK 0x00010000 /* shared (SMP) mapping mask */
763 #define ARM_TTE_BLOCK_SH 0x00010000 /* shared (SMP) mapping */
764
765 #define ARM_TTE_BLOCK_CBSHIFT 2
766 #define ARM_TTE_BLOCK_CB(x) ((x) << ARM_TTE_BLOCK_CBSHIFT)
767 #define ARM_TTE_BLOCK_CB_MASK (3<< ARM_TTE_BLOCK_CBSHIFT)
768
769 #define ARM_TTE_BLOCK_AP0SHIFT 10
770 #define ARM_TTE_BLOCK_AP0 (1<<ARM_TTE_BLOCK_AP0SHIFT)
771 #define ARM_TTE_BLOCK_AP0_MASK (1<<ARM_TTE_BLOCK_AP0SHIFT)
772
773 #define ARM_TTE_BLOCK_AP1SHIFT 11
774 #define ARM_TTE_BLOCK_AP1 (1<<ARM_TTE_BLOCK_AP1SHIFT)
775 #define ARM_TTE_BLOCK_AP1_MASK (1<<ARM_TTE_BLOCK_AP1SHIFT)
776
777 #define ARM_TTE_BLOCK_AP2SHIFT 15
778 #define ARM_TTE_BLOCK_AP2 (1<<ARM_TTE_BLOCK_AP2SHIFT)
779 #define ARM_TTE_BLOCK_AP2_MASK (1<<ARM_TTE_BLOCK_AP2SHIFT)
780
781
782 /* access protections */
783 #define ARM_TTE_BLOCK_AP(ap) ((((ap)&0x1)<<ARM_TTE_BLOCK_AP1SHIFT) \
784 | ((((ap)>>1)&0x1)<<ARM_TTE_BLOCK_AP2SHIFT))
785
786 /* mask access protections */
787 #define ARM_TTE_BLOCK_APMASK (ARM_TTE_BLOCK_AP1_MASK \
788 | ARM_TTE_BLOCK_AP2_MASK)
789
790 #define ARM_TTE_BLOCK_AF ARM_TTE_BLOCK_AP0 /* value for access */
791 #define ARM_TTE_BLOCK_AFMASK ARM_TTE_BLOCK_AP0_MASK /* access mask */
792
793 #define ARM_TTE_TABLE_MASK 0xFFFFFC00 /* mask for a L2 page table entry */
794 #define ARM_TTE_TABLE_SHIFT 10 /* shift for L2 page table phys address */
795
796 #define ARM_TTE_BLOCK_L1_MASK 0xFFF00000 /* mask to extract phys address from L1 section entry */
797 #define ARM_TTE_BLOCK_L1_SHIFT 20 /* shift for 1MB section phys address */
798
799 #define ARM_TTE_SUPER_L1_MASK 0xFF000000 /* mask to extract phys address from L1 super entry */
800 #define ARM_TTE_SUPER_L1_SHIFT 24 /* shift for 16MB section phys address */
801
802 #define ARM_TTE_BLOCK_SUPER 0x00040000 /* make section a 16MB section */
803 #define ARM_TTE_BLOCK_SUPER_MASK 0x00F40000 /* make section a 16MB section */
804
805 #define ARM_TTE_BLOCK_NXSHIFT 4
806 #define ARM_TTE_BLOCK_NX 0x00000010 /* section is no execute */
807 #define ARM_TTE_BLOCK_NX_MASK 0x00000010 /* mask for extracting no execute bit */
808 #define ARM_TTE_BLOCK_PNX ARM_TTE_BLOCK_NX
809
810 #define ARM_TTE_BLOCK_TEX0SHIFT 12
811 #define ARM_TTE_BLOCK_TEX0 (1<<ARM_TTE_BLOCK_TEX0SHIFT)
812 #define ARM_TTE_BLOCK_TEX0_MASK (1<<ARM_TTE_BLOCK_TEX0SHIFT)
813
814 #define ARM_TTE_BLOCK_TEX1SHIFT 13
815 #define ARM_TTE_BLOCK_TEX1 (1<<ARM_TTE_BLOCK_TEX1SHIFT)
816 #define ARM_TTE_BLOCK_TEX1_MASK (1<<ARM_TTE_BLOCK_TEX1SHIFT)
817
818 #define ARM_TTE_BLOCK_TEX2SHIFT 14
819 #define ARM_TTE_BLOCK_TEX2 (1<<ARM_TTE_BLOCK_TEX2SHIFT)
820 #define ARM_TTE_BLOCK_TEX2_MASK (1<<ARM_TTE_BLOCK_TEX2SHIFT)
821
822
823 /* mask memory attributes index */
824 #define ARM_TTE_BLOCK_ATTRINDX(i) ((((i)&0x3)<<ARM_TTE_BLOCK_CBSHIFT) \
825 | ((((i)>>2)&0x1)<<ARM_TTE_BLOCK_TEX0SHIFT))
826
827 /* mask memory attributes index */
828 #define ARM_TTE_BLOCK_ATTRINDXMASK (ARM_TTE_BLOCK_CB_MASK \
829 | ARM_TTE_BLOCK_TEX0_MASK)
830
831
832 /*
833 * Level 2 Page table entries
834 *
835 * The following page table entry types are possible:
836 *
837 * fault page entry
838 * 31 2 0
839 * +----------------------------------------+--+
840 * | ignored |00|
841 * +----------------------------------------+--+
842 *
843 * large (64KB) page entry
844 * 31 16 15 12 9 6 4 3 2 0
845 * +----------------+--+---+-+-+-+---+--+-+-+--+
846 * | base phys addr |XN|TEX|G|S|A|000|AP|C|B|01|
847 * +----------------+--+---+-+-+-+---+--+-+-+--+
848 *
849 * small (4KB) page entry
850 * 31 12 9 6 4 3 2 1 0
851 * +-----------------------+-+-+-+---+--+-+-+-+--+
852 * | base phys addr |G|S|A|TEX|AP|C|B|1|XN|
853 * +-----------------------+-+-+-+---+--+-+-+-+--+
854 *
855 * also where:
856 * 'XN' is the eXecute Never bit
857 * 'G' is the notGlobal (process-specific) bit
858 * 'S' is the shared bit
859 * 'A' in the access permission extension (ATX) bit
860 * 'TEX' remap register control bits
861 * 'AP' is the access protection
862 * 'dom' is the domain for the translation
863 * 'C' is the cache attribute
864 * 'B' is the write buffer attribute
865 */
866
867 #define PTE_SHIFT 2 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */
868 #define PTE_PGENTRIES (1024 >> PTE_SHIFT) /* number of ptes per page */
869
870 #define ARM_PTE_EMPTY 0x00000000 /* unasigned - invalid entry */
871
872 /* markers for (invalid) PTE for a page sent to compressor */
873 #define ARM_PTE_COMPRESSED ARM_PTE_TEX1 /* compressed... */
874 #define ARM_PTE_COMPRESSED_ALT ARM_PTE_TEX2 /* ... and was "alt_acct" */
875 #define ARM_PTE_COMPRESSED_MASK (ARM_PTE_COMPRESSED | ARM_PTE_COMPRESSED_ALT)
876 #define ARM_PTE_IS_COMPRESSED(x) \
877 ((((x) & 0x3) == 0) && /* PTE is not valid... */ \
878 ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \
879 ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \
880 (panic("compressed PTE %p 0x%x has extra bits 0x%x: corrupted?", \
881 &(x), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE)))
882
883 #define ARM_PTE_TYPE_FAULT 0x00000000 /* fault entry type */
884 #define ARM_PTE_TYPE 0x00000002 /* small page entry type */
885 #define ARM_PTE_TYPE_MASK 0x00000002 /* mask to get pte type */
886
887 #define ARM_PTE_NG_MASK 0x00000800 /* mask to determine notGlobal bit */
888 #define ARM_PTE_NG 0x00000800 /* value for a per-process mapping */
889
890 #define ARM_PTE_SHSHIFT 10
891 #define ARM_PTE_SH_MASK 0x00000400 /* shared (SMP) mapping mask */
892 #define ARM_PTE_SH 0x00000400 /* shared (SMP) mapping */
893
894 #define ARM_PTE_CBSHIFT 2
895 #define ARM_PTE_CB(x) ((x)<<ARM_PTE_CBSHIFT)
896 #define ARM_PTE_CB_MASK (0x3<<ARM_PTE_CBSHIFT)
897
898 #define ARM_PTE_AP0SHIFT 4
899 #define ARM_PTE_AP0 (1<<ARM_PTE_AP0SHIFT)
900 #define ARM_PTE_AP0_MASK (1<<ARM_PTE_AP0SHIFT)
901
902 #define ARM_PTE_AP1SHIFT 5
903 #define ARM_PTE_AP1 (1<<ARM_PTE_AP1SHIFT)
904 #define ARM_PTE_AP1_MASK (1<<ARM_PTE_AP1SHIFT)
905
906 #define ARM_PTE_AP2SHIFT 9
907 #define ARM_PTE_AP2 (1<<ARM_PTE_AP2SHIFT)
908 #define ARM_PTE_AP2_MASK (1<<ARM_PTE_AP2SHIFT)
909
910 /* access protections */
911 #define ARM_PTE_AP(ap) ((((ap)&0x1)<<ARM_PTE_AP1SHIFT) \
912 | ((((ap)>>1)&0x1)<<ARM_PTE_AP2SHIFT))
913
914 /* mask access protections */
915 #define ARM_PTE_APMASK (ARM_PTE_AP1_MASK \
916 | ARM_PTE_AP2_MASK)
917
918 #define ARM_PTE_AF ARM_PTE_AP0 /* value for access */
919 #define ARM_PTE_AFMASK ARM_PTE_AP0_MASK /* access mask */
920
921 #define ARM_PTE_PAGE_MASK 0xFFFFF000 /* mask for a small page */
922 #define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */
923
924 #define ARM_PTE_NXSHIFT 0
925 #define ARM_PTE_NX 0x00000001 /* small page no execute */
926 #define ARM_PTE_NX_MASK (1<<ARM_PTE_NXSHIFT)
927
928 #define ARM_PTE_PNXSHIFT 0
929 #define ARM_PTE_PNX 0x00000000 /* no privilege execute. not impl */
930 #define ARM_PTE_PNX_MASK (0<<ARM_PTE_NXSHIFT)
931
932 #define ARM_PTE_TEX0SHIFT 6
933 #define ARM_PTE_TEX0 (1<<ARM_PTE_TEX0SHIFT)
934 #define ARM_PTE_TEX0_MASK (1<<ARM_PTE_TEX0SHIFT)
935
936 #define ARM_PTE_TEX1SHIFT 7
937 #define ARM_PTE_TEX1 (1<<ARM_PTE_TEX1SHIFT)
938 #define ARM_PTE_TEX1_MASK (1<<ARM_PTE_TEX1SHIFT)
939
940 #define ARM_PTE_WRITEABLESHIFT ARM_PTE_TEX1SHIFT
941 #define ARM_PTE_WRITEABLE ARM_PTE_TEX1
942 #define ARM_PTE_WRITEABLE_MASK ARM_PTE_TEX1_MASK
943
944 #define ARM_PTE_TEX2SHIFT 8
945 #define ARM_PTE_TEX2 (1<<ARM_PTE_TEX2SHIFT)
946 #define ARM_PTE_TEX2_MASK (1<<ARM_PTE_TEX2SHIFT)
947
948 #define ARM_PTE_WIREDSHIFT ARM_PTE_TEX2SHIFT
949 #define ARM_PTE_WIRED ARM_PTE_TEX2
950 #define ARM_PTE_WIRED_MASK ARM_PTE_TEX2_MASK
951
952 /* mask memory attributes index */
953 #define ARM_PTE_ATTRINDX(indx) ((((indx)&0x3)<<ARM_PTE_CBSHIFT) \
954 | ((((indx)>>2)&0x1)<<ARM_PTE_TEX0SHIFT))
955
956 /* mask memory attributes index */
957 #define ARM_PTE_ATTRINDXMASK (ARM_PTE_CB_MASK \
958 | ARM_PTE_TEX0_MASK)
959
960 #define ARM_SMALL_PAGE_SIZE (4096) /* 4KB */
961 #define ARM_LARGE_PAGE_SIZE (64*1024) /* 64KB */
962 #define ARM_SECTION_SIZE (1024*1024) /* 1MB */
963 #define ARM_SUPERSECTION_SIZE (16*1024*1024) /* 16MB */
964
965 #endif
966
967 /*
968 * Format of the Debug Status and Control Register (DBGDSCR)
969 */
970 #define ARM_DBGDSCR_RXFULL (1 << 30)
971 #define ARM_DBGDSCR_TXFULL (1 << 29)
972 #define ARM_DBGDSCR_RXFULL_1 (1 << 27)
973 #define ARM_DBGDSCR_TXFULL_1 (1 << 26)
974 #define ARM_DBGDSCR_PIPEADV (1 << 25)
975 #define ARM_DBGDSCR_INSTRCOMPL_1 (1 << 24)
976 #define ARM_DBGDSCR_EXTDCCMODE_MASK (3 << 20)
977 #define ARM_DBGDSCR_EXTDCCMODE_NONBLOCKING (0 << 20)
978 #define ARM_DBGDSCR_EXTDCCMODE_STALL (1 << 20)
979 #define ARM_DBGDSCR_EXTDCCMODE_FAST (1 << 20)
980 #define ARM_DBGDSCR_ADADISCARD (1 << 19)
981 #define ARM_DBGDSCR_NS (1 << 18)
982 #define ARM_DBGDSCR_SPNIDDIS (1 << 17)
983 #define ARM_DBGDSCR_SPIDDIS (1 << 16)
984 #define ARM_DBGDSCR_MDBGEN (1 << 15)
985 #define ARM_DBGDSCR_HDBGEN (1 << 14)
986 #define ARM_DBGDSCR_ITREN (1 << 13)
987 #define ARM_DBGDSCR_UDCCDIS (1 << 12)
988 #define ARM_DBGDSCR_INTDIS (1 << 11)
989 #define ARM_DBGDSCR_DBGACK (1 << 10)
990 #define ARM_DBGDSCR_DBGNOPWRDWN (1 << 9)
991 #define ARM_DBGDSCR_UND_1 (1 << 8)
992 #define ARM_DBGDSCR_ADABORT_1 (1 << 7)
993 #define ARM_DBGDSCR_SDABORT_1 (1 << 6)
994 #define ARM_DBGDSCR_MOE_MASK (15 << 2)
995 #define ARM_DBGDSCR_MOE_HALT_REQUEST (0 << 2)
996 #define ARM_DBGDSCR_MOE_BREAKPOINT (1 << 2)
997 #define ARM_DBGDSCR_MOE_ASYNC_WATCHPOINT (2 << 2)
998 #define ARM_DBGDSCR_MOE_BKPT_INSTRUCTION (3 << 2)
999 #define ARM_DBGDSCR_MOE_EXT_DEBUG_REQ (4 << 2)
1000 #define ARM_DBGDSCR_MOE_VECTOR_CATCH (5 << 2)
1001 #define ARM_DBGDSCR_MOE_DSIDE_ABORT (6 << 2)
1002 #define ARM_DBGDSCR_MOE_ISIDE_ABORT (7 << 2)
1003 #define ARM_DBGDSCR_MOE_OS_UNLOCK_CATCH (8 << 2)
1004 #define ARM_DBGDSCR_MOE_SYNC_WATCHPOINT (10 << 2)
1005
1006 #define ARM_DBGDSCR_RESTARTED (1 << 1)
1007 #define ARM_DBGDSCR_HALTED (1 << 0)
1008
1009 /*
1010 * Format of the Debug & Watchpoint Breakpoint Value and Control Registers
1011 * Using ARMv7 names; ARMv6 and ARMv6.1 are bit-compatible
1012 */
1013 #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */
1014 #define ARM_DBGBVR_CONTEXTID_MASK 0xFFFFFFFF /* BVR only */
1015
1016 #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */
1017 #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */
1018 #define ARM_DBGBCR_MATCH_MATCH (0 << 22)
1019 #define ARM_DBGBCR_MATCH_MISMATCH (1 << 22)
1020 #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */
1021 #define ARM_DBGBCR_TYPE_IVA (0 << 21)
1022 #define ARM_DBGBCR_TYPE_CONTEXTID (1 << 21)
1023 #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */
1024 #define ARM_DBG_CR_LINKED_LINKED (1 << 20)
1025 #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20)
1026 #define ARM_DBG_CR_LINKED_BRP_MASK 0x000F0000 /* BCR & WCR */
1027 #define ARM_DBG_CR_SECURITY_STATE_MASK (3 << 14) /* BCR & WCR */
1028 #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14)
1029 #define ARM_DBG_CR_SECURITY_STATE_NONSECURE (1 << 14)
1030 #define ARM_DBG_CR_SECURITY_STATE_SECURE (2 << 14)
1031 #define ARM_DBG_CR_HIGHER_MODE_MASK (1 << 13) /* BCR & WCR */
1032 #define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13)
1033 #define ARM_DBG_CR_HIGHER_MODE_DISABLE (0 << 13)
1034 #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */
1035 #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */
1036 #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */
1037 #define ARM_DBCWCR_ACCESS_CONTROL_LOAD (1 << 3)
1038 #define ARM_DBCWCR_ACCESS_CONTROL_STORE (2 << 3)
1039 #define ARM_DBCWCR_ACCESS_CONTROL_ANY (3 << 3)
1040 #define ARM_DBG_CR_MODE_CONTROL_MASK (3 << 1) /* BCR & WCR */
1041 #define ARM_DBG_CR_MODE_CONTROL_U_S_S (0 << 1) /* BCR only */
1042 #define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */
1043 #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */
1044 #define ARM_DBG_CR_MODE_CONTROL_ANY (3 << 1) /* BCR & WCR */
1045 #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */
1046 #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0)
1047 #define ARM_DBG_CR_ENABLE_DISABLE (0 << 0)
1048
1049 /*
1050 * Format of the Device Power-down and Reset Status Register (DBGPRSR)
1051 */
1052 #define ARM_DBGPRSR_STICKY_RESET_STATUS (1 << 3)
1053 #define ARM_DBGPRSR_RESET_STATUS (1 << 2)
1054 #define ARM_DBGPRSR_STICKY_POWERDOWN_STATUS (1 << 1)
1055 #define ARM_DBGPRSR_POWERUP_STATUS (1 << 0)
1056
1057 /*
1058 * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR)
1059 */
1060 #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55
1061
1062 /* ARMv7 Debug register map */
1063 #define ARM_DEBUG_OFFSET_DBGDIDR (0x000)
1064 #define ARM_DEBUG_OFFSET_DBGWFAR (0x018)
1065 #define ARM_DEBUG_OFFSET_DBGVCR (0x01C)
1066 #define ARM_DEBUG_OFFSET_DBGECR (0x024)
1067 #define ARM_DEBUG_OFFSET_DBGDSCCR (0x028)
1068 #define ARM_DEBUG_OFFSET_DBGDSMCR (0x02C)
1069 #define ARM_DEBUG_OFFSET_DBGDTRRX (0x080)
1070 #define ARM_DEBUG_OFFSET_DBGITR (0x084) /* Write-only */
1071 #define ARM_DEBUG_OFFSET_DBGPCSR (0x084) /* Read-only */
1072 #define ARM_DEBUG_OFFSET_DBGDSCR (0x088)
1073 #define ARM_DEBUG_OFFSET_DBGDTRTX (0x08C)
1074 #define ARM_DEBUG_OFFSET_DBGDRCR (0x090)
1075 #define ARM_DEBUG_OFFSET_DBGBVR (0x100) /* 0x100 - 0x13C */
1076 #define ARM_DEBUG_OFFSET_DBGBCR (0x140) /* 0x140 - 0x17C */
1077 #define ARM_DEBUG_OFFSET_DBGWVR (0x180) /* 0x180 - 0x1BC */
1078 #define ARM_DEBUG_OFFSET_DBGWCR (0x1C0) /* 0x1C0 - 0x1FC */
1079 #define ARM_DEBUG_OFFSET_DBGOSLAR (0x300)
1080 #define ARM_DEBUG_OFFSET_DBGOSLSR (0x304)
1081 #define ARM_DEBUG_OFFSET_DBGOSSRR (0x308)
1082 #define ARM_DEBUG_OFFSET_DBGPRCR (0x310)
1083 #define ARM_DEBUG_OFFSET_DBGPRSR (0x314)
1084 #define ARM_DEBUG_OFFSET_DBGITCTRL (0xF00)
1085 #define ARM_DEBUG_OFFSET_DBGCLAIMSET (0xFA0)
1086 #define ARM_DEBUG_OFFSET_DBGCLAIMCLR (0xFA4)
1087 #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0)
1088 #define ARM_DEBUG_OFFSET_DBGLSR (0xFB4)
1089 #define ARM_DEBUG_OFFSET_DBGAUTHSTATUS (0xFB8)
1090 #define ARM_DEBUG_OFFSET_DBGDEVID (0xFC8)
1091 #define ARM_DEBUG_OFFSET_DBGDEVTYPE (0xFCC)
1092 #define ARM_DEBUG_OFFSET_DBGPID0 (0xFD0)
1093 #define ARM_DEBUG_OFFSET_DBGPID1 (0xFD4)
1094 #define ARM_DEBUG_OFFSET_DBGPID2 (0xFD8)
1095 #define ARM_DEBUG_OFFSET_DBGPID3 (0xFDA)
1096 #define ARM_DEBUG_OFFSET_DBGPID4 (0xFDC)
1097 #define ARM_DEBUG_OFFSET_DBGCID0 (0xFF0)
1098 #define ARM_DEBUG_OFFSET_DBGCID1 (0xFF4)
1099 #define ARM_DEBUG_OFFSET_DBGCID2 (0xFF8)
1100 #define ARM_DEBUG_OFFSET_DBGCID3 (0xFFA)
1101 #define ARM_DEBUG_OFFSET_DBGCID4 (0xFFC)
1102
1103 /*
1104 * Media and VFP Feature Register 1 (MVFR1)
1105 */
1106 #define MVFR_ASIMD_HPFP 0x00100000UL
1107
1108 #endif /* _ARM_PROC_REG_H_ */
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