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1 /*
2 * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the License
10 * may not be used to create, or enable the creation or redistribution of,
11 * unlawful or unlicensed copies of an Apple operating system, or to
12 * circumvent, violate, or enable the circumvention or violation of, any
13 * terms of an Apple operating system software license agreement.
14 *
15 * Please obtain a copy of the License at
16 * http://www.opensource.apple.com/apsl/ and read it before using this file.
17 *
18 * The Original Code and all software distributed under the License are
19 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
20 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
21 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
23 * Please see the License for the specific language governing rights and
24 * limitations under the License.
25 *
26 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
27 */
28
29 /*
30 * file: pe_serial.c
31 * Polled-mode 16x50 UART driver.
32 */
33
34 #include <pexpert/protos.h>
35 #include <pexpert/pexpert.h>
36
37 /* standard port addresses */
38 enum {
39 COM1_PORT_ADDR = 0x3f8,
40 COM2_PORT_ADDR = 0x2f8
41 };
42
43 /* UART register offsets */
44 enum {
45 UART_RBR = 0, /* receive buffer Register (R) */
46 UART_THR = 0, /* transmit holding register (W) */
47 UART_DLL = 0, /* DLAB = 1, divisor latch (LSB) */
48 UART_IER = 1, /* interrupt enable register */
49 UART_DLM = 1, /* DLAB = 1, divisor latch (MSB) */
50 UART_IIR = 2, /* interrupt ident register (R) */
51 UART_FCR = 2, /* fifo control register (W) */
52 UART_LCR = 3, /* line control register */
53 UART_MCR = 4, /* modem control register */
54 UART_LSR = 5, /* line status register */
55 UART_MSR = 6 /* modem status register */
56 };
57
58 enum {
59 UART_LCR_8BITS = 0x03,
60 UART_LCR_DLAB = 0x80
61 };
62
63 enum {
64 UART_MCR_DTR = 0x01,
65 UART_MCR_RTS = 0x02,
66 UART_MCR_OUT1 = 0x04,
67 UART_MCR_OUT2 = 0x08,
68 UART_MCR_LOOP = 0x10
69 };
70
71 enum {
72 UART_LSR_DR = 0x01,
73 UART_LSR_OE = 0x02,
74 UART_LSR_PE = 0x04,
75 UART_LSR_FE = 0x08,
76 UART_LSR_THRE = 0x20
77 };
78
79 static unsigned uart_baud_rate = 115200;
80 #define UART_PORT_ADDR COM1_PORT_ADDR
81
82 #define UART_CLOCK 1843200 /* 1.8432 MHz clock */
83
84 #define WRITE(r, v) outb(UART_PORT_ADDR + UART_##r, v)
85 #define READ(r) inb(UART_PORT_ADDR + UART_##r)
86 #define DELAY(x) { volatile int _d_; for (_d_ = 0; _d_ < (10000*x); _d_++) ; }
87
88 static int uart_initted = 0; /* 1 if init'ed */
89
90 static int
91 uart_probe( void )
92 {
93 /* Verify that the Divisor Register is accessible */
94
95 WRITE( LCR, UART_LCR_DLAB );
96 WRITE( DLL, 0x5a );
97 if (READ(DLL) != 0x5a) return 0;
98 WRITE( DLL, 0xa5 );
99 if (READ(DLL) != 0xa5) return 0;
100 WRITE( LCR, 0x00 );
101 return 1;
102 }
103
104 static void
105 uart_set_baud_rate( unsigned long baud_rate )
106 {
107 const unsigned char lcr = READ( LCR );
108 unsigned long div;
109
110 if (baud_rate == 0) baud_rate = 9600;
111 div = UART_CLOCK / 16 / baud_rate;
112 WRITE( LCR, lcr | UART_LCR_DLAB );
113 WRITE( DLM, (unsigned char)(div >> 8) );
114 WRITE( DLL, (unsigned char) div );
115 WRITE( LCR, lcr & ~UART_LCR_DLAB);
116 }
117
118 static void
119 uart_putc( char c )
120 {
121 if (!uart_initted) return;
122
123 /* Wait for THR empty */
124 while ( !(READ(LSR) & UART_LSR_THRE) ) DELAY(1);
125
126 WRITE( THR, c );
127 }
128
129 static int
130 uart_getc( void )
131 {
132 /*
133 * This function returns:
134 * -1 : no data
135 * -2 : receiver error
136 * >0 : character received
137 */
138
139 unsigned char lsr;
140
141 if (!uart_initted) return -1;
142
143 lsr = READ( LSR );
144
145 if ( lsr & (UART_LSR_FE | UART_LSR_PE | UART_LSR_OE) )
146 {
147 READ( RBR ); /* discard */
148 return -2;
149 }
150
151 if ( lsr & UART_LSR_DR )
152 {
153 return READ( RBR );
154 }
155
156 return -1;
157 }
158
159 int serial_init( void )
160 {
161 unsigned serial_baud_rate = 0;
162
163 if ( /*uart_initted ||*/ uart_probe() == 0 ) return 0;
164
165 /* Disable hardware interrupts */
166
167 WRITE( MCR, 0 );
168 WRITE( IER, 0 );
169
170 /* Disable FIFO's for 16550 devices */
171
172 WRITE( FCR, 0 );
173
174 /* Set for 8-bit, no parity, DLAB bit cleared */
175
176 WRITE( LCR, UART_LCR_8BITS );
177
178 /* Set baud rate - use the supplied boot-arg if available */
179
180 if (PE_parse_boot_arg("serialbaud", &serial_baud_rate))
181 {
182 /* Valid divisor? */
183 if (!((UART_CLOCK / 16) % serial_baud_rate)) {
184 uart_baud_rate = serial_baud_rate;
185 }
186 }
187 uart_set_baud_rate( uart_baud_rate );
188
189 /* Assert DTR# and RTS# lines (OUT2?) */
190
191 WRITE( MCR, UART_MCR_DTR | UART_MCR_RTS );
192
193 /* Clear any garbage in the input buffer */
194
195 READ( RBR );
196
197 uart_initted = 1;
198
199 return 1;
200 }
201
202 void serial_putc( char c )
203 {
204 uart_putc(c);
205 if (c == '\n') uart_putc('\r');
206 }
207
208 int serial_getc( void )
209 {
210 return uart_getc();
211 }