pexpert/pexpert/arm64/H13.h

   1 /*
   2  * Copyright (c) 2019 Apple Inc. All rights reserved.
   3  *
   4  * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License. The rights granted to you under the License
  10  * may not be used to create, or enable the creation or redistribution of,
  11  * unlawful or unlicensed copies of an Apple operating system, or to
  12  * circumvent, violate, or enable the circumvention or violation of, any
  13  * terms of an Apple operating system software license agreement.
  14  *
  15  * Please obtain a copy of the License at
  16  * http://www.opensource.apple.com/apsl/ and read it before using this file.
  17  *
  18  * The Original Code and all software distributed under the License are
  19  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  20  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  21  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  23  * Please see the License for the specific language governing rights and
  24  * limitations under the License.
  25  *
  26  * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
  27  */
  28
  29 #ifndef _PEXPERT_ARM64_H13_H
  30 #define _PEXPERT_ARM64_H13_H
  31
  32 #define APPLEFIRESTORM
  33 #define NO_MONITOR              1 /* No EL3 for this CPU -- ever */
  34 #define HAS_CTRR                1 /* Has CTRR registers */
  35 #define HAS_NEX_PG              1 /* Supports p-Core NEX powergating during Neon inactivity */
  36 #define HAS_BP_RET              1 /* Supports branch predictor state retention across ACC sleep */
  37 #define HAS_CONTINUOUS_HWCLOCK  1 /* Has a hardware clock that ticks during sleep */
  38 #define HAS_IPI                 1 /* Has IPI registers */
  39 #define HAS_CLUSTER             1 /* Has eCores and pCores in separate clusters */
  40 #define HAS_RETENTION_STATE     1 /* Supports architectural state retention */
  41 #define HAS_VMSA_LOCK           1 /* Supports lockable MMU config registers */
  42 #define HAS_DPC_ERR             1 /* Has an error register for DPC */
  43 #define HAS_UCNORMAL_MEM        1 /* Supports completely un-cacheable normal memory type */
  44 #define HAS_SPR_LOCK            1 /* Supports lockable special-purpose registers */
  45 #define HAS_TWO_STAGE_SPR_LOCK  1 /* SPR locks are split into RO_CTL and LOCK registers */
  46 #define HAS_FAST_CNTVCT         1
  47 #define HAS_E0PD                1 /* Supports E0PD0 and E0PD1 in TCR for Meltdown mitigation (ARMv8.5)*/
  48 #define HAS_ICACHE_FUSION_BUG   1 /* HW bug that causes incorrect reporting of instruction aborts on fused instructions */
  49
  50 #define CPU_HAS_APPLE_PAC                    1
  51 #define HAS_UNCORE_CTRS                      1
  52 #define UNCORE_VERSION                       2
  53 #define UNCORE_PER_CLUSTER                   1
  54 #define UNCORE_NCTRS                         16
  55 #define CORE_NCTRS                           10
  56
  57 #define __ARM_AMP__                          1
  58 #define __ARM_16K_PG__                       1
  59 #define __ARM_GLOBAL_SLEEP_BIT__             1
  60 #define __ARM_PAN_AVAILABLE__                1
  61 #define __ARM_WKDM_ISA_AVAILABLE__           1
  62 #define __ARM_WKDM_POPCNT__                  1
  63 #define __ARM_WKDM_POPCNT_COMPRESSED_DATA__  0
  64 #define __ARM_SB_AVAILABLE__                 1
  65 #define __PLATFORM_WKDM_ALIGNMENT_MASK__     (0x3FULL)
  66 #define __PLATFORM_WKDM_ALIGNMENT_BOUNDARY__ (64)
  67
  68 /* Optional CPU features -- an SoC may #undef these */
  69 #define ARM_PARAMETERIZED_PMAP               1
  70 #define __ARM_MIXED_PAGE_SIZE__              1
  71 #define HAS_APCTL_EL1_USERKEYEN              1 /* Supports use of KernKey in EL0 */
  72
  73 /*
  74  * APSTS_SUPPORTED: Pointer authentication status registers, MKEYVld flag moved here from APCTL on APPLELIGHTNING (H12)
  75  */
  76 #define __APSTS_SUPPORTED__                  1
  77 #define __ARM_RANGE_TLBI__                   1
  78 #define __ARM_E2H__                          1
  79
  80 #include <pexpert/arm64/apple_arm64_common.h>
  81
  82 #endif /* !_PEXPERT_ARM64_H13_H */