2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
4 * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. The rights granted to you under the
10 * License may not be used to create, or enable the creation or
11 * redistribution of, unlawful or unlicensed copies of an Apple operating
12 * system, or to circumvent, violate, or enable the circumvention or
13 * violation of, any terms of an Apple operating system software license
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17 * http://www.opensource.apple.com/apsl/ and read it before using this
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22 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
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34 #include <pexpert/pexpert.h>
38 #define min(a,b) ((a) < (b) ? (a) : (b))
41 * CPU identification routines.
43 * Note that this code assumes a processor that supports the
44 * 'cpuid' instruction.
47 static unsigned int cpuid_maxcpuid
;
49 static i386_cpu_info_t cpuid_cpu_info
;
51 uint32_t cpuid_feature
; /* XXX obsolescent for compat */
54 * We only identify Intel CPUs here. Adding support
55 * for others would be straightforward.
57 static void set_cpu_generic(i386_cpu_info_t
*);
58 static void set_cpu_intel(i386_cpu_info_t
*);
59 static void set_cpu_amd(i386_cpu_info_t
*);
60 static void set_cpu_nsc(i386_cpu_info_t
*);
61 static void set_cpu_unknown(i386_cpu_info_t
*);
65 void (* func
)(i386_cpu_info_t
*);
67 {CPUID_VID_INTEL
, set_cpu_intel
},
68 {CPUID_VID_AMD
, set_cpu_amd
},
69 {CPUID_VID_NSC
, set_cpu_nsc
},
74 cpuid_get_info(i386_cpu_info_t
*info_p
)
76 uint32_t cpuid_result
[4];
79 bzero((void *)info_p
, sizeof(i386_cpu_info_t
));
81 /* do cpuid 0 to get vendor */
82 do_cpuid(0, cpuid_result
);
83 cpuid_maxcpuid
= cpuid_result
[0];
84 bcopy((char *)&cpuid_result
[1], &info_p
->cpuid_vendor
[0], 4); /* ugh */
85 bcopy((char *)&cpuid_result
[2], &info_p
->cpuid_vendor
[8], 4);
86 bcopy((char *)&cpuid_result
[3], &info_p
->cpuid_vendor
[4], 4);
87 info_p
->cpuid_vendor
[12] = 0;
91 if ((cpu_vendors
[i
].vendor
== 0) ||
92 (!strcmp(cpu_vendors
[i
].vendor
, info_p
->cpuid_vendor
))) {
93 cpu_vendors
[i
].func(info_p
);
100 * Cache descriptor table. Each row has the form:
101 * (descriptor_value, cache, size, linesize,
103 * Note: the CACHE_DESC macro does not expand description text in the kernel.
105 static cpuid_cache_desc_t cpuid_cache_desc_tab
[] = {
106 CACHE_DESC(CPUID_CACHE_ITLB_4K
, Lnone
, 0, 0, \
107 "Instruction TLB, 4K, pages 4-way set associative, 64 entries"),
108 CACHE_DESC(CPUID_CACHE_ITLB_4M
, Lnone
, 0, 0, \
109 "Instruction TLB, 4M, pages 4-way set associative, 2 entries"),
110 CACHE_DESC(CPUID_CACHE_DTLB_4K
, Lnone
, 0, 0, \
111 "Data TLB, 4K pages, 4-way set associative, 64 entries"),
112 CACHE_DESC(CPUID_CACHE_DTLB_4M
, Lnone
, 0, 0, \
113 "Data TLB, 4M pages, 4-way set associative, 8 entries"),
114 CACHE_DESC(CPUID_CACHE_ITLB_64
, Lnone
, 0, 0, \
115 "Instruction TLB, 4K and 2M or 4M pages, 64 entries"),
116 CACHE_DESC(CPUID_CACHE_ITLB_128
, Lnone
, 0, 0, \
117 "Instruction TLB, 4K and 2M or 4M pages, 128 entries"),
118 CACHE_DESC(CPUID_CACHE_ITLB_256
, Lnone
, 0, 0, \
119 "Instruction TLB, 4K and 2M or 4M pages, 256 entries"),
120 CACHE_DESC(CPUID_CACHE_DTLB_64
, Lnone
, 0, 0, \
121 "Data TLB, 4K and 4M pages, 64 entries"),
122 CACHE_DESC(CPUID_CACHE_DTLB_128
, Lnone
, 0, 0, \
123 "Data TLB, 4K and 4M pages, 128 entries"),
124 CACHE_DESC(CPUID_CACHE_DTLB_256
, Lnone
, 0, 0, \
125 "Data TLB, 4K and 4M pages, 256 entries"),
126 CACHE_DESC(CPUID_CACHE_ITLB_128_4
, Lnone
, 0, 0, \
127 "Instruction TLB, 4K pages, 4-way set associative, 128 entries"),
128 CACHE_DESC(CPUID_CACHE_DTLB_128_4
, Lnone
, 0, 0, \
129 "Data TLB, 4K pages, 4-way set associative, 128 entries"),
130 CACHE_DESC(CPUID_CACHE_ICACHE_8K
, L1I
, 8*1024, 32, \
131 "Instruction L1 cache, 8K, 4-way set associative, 32byte line size"),
132 CACHE_DESC(CPUID_CACHE_DCACHE_8K
, L1D
, 8*1024, 32, \
133 "Data L1 cache, 8K, 2-way set associative, 32byte line size"),
134 CACHE_DESC(CPUID_CACHE_ICACHE_16K
, L1I
, 16*1024, 32, \
135 "Instruction L1 cache, 16K, 4-way set associative, 32byte line size"),
136 CACHE_DESC(CPUID_CACHE_DCACHE_16K
, L1D
, 16*1024, 32, \
137 "Data L1 cache, 16K, 4-way set associative, 32byte line size"),
138 CACHE_DESC(CPUID_CACHE_DCACHE_8K_64
, L1D
, 8*1024, 64, \
139 "Data L1 cache, 8K, 4-way set associative, 64byte line size"),
140 CACHE_DESC(CPUID_CACHE_DCACHE_16K_64
, L1D
, 16*1024, 64, \
141 "Data L1 cache, 16K, 4-way set associative, 64byte line size"),
142 CACHE_DESC(CPUID_CACHE_DCACHE_32K_64
, L1D
, 32*1024, 64, \
143 "Data L1 cache, 32K, 4-way set associative, 64byte line size"),
144 CACHE_DESC(CPUID_CACHE_DCACHE_32K
, L1D
, 32*1024, 64, \
145 "Data L1 cache, 32K, 8-way set assocative, 64byte line size"),
146 CACHE_DESC(CPUID_CACHE_ICACHE_32K
, L1I
, 32*1024, 64, \
147 "Instruction L1 cache, 32K, 8-way set associative, 64byte line size"),
148 CACHE_DESC(CPUID_CACHE_DCACHE_16K_8
, L1D
, 16*1024, 64, \
149 "Data L1 cache, 16K, 8-way set associative, 64byte line size"),
150 CACHE_DESC(CPUID_CACHE_TRACE_12K
, L1I
, 12*1024, 64, \
151 "Trace cache, 12K-uop, 8-way set associative"),
152 CACHE_DESC(CPUID_CACHE_TRACE_16K
, L1I
, 16*1024, 64, \
153 "Trace cache, 16K-uop, 8-way set associative"),
154 CACHE_DESC(CPUID_CACHE_TRACE_32K
, L1I
, 32*1024, 64, \
155 "Trace cache, 32K-uop, 8-way set associative"),
156 CACHE_DESC(CPUID_CACHE_UCACHE_128K
, L2U
, 128*1024, 32, \
157 "Unified L2 cache, 128K, 4-way set associative, 32byte line size"),
158 CACHE_DESC(CPUID_CACHE_UCACHE_256K
, L2U
, 128*1024, 32, \
159 "Unified L2 cache, 256K, 4-way set associative, 32byte line size"),
160 CACHE_DESC(CPUID_CACHE_UCACHE_512K
, L2U
, 512*1024, 32, \
161 "Unified L2 cache, 512K, 4-way set associative, 32byte line size"),
162 CACHE_DESC(CPUID_CACHE_UCACHE_1M
, L2U
, 1*1024*1024, 32, \
163 "Unified L2 cache, 1M, 4-way set associative, 32byte line size"),
164 CACHE_DESC(CPUID_CACHE_UCACHE_2M
, L2U
, 2*1024*1024, 32, \
165 "Unified L2 cache, 2M, 4-way set associative, 32byte line size"),
166 CACHE_DESC(CPUID_CACHE_UCACHE_128K_64
, L2U
, 128*1024, 64, \
167 "Unified L2 cache, 128K, 8-way set associative, 64byte line size"),
168 CACHE_DESC(CPUID_CACHE_UCACHE_256K_64
, L2U
, 256*1024, 64, \
169 "Unified L2 cache, 256K, 8-way set associative, 64byte line size"),
170 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64
, L2U
, 512*1024, 64, \
171 "Unified L2 cache, 512K, 8-way set associative, 64byte line size"),
172 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64
, L2U
, 1*1024*1024, 64, \
173 "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
174 CACHE_DESC(CPUID_CACHE_UCACHE_256K_32
, L2U
, 256*1024, 32, \
175 "Unified L2 cache, 256K, 8-way set associative, 32byte line size"),
176 CACHE_DESC(CPUID_CACHE_UCACHE_512K_32
, L2U
, 512*1024, 32, \
177 "Unified L2 cache, 512K, 8-way set associative, 32byte line size"),
178 CACHE_DESC(CPUID_CACHE_UCACHE_1M_32
, L2U
, 1*1024*1024, 32, \
179 "Unified L2 cache, 1M, 8-way set associative, 32byte line size"),
180 CACHE_DESC(CPUID_CACHE_UCACHE_2M_32
, L2U
, 2*1024*1024, 32, \
181 "Unified L2 cache, 2M, 8-way set associative, 32byte line size"),
182 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_4
, L2U
, 1*1024*1024, 64, \
183 "Unified L2 cache, 1M, 4-way set associative, 64byte line size"),
184 CACHE_DESC(CPUID_CACHE_UCACHE_2M_64
, L2U
, 2*1024*1024, 64, \
185 "Unified L2 cache, 2M, 8-way set associative, 64byte line size"),
186 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_2
,L2U
, 512*1024, 64, \
187 "Unified L2 cache, 512K, 2-way set associative, 64byte line size"),
188 CACHE_DESC(CPUID_CACHE_UCACHE_512K_64_4
,L2U
, 512*1024, 64, \
189 "Unified L2 cache, 512K, 4-way set associative, 64byte line size"),
190 CACHE_DESC(CPUID_CACHE_UCACHE_1M_64_8
, L2U
, 1*1024*1024, 64, \
191 "Unified L2 cache, 1M, 8-way set associative, 64byte line size"),
192 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S4
, L2U
, 128*1024, 64, \
193 "Unified L2 sectored cache, 128K, 4-way set associative, 64byte line size"),
194 CACHE_DESC(CPUID_CACHE_UCACHE_128K_S2
, L2U
, 128*1024, 64, \
195 "Unified L2 sectored cache, 128K, 2-way set associative, 64byte line size"),
196 CACHE_DESC(CPUID_CACHE_UCACHE_256K_S4
, L2U
, 256*1024, 64, \
197 "Unified L2 sectored cache, 256K, 4-way set associative, 64byte line size"),
198 CACHE_DESC(CPUID_CACHE_L3CACHE_512K
, L3U
, 512*1024, 64, \
199 "Unified L3 cache, 512K, 4-way set associative, 64byte line size"),
200 CACHE_DESC(CPUID_CACHE_L3CACHE_1M
, L3U
, 1*1024*1024, 64, \
201 "Unified L3 cache, 1M, 8-way set associative, 64byte line size"),
202 CACHE_DESC(CPUID_CACHE_L3CACHE_2M
, L3U
, 2*1024*1024, 64, \
203 "Unified L3 cache, 2M, 8-way set associative, 64byte line size"),
204 CACHE_DESC(CPUID_CACHE_L3CACHE_4M
, L3U
, 4*1024*1024, 64, \
205 "Unified L3 cache, 4M, 8-way set associative, 64byte line size"),
206 CACHE_DESC(CPUID_CACHE_PREFETCH_64
, Lnone
, 0, 0, \
207 "64-Byte Prefetching"),
208 CACHE_DESC(CPUID_CACHE_PREFETCH_128
, Lnone
, 0, 0, \
209 "128-Byte Prefetching"),
210 CACHE_DESC(CPUID_CACHE_NOCACHE
, Lnone
, 0, 0, \
211 "No L2 cache or, if valid L2 cache, no L3 cache"),
212 CACHE_DESC(CPUID_CACHE_NULL
, Lnone
, 0, 0, \
216 static const char * get_intel_model_string( i386_cpu_info_t
* info_p
)
218 /* check for brand id */
219 switch(info_p
->cpuid_brand
) {
220 case CPUID_BRAND_UNSUPPORTED
:
221 /* brand ID not supported; use alternate method. */
222 switch(info_p
->cpuid_family
) {
223 case CPUID_FAMILY_486
:
225 case CPUID_FAMILY_586
:
226 return "Intel Pentium";
227 case CPUID_FAMILY_686
:
228 switch(info_p
->cpuid_model
) {
230 return "Intel Pentium Pro";
231 case CPUID_MODEL_PII
:
232 return "Intel Pentium II";
233 case CPUID_MODEL_P65
:
234 case CPUID_MODEL_P66
:
235 return "Intel Celeron";
236 case CPUID_MODEL_P67
:
237 case CPUID_MODEL_P68
:
238 case CPUID_MODEL_P6A
:
239 case CPUID_MODEL_P6B
:
240 return "Intel Pentium III";
241 case CPUID_MODEL_PM9
:
242 case CPUID_MODEL_PMD
:
243 return "Intel Pentium M";
245 return "Unknown Intel P6 Family";
247 case CPUID_FAMILY_ITANIUM
:
248 return "Intel Itanium";
249 case CPUID_FAMILY_EXTENDED
:
250 switch (info_p
->cpuid_extfamily
) {
251 case CPUID_EXTFAMILY_PENTIUM4
:
252 return "Intel Pentium 4";
253 case CPUID_EXTFAMILY_ITANIUM2
:
254 return "Intel Itanium 2";
257 return "Unknown Intel Family";
260 case CPUID_BRAND_CELERON_1
:
261 case CPUID_BRAND_CELERON_A
:
262 case CPUID_BRAND_CELERON_14
:
263 return "Intel Celeron";
264 case CPUID_BRAND_PENTIUM_III_2
:
265 case CPUID_BRAND_PENTIUM_III_4
:
266 return "Pentium III";
267 case CPUID_BRAND_PIII_XEON
:
268 if (info_p
->cpuid_signature
== 0x6B1)
269 return "Intel Celeron";
271 return "Intel Pentium III Xeon";
272 case CPUID_BRAND_PENTIUM_III_M
:
273 return "Mobile Intel Pentium III-M";
274 case CPUID_BRAND_M_CELERON_7
:
275 case CPUID_BRAND_M_CELERON_F
:
276 case CPUID_BRAND_M_CELERON_13
:
277 case CPUID_BRAND_M_CELERON_17
:
278 return "Mobile Intel Celeron";
279 case CPUID_BRAND_PENTIUM4_8
:
280 case CPUID_BRAND_PENTIUM4_9
:
281 return "Intel Pentium 4";
282 case CPUID_BRAND_XEON
:
284 case CPUID_BRAND_XEON_MP
:
285 return "Intel Xeon MP";
286 case CPUID_BRAND_PENTIUM4_M
:
287 if (info_p
->cpuid_signature
== 0xF13)
290 return "Mobile Intel Pentium 4";
291 case CPUID_BRAND_CELERON_M
:
292 return "Intel Celeron M";
293 case CPUID_BRAND_PENTIUM_M
:
294 return "Intel Pentium M";
295 case CPUID_BRAND_MOBILE_15
:
296 case CPUID_BRAND_MOBILE_17
:
297 return "Mobile Intel";
300 return "Unknown Intel";
303 static void set_intel_cache_info( i386_cpu_info_t
* info_p
)
305 uint32_t cpuid_result
[4];
306 uint32_t l1d_cache_linesize
= 0;
310 /* get processor cache descriptor info */
311 do_cpuid(2, cpuid_result
);
312 for (j
= 0; j
< 4; j
++) {
313 if ((cpuid_result
[j
] >> 31) == 1) /* bit31 is validity */
315 ((uint32_t *) info_p
->cache_info
)[j
] = cpuid_result
[j
];
317 /* first byte gives number of cpuid calls to get all descriptors */
318 for (i
= 1; i
< info_p
->cache_info
[0]; i
++) {
319 if (i
*16 > sizeof(info_p
->cache_info
))
321 do_cpuid(2, cpuid_result
);
322 for (j
= 0; j
< 4; j
++) {
323 if ((cpuid_result
[j
] >> 31) == 1)
325 ((uint32_t *) info_p
->cache_info
)[4*i
+j
] =
330 /* decode the descriptors looking for L1/L2/L3 size info */
331 for (i
= 1; i
< sizeof(info_p
->cache_info
); i
++) {
332 cpuid_cache_desc_t
*descp
;
333 uint8_t desc
= info_p
->cache_info
[i
];
335 if (desc
== CPUID_CACHE_NULL
)
337 for (descp
= cpuid_cache_desc_tab
;
338 descp
->value
!= CPUID_CACHE_NULL
; descp
++) {
339 if (descp
->value
!= desc
)
341 info_p
->cache_size
[descp
->type
] = descp
->size
;
342 if (descp
->type
== L2U
)
343 info_p
->cache_linesize
= descp
->linesize
;
344 if (descp
->type
== L1D
)
345 l1d_cache_linesize
= descp
->linesize
;
349 /* For P-IIIs, L2 could be 256k or 512k but we can't tell */
350 if (info_p
->cache_size
[L2U
] == 0 &&
351 info_p
->cpuid_family
== 0x6 && info_p
->cpuid_model
== 0xb) {
352 info_p
->cache_size
[L2U
] = 256*1024;
353 info_p
->cache_linesize
= 32;
355 /* If we have no L2 cache, use the L1 data cache line size */
356 if (info_p
->cache_size
[L2U
] == 0)
357 info_p
->cache_linesize
= l1d_cache_linesize
;
360 static void set_cpu_intel( i386_cpu_info_t
* info_p
)
362 set_cpu_generic(info_p
);
363 set_intel_cache_info(info_p
);
364 info_p
->cpuid_model_string
= get_intel_model_string(info_p
);
367 static const char * get_amd_model_string( i386_cpu_info_t
* info_p
)
369 switch (info_p
->cpuid_family
)
371 case CPUID_FAMILY_486
:
372 switch (info_p
->cpuid_model
) {
373 case CPUID_MODEL_AM486_DX
:
374 case CPUID_MODEL_AM486_DX2
:
375 case CPUID_MODEL_AM486_DX2WB
:
376 case CPUID_MODEL_AM486_DX4
:
377 case CPUID_MODEL_AM486_DX4WB
:
379 case CPUID_MODEL_AM486_5X86
:
380 case CPUID_MODEL_AM486_5X86WB
:
384 case CPUID_FAMILY_586
:
385 switch (info_p
->cpuid_model
) {
386 case CPUID_MODEL_K5M0
:
387 case CPUID_MODEL_K5M1
:
388 case CPUID_MODEL_K5M2
:
389 case CPUID_MODEL_K5M3
:
391 case CPUID_MODEL_K6M6
:
392 case CPUID_MODEL_K6M7
:
394 case CPUID_MODEL_K6_2
:
396 case CPUID_MODEL_K6_III
:
400 case CPUID_FAMILY_686
:
401 switch (info_p
->cpuid_model
) {
402 case CPUID_MODEL_ATHLON_M1
:
403 case CPUID_MODEL_ATHLON_M2
:
404 case CPUID_MODEL_ATHLON_M4
:
405 case CPUID_MODEL_ATHLON_M6
:
406 case CPUID_MODEL_ATHLON_M8
:
407 case CPUID_MODEL_ATHLON_M10
:
409 case CPUID_MODEL_DURON_M3
:
410 case CPUID_MODEL_DURON_M7
:
413 return "Unknown AMD Athlon";
415 case CPUID_FAMILY_EXTENDED
:
416 switch (info_p
->cpuid_model
) {
417 case CPUID_MODEL_ATHLON64
:
418 return "AMD Athlon 64";
419 case CPUID_MODEL_OPTERON
:
420 return "AMD Opteron";
422 return "Unknown AMD-64";
425 return "Unknown AMD";
428 static void set_amd_cache_info( i386_cpu_info_t
* info_p
)
430 uint32_t cpuid_result
[4];
432 /* It would make sense to fill in info_p->cache_info with complete information
433 * on the TLBs and data cache associativity, lines, etc, either by mapping
434 * to the Intel tags (if possible), or replacing cache_info with a generic
435 * mechanism. But right now, nothing makes use of that information (that I know
439 /* L1 Cache and TLB Information */
440 do_cpuid(0x80000005, cpuid_result
);
442 /* EAX: TLB Information for 2-Mbyte and 4-MByte Pages */
445 /* EBX: TLB Information for 4-Kbyte Pages */
448 /* ECX: L1 Data Cache Information */
449 info_p
->cache_size
[L1D
] = ((cpuid_result
[2] >> 24) & 0xFF) * 1024;
450 info_p
->cache_linesize
= (cpuid_result
[2] & 0xFF);
452 /* EDX: L1 Instruction Cache Information */
453 info_p
->cache_size
[L1I
] = ((cpuid_result
[3] >> 24) & 0xFF) * 1024;
455 /* L2 Cache Information */
456 do_cpuid(0x80000006, cpuid_result
);
458 /* EAX: L2 TLB Information for 2-Mbyte and 4-Mbyte Pages */
461 /* EBX: L2 TLB Information for 4-Kbyte Pages */
464 /* ECX: L2 Cache Information */
465 info_p
->cache_size
[L2U
] = ((cpuid_result
[2] >> 16) & 0xFFFF) * 1024;
466 if (info_p
->cache_size
[L2U
] > 0)
467 info_p
->cache_linesize
= cpuid_result
[2] & 0xFF;
470 static void set_cpu_amd( i386_cpu_info_t
* info_p
)
472 set_cpu_generic(info_p
);
473 set_amd_cache_info(info_p
);
474 info_p
->cpuid_model_string
= get_amd_model_string(info_p
);
477 static void set_cpu_nsc( i386_cpu_info_t
* info_p
)
479 set_cpu_generic(info_p
);
480 set_amd_cache_info(info_p
);
482 if (info_p
->cpuid_family
== CPUID_FAMILY_586
&& info_p
->cpuid_model
== CPUID_MODEL_GX1
)
483 info_p
->cpuid_model_string
= "AMD Geode GX1";
484 else if (info_p
->cpuid_family
== CPUID_FAMILY_586
&& info_p
->cpuid_model
== CPUID_MODEL_GX2
)
485 info_p
->cpuid_model_string
= "AMD Geode GX";
487 info_p
->cpuid_model_string
= "Unknown National Semiconductor";
491 set_cpu_generic(i386_cpu_info_t
*info_p
)
493 uint32_t cpuid_result
[4];
497 /* get extended cpuid results */
498 do_cpuid(0x80000000, cpuid_result
);
499 max_extid
= cpuid_result
[0];
501 /* check to see if we can get brand string */
502 if (max_extid
>= 0x80000004) {
504 * The brand string 48 bytes (max), guaranteed to
507 do_cpuid(0x80000002, cpuid_result
);
508 bcopy((char *)cpuid_result
, &str
[0], 16);
509 do_cpuid(0x80000003, cpuid_result
);
510 bcopy((char *)cpuid_result
, &str
[16], 16);
511 do_cpuid(0x80000004, cpuid_result
);
512 bcopy((char *)cpuid_result
, &str
[32], 16);
513 for (p
= str
; *p
!= '\0'; p
++) {
514 if (*p
!= ' ') break;
516 strncpy(info_p
->cpuid_brand_string
,
517 p
, sizeof(info_p
->cpuid_brand_string
)-1);
518 info_p
->cpuid_brand_string
[sizeof(info_p
->cpuid_brand_string
)-1] = '\0';
520 if (!strcmp(info_p
->cpuid_brand_string
, CPUID_STRING_UNKNOWN
)) {
522 * This string means we have a BIOS-programmable brand string,
523 * and the BIOS couldn't figure out what sort of CPU we have.
525 info_p
->cpuid_brand_string
[0] = '\0';
529 /* get processor signature and decode */
530 do_cpuid(1, cpuid_result
);
531 info_p
->cpuid_signature
= cpuid_result
[0];
532 info_p
->cpuid_stepping
= cpuid_result
[0] & 0x0f;
533 info_p
->cpuid_model
= (cpuid_result
[0] >> 4) & 0x0f;
534 info_p
->cpuid_family
= (cpuid_result
[0] >> 8) & 0x0f;
535 info_p
->cpuid_type
= (cpuid_result
[0] >> 12) & 0x03;
536 info_p
->cpuid_extmodel
= (cpuid_result
[0] >> 16) & 0x0f;
537 info_p
->cpuid_extfamily
= (cpuid_result
[0] >> 20) & 0xff;
538 info_p
->cpuid_brand
= cpuid_result
[1] & 0xff;
539 info_p
->cpuid_features
= cpuid_result
[3];
545 set_cpu_unknown(__unused i386_cpu_info_t
*info_p
)
547 info_p
->cpuid_model_string
= "Unknown";
554 } feature_names
[] = {
555 {CPUID_FEATURE_FPU
, "FPU",},
556 {CPUID_FEATURE_VME
, "VME",},
557 {CPUID_FEATURE_DE
, "DE",},
558 {CPUID_FEATURE_PSE
, "PSE",},
559 {CPUID_FEATURE_TSC
, "TSC",},
560 {CPUID_FEATURE_MSR
, "MSR",},
561 {CPUID_FEATURE_PAE
, "PAE",},
562 {CPUID_FEATURE_MCE
, "MCE",},
563 {CPUID_FEATURE_CX8
, "CX8",},
564 {CPUID_FEATURE_APIC
, "APIC",},
565 {CPUID_FEATURE_SEP
, "SEP",},
566 {CPUID_FEATURE_MTRR
, "MTRR",},
567 {CPUID_FEATURE_PGE
, "PGE",},
568 {CPUID_FEATURE_MCA
, "MCA",},
569 {CPUID_FEATURE_CMOV
, "CMOV",},
570 {CPUID_FEATURE_PAT
, "PAT",},
571 {CPUID_FEATURE_PSE36
, "PSE36",},
572 {CPUID_FEATURE_PSN
, "PSN",},
573 {CPUID_FEATURE_CLFSH
, "CLFSH",},
574 {CPUID_FEATURE_DS
, "DS",},
575 {CPUID_FEATURE_ACPI
, "ACPI",},
576 {CPUID_FEATURE_MMX
, "MMX",},
577 {CPUID_FEATURE_FXSR
, "FXSR",},
578 {CPUID_FEATURE_SSE
, "SSE",},
579 {CPUID_FEATURE_SSE2
, "SSE2",},
580 {CPUID_FEATURE_SS
, "SS",},
581 {CPUID_FEATURE_HTT
, "HTT",},
582 {CPUID_FEATURE_TM
, "TM",},
587 cpuid_get_feature_names(uint32_t feature
, char *buf
, unsigned buf_len
)
593 for (i
= 0; feature_names
[i
].mask
!= 0; i
++) {
594 if ((feature
& feature_names
[i
].mask
) == 0)
598 len
= min(strlen(feature_names
[i
].name
), (buf_len
-1) - (p
-buf
));
601 bcopy(feature_names
[i
].name
, p
, len
);
609 cpuid_feature_display(
615 printf("%s: %s\n", header
,
616 cpuid_get_feature_names(cpuid_features(), buf
, sizeof(buf
)));
624 if (cpuid_cpu_info
.cpuid_brand_string
[0] != '\0') {
625 printf("%s: %s\n", header
,
626 cpuid_cpu_info
.cpuid_brand_string
);
633 return cpuid_cpu_info
.cpuid_family
;
639 static int checked
= 0;
640 char fpu_arg
[16] = { 0 };
642 /* check for boot-time fpu limitations */
643 if (PE_parse_boot_arg("_fpu", &fpu_arg
[0])) {
644 printf("limiting fpu features to: %s\n", fpu_arg
);
645 if (!strncmp("387", fpu_arg
, sizeof "387") || !strncmp("mmx", fpu_arg
, sizeof "mmx")) {
646 printf("no sse or sse2\n");
647 cpuid_cpu_info
.cpuid_features
&= ~(CPUID_FEATURE_SSE
| CPUID_FEATURE_SSE2
| CPUID_FEATURE_FXSR
);
648 } else if (!strncmp("sse", fpu_arg
, sizeof "sse")) {
650 cpuid_cpu_info
.cpuid_features
&= ~(CPUID_FEATURE_SSE2
);
655 return cpuid_cpu_info
.cpuid_features
;
661 return &cpuid_cpu_info
;
664 /* XXX for temporary compatibility */
668 cpuid_get_info(&cpuid_cpu_info
);
669 cpuid_feature
= cpuid_cpu_info
.cpuid_features
; /* XXX compat */