osfmk/i386/AT386/rtc.h

   1 /*
   2  * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
   3  *
   4  * @APPLE_LICENSE_OSREFERENCE_HEADER_START@
   5  *
   6  * This file contains Original Code and/or Modifications of Original Code
   7  * as defined in and that are subject to the Apple Public Source License
   8  * Version 2.0 (the 'License'). You may not use this file except in
   9  * compliance with the License.  The rights granted to you under the
  10  * License may not be used to create, or enable the creation or
  11  * redistribution of, unlawful or unlicensed copies of an Apple operating
  12  * system, or to circumvent, violate, or enable the circumvention or
  13  * violation of, any terms of an Apple operating system software license
  14  * agreement.
  15  *
  16  * Please obtain a copy of the License at
  17  * http://www.opensource.apple.com/apsl/ and read it before using this
  18  * file.
  19  *
  20  * The Original Code and all software distributed under the License are
  21  * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
  22  * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
  23  * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
  25  * Please see the License for the specific language governing rights and
  26  * limitations under the License.
  27  *
  28  * @APPLE_LICENSE_OSREFERENCE_HEADER_END@
  29  */
  30 /*
  31  * @OSF_COPYRIGHT@
  32  */
  33 /*
  34  * HISTORY
  35  *
  36  * Revision 1.1.1.1  1998/09/22 21:05:39  wsanchez
  37  * Import of Mac OS X kernel (~semeria)
  38  *
  39  * Revision 1.1.1.1  1998/03/07 02:25:40  wsanchez
  40  * Import of OSF Mach kernel (~mburg)
  41  *
  42  * Revision 1.1.6.1  1994/09/23  01:47:30  ezf
  43  *      change marker to not FREE
  44  *      [1994/09/22  21:20:22  ezf]
  45  *
  46  * Revision 1.1.2.3  1993/08/09  19:39:04  dswartz
  47  *      Add ANSI prototypes - CR#9523
  48  *      [1993/08/06  17:51:17  dswartz]
  49  *
  50  * Revision 1.1.2.2  1993/06/02  23:21:32  jeffc
  51  *      Added to OSF/1 R1.3 from NMK15.0.
  52  *      [1993/06/02  21:03:17  jeffc]
  53  *
  54  * Revision 1.1  1992/09/30  02:27:20  robert
  55  *      Initial revision
  56  *
  57  * $EndLog$
  58  */
  59 /* CMU_HIST */
  60 /*
  61  * Revision 2.7  91/05/14  16:30:03  mrt
  62  *      Correcting copyright
  63  *
  64  * Revision 2.6  91/03/16  14:47:03  rpd
  65  *      Fixed ioctl definitions for ANSI C.
  66  *      [91/02/20            rpd]
  67  *
  68  * Revision 2.5  91/02/05  17:20:25  mrt
  69  *      Changed to new Mach copyright
  70  *      [91/02/01  17:47:16  mrt]
  71  *
  72  * Revision 2.4  90/11/26  14:51:02  rvb
  73  *      jsb bet me to XMK34, sigh ...
  74  *      [90/11/26            rvb]
  75  *      Synched 2.5 & 3.0 at I386q (r1.5.1.3) & XMK35 (r2.4)
  76  *      [90/11/15            rvb]
  77  *
  78  * Revision 1.5.1.2  90/07/27  11:27:06  rvb
  79  *      Fix Intel Copyright as per B. Davies authorization.
  80  *      [90/07/27            rvb]
  81  *
  82  * Revision 2.2  90/05/03  15:46:11  dbg
  83  *      First checkin.
  84  *
  85  * Revision 1.5.1.1  90/01/08  13:29:46  rvb
  86  *      Add Intel copyright.
  87  *      [90/01/08            rvb]
  88  *
  89  * Revision 1.5  89/09/25  12:27:37  rvb
  90  *      File was provided by Intel 9/18/89.
  91  *      [89/09/23            rvb]
  92  *
  93  */
  94 /* CMU_ENDHIST */
  95 /*
  96  * Mach Operating System
  97  * Copyright (c) 1991,1990,1989 Carnegie Mellon University
  98  * All Rights Reserved.
  99  *
 100  * Permission to use, copy, modify and distribute this software and its
 101  * documentation is hereby granted, provided that both the copyright
 102  * notice and this permission notice appear in all copies of the
 103  * software, derivative works or modified versions, and any portions
 104  * thereof, and that both notices appear in supporting documentation.
 105  *
 106  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
 107  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
 108  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
 109  *
 110  * Carnegie Mellon requests users of this software to return to
 111  *
 112  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
 113  *  School of Computer Science
 114  *  Carnegie Mellon University
 115  *  Pittsburgh PA 15213-3890
 116  *
 117  * any improvements or extensions that they make and grant Carnegie Mellon
 118  * the rights to redistribute these changes.
 119  */
 120 /*
 121  */
 122
 123 /*
 124  *   Copyright 1988, 1989 by Intel Corporation, Santa Clara, California.
 125  *
 126  *              All Rights Reserved
 127  *
 128  * Permission to use, copy, modify, and distribute this software and
 129  * its documentation for any purpose and without fee is hereby
 130  * granted, provided that the above copyright notice appears in all
 131  * copies and that both the copyright notice and this permission notice
 132  * appear in supporting documentation, and that the name of Intel
 133  * not be used in advertising or publicity pertaining to distribution
 134  * of the software without specific, written prior permission.
 135  *
 136  * INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE
 137  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS,
 138  * IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR
 139  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
 140  * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT,
 141  * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION
 142  * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 143  */
 144
 145 #define RTC_ADDR        0x70    /* I/O port address for register select */
 146 #define RTC_DATA        0x71    /* I/O port address for data read/write */
 147
 148 /*
 149  * Register A definitions
 150  */
 151 #define RTC_A           0x0a    /* register A address */
 152 #define RTC_UIP         0x80    /* Update in progress bit */
 153 #define RTC_DIV0        0x00    /* Time base of 4.194304 MHz */
 154 #define RTC_DIV1        0x10    /* Time base of 1.048576 MHz */
 155 #define RTC_DIV2        0x20    /* Time base of 32.768 KHz */
 156 #define RTC_RATE6       0x06    /* interrupt rate of 976.562 */
 157
 158 /*
 159  * Register B definitions
 160  */
 161 #define RTC_B           0x0b    /* register B address */
 162 #define RTC_SET         0x80    /* stop updates for time set */
 163 #define RTC_PIE         0x40    /* Periodic interrupt enable */
 164 #define RTC_AIE         0x20    /* Alarm interrupt enable */
 165 #define RTC_UIE         0x10    /* Update ended interrupt enable */
 166 #define RTC_SQWE        0x08    /* Square wave enable */
 167 #define RTC_DM          0x04    /* Date mode, 1 = binary, 0 = BCD */
 168 #define RTC_HM          0x02    /* hour mode, 1 = 24 hour, 0 = 12 hour */
 169 #define RTC_DSE         0x01    /* Daylight savings enable */
 170
 171 /*
 172  * Register C definitions
 173  */
 174 #define RTC_C           0x0c    /* register C address */
 175 #define RTC_IRQF        0x80    /* IRQ flag */
 176 #define RTC_PF          0x40    /* PF flag bit */
 177 #define RTC_AF          0x20    /* AF flag bit */
 178 #define RTC_UF          0x10    /* UF flag bit */
 179
 180 /*
 181  * Register D definitions
 182  */
 183 #define RTC_D           0x0d    /* register D address */
 184 #define RTC_VRT         0x80    /* Valid RAM and time bit */
 185
 186 #define RTC_NREG        0x0e    /* number of RTC registers */
 187 #define RTC_NREGP       0x0a    /* number of RTC registers to set time */
 188
 189 #define RTCRTIME        _IOR('c', 0x01, struct rtc_st) /* Read time from RTC */
 190 #define RTCSTIME        _IOW('c', 0x02, struct rtc_st) /* Set time into RTC */
 191
 192 struct rtc_st {
 193         char    rtc_sec;
 194         char    rtc_asec;
 195         char    rtc_min;
 196         char    rtc_amin;
 197         char    rtc_hr;
 198         char    rtc_ahr;
 199         char    rtc_dow;
 200         char    rtc_dom;
 201         char    rtc_mon;
 202         char    rtc_yr;
 203         char    rtc_statusa;
 204         char    rtc_statusb;
 205         char    rtc_statusc;
 206         char    rtc_statusd;
 207 };
 208
 209 /*
 210  * this macro reads contents of real time clock to specified buffer
 211  */
 212 #define load_rtc(regs) \
 213 {\
 214         register int i; \
 215         \
 216         for (i = 0; i < RTC_NREG; i++) { \
 217                 outb(RTC_ADDR, i); \
 218                 (regs)[i] = inb(RTC_DATA); \
 219         } \
 220 }
 221
 222 /*
 223  * this macro writes contents of specified buffer to real time clock
 224  */
 225 #define save_rtc(regs) \
 226 { \
 227         register int i; \
 228         for (i = 0; i < RTC_NREGP; i++) { \
 229                 outb(RTC_ADDR, i); \
 230                 outb(RTC_DATA, (regs)[i]);\
 231         } \
 232 }
 233
 234