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1/*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
12 *
13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23/*
24 * @OSF_COPYRIGHT@
25 */
26
27/*
28 * Mach Operating System
29 * Copyright (c) 1991,1990 Carnegie Mellon University
30 * All Rights Reserved.
31 *
32 * Permission to use, copy, modify and distribute this software and its
33 * documentation is hereby granted, provided that both the copyright
34 * notice and this permission notice appear in all copies of the
35 * software, derivative works or modified versions, and any portions
36 * thereof, and that both notices appear in supporting documentation.
37 *
38 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
39 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
40 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
41 *
42 * Carnegie Mellon requests users of this software to return to
43 *
44 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
45 * School of Computer Science
46 * Carnegie Mellon University
47 * Pittsburgh PA 15213-3890
48 *
49 * any improvements or extensions that they make and grant Carnegie Mellon
50 * the rights to redistribute these changes.
51 */
52
53#include <i386/asm.h>
54#include <i386/mp_slave_boot.h>
55#include <i386/postcode.h>
56
57#define CR0_PE_ON 0x1
58#define CR0_PE_OFF 0xfffffffe
59
60 .file "slave_boot.s"
61
62 .text
63 .align 12 // Page align for single bcopy_phys()
64
65#define LJMP(segment,address) \
66 .byte 0xea ;\
67 .long address-EXT(slave_boot_base) ;\
68 .word segment
69
70#define LGDT(address) \
71 .word 0x010f ;\
72 .byte 0x15 ;\
73 .long address-EXT(slave_boot_base)
74
75Entry(slave_boot_base)
76 /* code is loaded at 0x0:0x1000 */
77 /* ljmp to the next instruction to set up %cs */
78 data16
79 LJMP(MP_BOOTSEG, EXT(slave_pstart))
80
81Entry(slave_pstart)
82 /* set up %ds */
83 mov %cs, %ax
84 mov %ax, %ds
85
86 POSTCODE(SLAVE_PSTART_ENTRY);
87
88 /* set up %ss and %esp */
89 data16
90 mov $(MP_BOOTSEG), %eax
91 mov %ax, %ss
92 data16
93 mov $(MP_BOOTSTACK), %esp
94
95 /*set up %es */
96 mov %ax, %es
97
98 /* change to protected mode */
99 data16
100 call EXT(real_to_prot)
101
102 push MP_MACH_START
103 call EXT(startprog)
104
105/*
106 real_to_prot()
107 transfer from real mode to protected mode.
108*/
109
110Entry(real_to_prot)
111 /* guarantee that interrupt is disabled when in prot mode */
112 cli
113
114 POSTCODE(REAL_TO_PROT_ENTRY);
115
116 /* load the gdtr */
117 addr16
118 data16
119 LGDT(EXT(gdtr))
120
121 /* load the gdtr */
122 /* set the PE bit of CR0 */
123 mov %cr0, %eax
124
125 data16
126 or $(CR0_PE_ON), %eax
127 mov %eax, %cr0
128
129 /* make intrasegment jump to flush the processor pipeline and */
130 /* reload CS register */
131 data16
132 LJMP(0x08, xprot)
133
134xprot:
135
136 /* we are in USE32 mode now */
137 /* set up the protective mode segment registers : DS, SS, ES */
138 mov $0x10, %eax
139 movw %ax, %ds
140 movw %ax, %ss
141 movw %ax, %es
142
143 POSTCODE(REAL_TO_PROT_EXIT);
144
145 ret
146
147/*
148 startprog(phyaddr)
149 start the program on protected mode where phyaddr is the entry point
150*/
151
152Entry(startprog)
153 push %ebp
154 movl %esp, %ebp
155
156 POSTCODE(STARTPROG_ENTRY);
157
158 movl 0x8(%ebp), %ecx /* entry offset */
159 movl $0x28, %ebx /* segment */
160 push %ebx
161 push %ecx
162
163 /* set up %ds and %es */
164 movl $0x20, %ebx
165 movw %bx, %ds
166 movw %bx, %es
167
168 POSTCODE(STARTPROG_EXIT);
169
170 lret
171
172
173 . = MP_BOOTGDT-MP_BOOT /* GDT location */
174Entry(Gdt)
175
176/* Segment Descriptor
177 *
178 * 31 24 19 16 7 0
179 * ------------------------------------------------------------
180 * | | |B| |A| | | |1|0|E|W|A| |
181 * | BASE 31..24 |G|/|0|V| LIMIT |P|DPL| TYPE | BASE 23:16 |
182 * | | |D| |L| 19..16| | |1|1|C|R|A| |
183 * ------------------------------------------------------------
184 * | | |
185 * | BASE 15..0 | LIMIT 15..0 |
186 * | | |
187 * ------------------------------------------------------------
188 */
189 .word 0,0 /* 0x0 : null */
190 .byte 0,0,0,0
191
192 .word 0xffff,MP_BOOT /* 0x8 : boot code */
193 .byte 0,0x9e,0xcf,0
194
195 .word 0xffff,MP_BOOT /* 0x10 : boot data */
196 .byte 0,0x92,0xcf,0
197
198 .word 0xffff,MP_BOOT /* 0x18 : boot code, 16 bits */
199 .byte 0,0x9e,0x0,0
200
201 .word 0xffff,0 /* 0x20 : init data */
202 .byte 0,0x93,0xcf,0
203
204 .word 0xffff,0 /* 0x28 : init code */
205 .byte 0,0x9f,0xcf,0
206
207Entry(gdtr)
208 .short 48 /* limit (8*6 segs) */
209 .short MP_BOOTGDT /* base low */
210 .short 0 /* base high */
211
212Entry(slave_boot_end)
213
214
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