| | 1 | /* |
| | 2 | * Copyright (c) 2003 Apple Computer, Inc. All rights reserved. |
| | 3 | * |
| | 4 | * @APPLE_LICENSE_OSREFERENCE_HEADER_START@ |
| | 5 | * |
| | 6 | * This file contains Original Code and/or Modifications of Original Code |
| | 7 | * as defined in and that are subject to the Apple Public Source License |
| | 8 | * Version 2.0 (the 'License'). You may not use this file except in |
| | 9 | * compliance with the License. The rights granted to you under the |
| | 10 | * License may not be used to create, or enable the creation or |
| | 11 | * redistribution of, unlawful or unlicensed copies of an Apple operating |
| | 12 | * system, or to circumvent, violate, or enable the circumvention or |
| | 13 | * violation of, any terms of an Apple operating system software license |
| | 14 | * agreement. |
| | 15 | * |
| | 16 | * Please obtain a copy of the License at |
| | 17 | * http://www.opensource.apple.com/apsl/ and read it before using this |
| | 18 | * file. |
| | 19 | * |
| | 20 | * The Original Code and all software distributed under the License are |
| | 21 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER |
| | 22 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
| | 23 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, |
| | 24 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
| | 25 | * Please see the License for the specific language governing rights and |
| | 26 | * limitations under the License. |
| | 27 | * |
| | 28 | * @APPLE_LICENSE_OSREFERENCE_HEADER_END@ |
| | 29 | */ |
| | 30 | |
| | 31 | #define ASSEMBLER |
| | 32 | #include <sys/appleapiopts.h> |
| | 33 | #include <ppc/asm.h> // EXT, LEXT |
| | 34 | #include <machine/cpu_capabilities.h> |
| | 35 | #include <machine/commpage.h> |
| | 36 | |
| | 37 | .text |
| | 38 | .align 2 |
| | 39 | |
| | 40 | |
| | 41 | // ********************************************* |
| | 42 | // * C O M M P A G E _ F L U S H _ D C A C H E * |
| | 43 | // ********************************************* |
| | 44 | // |
| | 45 | // Note that this routine is called both in 32 and 64-bit mode. |
| | 46 | // |
| | 47 | // r3 = ptr to 1st byte to flush |
| | 48 | // r4 = length to flush (may be 0) |
| | 49 | |
| | 50 | commpage_flush_dcache: |
| | 51 | mr. r4,r4 // test length for 0 in mode-independent way |
| | 52 | lhz r5,_COMM_PAGE_CACHE_LINESIZE(0) |
| | 53 | subi r9,r5,1 // get (linesize-1) |
| | 54 | and r0,r3,r9 // get offset within line of 1st byte |
| | 55 | add r4,r4,r0 // adjust length so we flush them all |
| | 56 | add r4,r4,r9 // round length up... |
| | 57 | andc r4,r4,r9 // ...to multiple of cache lines |
| | 58 | beqlr-- // length was 0, so exit |
| | 59 | 1: |
| | 60 | sub. r4,r4,r5 // more to go? |
| | 61 | dcbf 0,r3 // flush another line |
| | 62 | add r3,r3,r5 |
| | 63 | bne 1b |
| | 64 | sync // make sure lines are flushed before we return |
| | 65 | blr |
| | 66 | |
| | 67 | COMMPAGE_DESCRIPTOR(commpage_flush_dcache,_COMM_PAGE_FLUSH_DCACHE,0,0,kCommPageBoth) |
| | 68 | |
| | 69 | |
| | 70 | // ********************************************* |
| | 71 | // * C O M M P A G E _ F L U S H _ I C A C H E * |
| | 72 | // ********************************************* |
| | 73 | // |
| | 74 | // Note that this routine is called both in 32 and 64-bit mode. |
| | 75 | // |
| | 76 | // r3 = ptr to 1st byte to flush |
| | 77 | // r4 = length to flush (may be 0) |
| | 78 | |
| | 79 | commpage_flush_icache: |
| | 80 | mr. r4,r4 // test length for 0 in mode-independent way |
| | 81 | lhz r5,_COMM_PAGE_CACHE_LINESIZE(0) |
| | 82 | subi r9,r5,1 // get (linesize-1) |
| | 83 | and r0,r3,r9 // get offset within line of 1st byte |
| | 84 | add r4,r4,r0 // adjust length so we flush them all |
| | 85 | mr r7,r3 // copy ptr |
| | 86 | add r4,r4,r9 // round length up... |
| | 87 | andc r4,r4,r9 // ...to multiple of cache lines |
| | 88 | mr r6,r4 // copy length |
| | 89 | beqlr-- // length was 0, so exit |
| | 90 | 1: |
| | 91 | sub. r4,r4,r5 // more to go? |
| | 92 | dcbf 0,r3 // flush another line |
| | 93 | add r3,r3,r5 |
| | 94 | bne 1b |
| | 95 | sync // make sure lines are flushed |
| | 96 | 2: |
| | 97 | sub. r6,r6,r5 // more to go? |
| | 98 | icbi 0,r7 |
| | 99 | add r7,r7,r5 |
| | 100 | bne 2b |
| | 101 | |
| | 102 | // The following sync is only needed on MP machines, probably only on |
| | 103 | // 7400-family MP machines. But because we're not certain of this, and |
| | 104 | // this isn't a speed critical routine, we are conservative and always sync. |
| | 105 | |
| | 106 | sync // wait until other processors see the icbi's |
| | 107 | isync // make sure we haven't prefetched old instructions |
| | 108 | |
| | 109 | blr |
| | 110 | |
| | 111 | COMMPAGE_DESCRIPTOR(commpage_flush_icache,_COMM_PAGE_FLUSH_ICACHE,0,0,kCommPageBoth) |
| | 112 | |
| | 113 | |
projects / apple / xnu.git / blame_incremental