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	1	/*
	2	* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
	5	*
	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
	14	*
	15	* Please obtain a copy of the License at
	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
	17	*
	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
	25	*
	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
	27	*/
	28	/*
	29	* @OSF_COPYRIGHT@
	30	*/
	31	/*
	32	* Mach Operating System
	33	* Copyright (c) 1992-1989 Carnegie Mellon University
	34	* All Rights Reserved.
	35	*
	36	* Permission to use, copy, modify and distribute this software and its
	37	* documentation is hereby granted, provided that both the copyright
	38	* notice and this permission notice appear in all copies of the
	39	* software, derivative works or modified versions, and any portions
	40	* thereof, and that both notices appear in supporting documentation.
	41	*
	42	* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
	43	* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
	44	* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
	45	*
	46	* Carnegie Mellon requests users of this software to return to
	47	*
	48	* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
	49	* School of Computer Science
	50	* Carnegie Mellon University
	51	* Pittsburgh PA 15213-3890
	52	*
	53	* any improvements or extensions that they make and grant Carnegie Mellon
	54	* the rights to redistribute these changes.
	55	*/
	56	/*
	57	*/
	58
	59	#ifndef _I386_FP_SAVE_H_
	60	#define _I386_FP_SAVE_H_
	61
	62	#ifdef MACH_KERNEL_PRIVATE
	63
	64
	65	struct x86_fx_thread_state {
	66	unsigned short fx_control; /* control */
	67	unsigned short fx_status; /* status */
	68	unsigned char fx_tag; /* register tags */
	69	unsigned char fx_bbz1; /* better be zero when calling fxrtstor */
	70	unsigned short fx_opcode;
	71	union {
	72	struct { /* 32-bit layout: */
	73	unsigned int fx_eip; /* eip instruction */
	74	unsigned short fx_cs; /* cs instruction */
	75	unsigned short fx_bbz2;/* better be zero when calling fxrtstor */
	76	unsigned int fx_dp; /* data address */
	77	unsigned short fx_ds; /* data segment */
	78	unsigned short fx_bbz3;/* better be zero when calling fxrtstor */
	79	};
	80	struct { /* 64-bit layout: */
	81	uint64_t fx_rip; /* instruction pointer */
	82	uint64_t fx_rdp; /* data pointer */
	83	};
	84	};
	85	unsigned int fx_MXCSR;
	86	unsigned int fx_MXCSR_MASK;
	87	unsigned short fx_reg_word[8][8]; /* STx/MMx registers */
	88	unsigned short fx_XMM_reg[8][16]; /* XMM0-XMM15 on 64 bit processors */
	89	/* XMM0-XMM7 on 32 bit processors... unused storage reserved */
	90
	91	unsigned char fx_reserved[16 * 5]; /* reserved by intel for future
	92	* expansion */
	93	unsigned int fp_valid;
	94	unsigned int fp_save_layout;
	95	unsigned char fx_pad[8];
	96	}__attribute__ ((packed));
	97
	98	struct xsave_header {
	99	uint64_t xstate_bv;
	100	uint64_t xcomp_bv;
	101	uint8_t xhrsvd[48];
	102	};
	103
	104	typedef struct { uint64_t lo64, hi64; }__attribute__ ((packed)) reg128_t;
	105	typedef struct { reg128_t lo128, hi128; }__attribute__ ((packed)) reg256_t;
	106	typedef struct { reg256_t lo256, hi256; }__attribute__ ((packed)) reg512_t;
	107
	108	struct x86_avx_thread_state {
	109	struct x86_fx_thread_state fp;
	110	struct xsave_header _xh; /* Offset 512, xsave header */
	111	reg128_t x_YMM_Hi128[16]; /* Offset 576, high YMMs `*/
	112	/* Offset 832, end */
	113	}__attribute__ ((packed));
	114
	115	struct x86_avx512_thread_state {
	116	struct x86_fx_thread_state fp;
	117	struct xsave_header _xh; /* Offset 512, xsave header */
	118	reg128_t x_YMM_Hi128[16]; /* Offset 576, high YMMs */
	119
	120	uint64_t x_pad[16]; /* Offset 832, unused AMD LWP */
	121	uint64_t x_BNDREGS[8]; /* Offset 960, unused MPX */
	122	uint64_t x_BNDCTL[8]; /* Offset 1024, unused MPX */
	123
	124	uint64_t x_Opmask[8]; /* Offset 1088, K0-K7 */
	125	reg256_t x_ZMM_Hi256[16]; /* Offset 1152, ZMM0..15[511:256] */
	126	reg512_t x_Hi16_ZMM[16]; /* Offset 1664, ZMM16..31[511:0] */
	127	/* Offset 2688, end */
	128	}__attribute__ ((packed));
	129
	130	typedef union {
	131	struct x86_fx_thread_state fx;
	132	struct x86_avx_thread_state avx;
	133	#if !defined(RC_HIDE_XNU_J137)
	134	struct x86_avx512_thread_state avx512;
	135	#endif
	136	} x86_ext_thread_state_t;
	137
	138	#define EVEX_PREFIX 0x62 /* AVX512's EVEX vector operation prefix */
	139	#define VEX2_PREFIX 0xC5 /* VEX 2-byte prefix for Opmask instructions */
	140	#define VEX3_PREFIX 0xC4 /* VEX 3-byte prefix for Opmask instructions */
	141
	142	#endif /* MACH_KERNEL_PRIVATE */
	143	/*
	144	* Control register
	145	*/
	146	#define FPC_IE 0x0001 /* enable invalid operation
	147	* exception */
	148	#define FPC_IM FPC_IE
	149	#define FPC_DE 0x0002 /* enable denormalized operation
	150	* exception */
	151	#define FPC_DM FPC_DE
	152	#define FPC_ZE 0x0004 /* enable zero-divide exception */
	153	#define FPC_ZM FPC_ZE
	154	#define FPC_OE 0x0008 /* enable overflow exception */
	155	#define FPC_OM FPC_OE
	156	#define FPC_UE 0x0010 /* enable underflow exception */
	157	#define FPC_PE 0x0020 /* enable precision exception */
	158	#define FPC_PC 0x0300 /* precision control: */
	159	#define FPC_PC_24 0x0000 /* 24 bits */
	160	#define FPC_PC_53 0x0200 /* 53 bits */
	161	#define FPC_PC_64 0x0300 /* 64 bits */
	162	#define FPC_RC 0x0c00 /* rounding control: */
	163	#define FPC_RC_RN 0x0000 /* round to nearest or even */
	164	#define FPC_RC_RD 0x0400 /* round down */
	165	#define FPC_RC_RU 0x0800 /* round up */
	166	#define FPC_RC_CHOP 0x0c00 /* chop */
	167	#define FPC_IC 0x1000 /* infinity control (obsolete) */
	168	#define FPC_IC_PROJ 0x0000 /* projective infinity */
	169	#define FPC_IC_AFF 0x1000 /* affine infinity (std) */
	170
	171	/*
	172	* Status register
	173	*/
	174	#define FPS_IE 0x0001 /* invalid operation */
	175	#define FPS_DE 0x0002 /* denormalized operand */
	176	#define FPS_ZE 0x0004 /* divide by zero */
	177	#define FPS_OE 0x0008 /* overflow */
	178	#define FPS_UE 0x0010 /* underflow */
	179	#define FPS_PE 0x0020 /* precision */
	180	#define FPS_SF 0x0040 /* stack flag */
	181	#define FPS_ES 0x0080 /* error summary */
	182	#define FPS_C0 0x0100 /* condition code bit 0 */
	183	#define FPS_C1 0x0200 /* condition code bit 1 */
	184	#define FPS_C2 0x0400 /* condition code bit 2 */
	185	#define FPS_TOS 0x3800 /* top-of-stack pointer */
	186	#define FPS_TOS_SHIFT 11
	187	#define FPS_C3 0x4000 /* condition code bit 3 */
	188	#define FPS_BUSY 0x8000 /* FPU busy */
	189
	190	/*
	191	* Kind of floating-point support provided by kernel.
	192	*/
	193	#define FP_NO 0 /* no floating point */
	194	#define FP_SOFT 1 /* software FP emulator */
	195	#define FP_287 2 /* 80287 */
	196	#define FP_387 3 /* 80387 or 80486 */
	197	#define FP_FXSR 4 /* Fast save/restore SIMD Extension */
	198
	199	#endif /* _I386_FP_SAVE_H_ */