[apple/xnu.git] / osfmk / i386 / machine_check.c

/*
 * Copyright (c) 2007-2011 Apple Inc. All rights reserved.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_START@
 *
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. The rights granted to you under the License
 * may not be used to create, or enable the creation or redistribution of,
 * unlawful or unlicensed copies of an Apple operating system, or to
 * circumvent, violate, or enable the circumvention or violation of, any
 * terms of an Apple operating system software license agreement.
 *
 * Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this file.
 *
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 *
 * @APPLE_OSREFERENCE_LICENSE_HEADER_END@
 */

#include <kern/zalloc.h>
#include <mach/mach_time.h>
#include <i386/cpu_data.h>
#include <i386/cpuid.h>
#include <i386/cpu_topology.h>
#include <i386/cpu_threads.h>
#include <i386/lapic.h>
#include <i386/machine_cpu.h>
#include <i386/machine_check.h>
#include <i386/proc_reg.h>

/*
 * At the time of the machine-check exception, all hardware-threads panic.
 * Each thread saves the state of its MCA registers to its per-cpu data area.
 *
 * State reporting is serialized so one thread dumps all valid state for all
 * threads to the panic log. This may entail spinning waiting for other
 * threads to complete saving state to memory. A timeout applies to this wait
 * -- in particular, a 3-strikes timeout may prevent a thread from taking
 * part is the affair.
 */

#define IF(bool, str)    ((bool) ? (str) : "")

static boolean_t        mca_initialized = FALSE;
static boolean_t        mca_MCE_present = FALSE;
static boolean_t        mca_MCA_present = FALSE;
static uint32_t         mca_family = 0;
static unsigned int     mca_error_bank_count = 0;
static boolean_t        mca_control_MSR_present = FALSE;
static boolean_t        mca_cmci_present = FALSE;
static ia32_mcg_cap_t   ia32_mcg_cap;
decl_simple_lock_data(static, mca_lock);

typedef struct {
	ia32_mci_ctl_t          mca_mci_ctl;
	ia32_mci_status_t       mca_mci_status;
	ia32_mci_misc_t         mca_mci_misc;
	ia32_mci_addr_t         mca_mci_addr;
} mca_mci_bank_t;

typedef struct mca_state {
	boolean_t               mca_is_saved;
	boolean_t               mca_is_valid;   /* some state is valid */
	ia32_mcg_ctl_t          mca_mcg_ctl;
	ia32_mcg_status_t       mca_mcg_status;
	mca_mci_bank_t          mca_error_bank[0];
} mca_state_t;

typedef enum {
	CLEAR,
	DUMPING,
	DUMPED
} mca_dump_state_t;
static volatile mca_dump_state_t mca_dump_state = CLEAR;

static void
mca_get_availability(void)
{
	uint64_t        features = cpuid_info()->cpuid_features;
	uint32_t        family =   cpuid_info()->cpuid_family;
	uint32_t        model =    cpuid_info()->cpuid_model;
	uint32_t        stepping = cpuid_info()->cpuid_stepping;

	if ((model == CPUID_MODEL_HASWELL && stepping < 3) ||
	    (model == CPUID_MODEL_HASWELL_ULT && stepping < 1) ||
	    (model == CPUID_MODEL_CRYSTALWELL && stepping < 1)) {
		panic("Haswell pre-C0 steppings are not supported");
	}

	mca_MCE_present = (features & CPUID_FEATURE_MCE) != 0;
	mca_MCA_present = (features & CPUID_FEATURE_MCA) != 0;
	mca_family = family;

	/*
	 * If MCA, the number of banks etc is reported by the IA32_MCG_CAP MSR.
	 */
	if (mca_MCA_present) {
		ia32_mcg_cap.u64 = rdmsr64(IA32_MCG_CAP);
		mca_error_bank_count = ia32_mcg_cap.bits.count;
		mca_control_MSR_present = ia32_mcg_cap.bits.mcg_ctl_p;
		mca_cmci_present = ia32_mcg_cap.bits.mcg_ext_corr_err_p;
	}
}

void
mca_cpu_init(void)
{
	unsigned int    i;

	/*
	 * The first (boot) processor is responsible for discovering the
	 * machine check architecture present on this machine.
	 */
	if (!mca_initialized) {
		mca_get_availability();
		mca_initialized = TRUE;
		simple_lock_init(&mca_lock, 0);
	}

	if (mca_MCA_present) {
		/* Enable all MCA features */
		if (mca_control_MSR_present) {
			wrmsr64(IA32_MCG_CTL, IA32_MCG_CTL_ENABLE);
		}

		switch (mca_family) {
		case 0x06:
			/* Enable all but mc0 */
			for (i = 1; i < mca_error_bank_count; i++) {
				wrmsr64(IA32_MCi_CTL(i), 0xFFFFFFFFFFFFFFFFULL);
			}

			/* Clear all errors */
			for (i = 0; i < mca_error_bank_count; i++) {
				wrmsr64(IA32_MCi_STATUS(i), 0ULL);
			}
			break;
		case 0x0F:
			/* Enable all banks */
			for (i = 0; i < mca_error_bank_count; i++) {
				wrmsr64(IA32_MCi_CTL(i), 0xFFFFFFFFFFFFFFFFULL);
			}

			/* Clear all errors */
			for (i = 0; i < mca_error_bank_count; i++) {
				wrmsr64(IA32_MCi_STATUS(i), 0ULL);
			}
			break;
		}
	}

	/* Enable machine check exception handling if available */
	if (mca_MCE_present) {
		set_cr4(get_cr4() | CR4_MCE);
	}
}

boolean_t
mca_is_cmci_present(void)
{
	if (!mca_initialized) {
		mca_cpu_init();
	}
	return mca_cmci_present;
}

void
mca_cpu_alloc(cpu_data_t        *cdp)
{
	vm_size_t       mca_state_size;

	/*
	 * Allocate space for an array of error banks.
	 */
	mca_state_size = sizeof(mca_state_t) +
	    sizeof(mca_mci_bank_t) * mca_error_bank_count;
	cdp->cpu_mca_state = zalloc_permanent(mca_state_size, ZALIGN_PTR);
	if (cdp->cpu_mca_state == NULL) {
		printf("mca_cpu_alloc() failed for cpu %d\n", cdp->cpu_number);
		return;
	}

	/*
	 * If the boot processor is yet have its allocation made,
	 * do this now.
	 */
	if (cpu_datap(master_cpu)->cpu_mca_state == NULL) {
		mca_cpu_alloc(cpu_datap(master_cpu));
	}
}

static void
mca_save_state(mca_state_t *mca_state)
{
	mca_mci_bank_t  *bank;
	unsigned int    i;

	assert(!ml_get_interrupts_enabled() || get_preemption_level() > 0);

	if (mca_state == NULL) {
		return;
	}

	mca_state->mca_mcg_ctl = mca_control_MSR_present ?
	    rdmsr64(IA32_MCG_CTL) : 0ULL;
	mca_state->mca_mcg_status.u64 = rdmsr64(IA32_MCG_STATUS);

	bank = (mca_mci_bank_t *) &mca_state->mca_error_bank[0];
	for (i = 0; i < mca_error_bank_count; i++, bank++) {
		bank->mca_mci_ctl        = rdmsr64(IA32_MCi_CTL(i));
		bank->mca_mci_status.u64 = rdmsr64(IA32_MCi_STATUS(i));
		if (!bank->mca_mci_status.bits.val) {
			continue;
		}
		bank->mca_mci_misc = (bank->mca_mci_status.bits.miscv)?
		    rdmsr64(IA32_MCi_MISC(i)) : 0ULL;
		bank->mca_mci_addr = (bank->mca_mci_status.bits.addrv)?
		    rdmsr64(IA32_MCi_ADDR(i)) : 0ULL;
		mca_state->mca_is_valid = TRUE;
	}

	/*
	 * If we're the first thread with MCA state, point our package to it
	 * and don't care about races
	 */
	if (x86_package()->mca_state == NULL) {
		x86_package()->mca_state = mca_state;
	}

	mca_state->mca_is_saved = TRUE;
}

void
mca_check_save(void)
{
	if (mca_dump_state > CLEAR) {
		mca_save_state(current_cpu_datap()->cpu_mca_state);
	}
}

static void
mca_report_cpu_info(void)
{
	i386_cpu_info_t *infop = cpuid_info();

	paniclog_append_noflush(" family: %d model: %d stepping: %d microcode: %d\n",
	    infop->cpuid_family,
	    infop->cpuid_model,
	    infop->cpuid_stepping,
	    infop->cpuid_microcode_version);
	paniclog_append_noflush(" signature: 0x%x\n",
	    infop->cpuid_signature);
	paniclog_append_noflush(" %s\n",
	    infop->cpuid_brand_string);
}

static void
mca_dump_bank(mca_state_t *state, int i)
{
	mca_mci_bank_t          *bank;
	ia32_mci_status_t       status;

	bank = &state->mca_error_bank[i];
	status = bank->mca_mci_status;
	if (!status.bits.val) {
		return;
	}

	paniclog_append_noflush(" IA32_MC%d_STATUS(0x%x): 0x%016qx\n",
	    i, IA32_MCi_STATUS(i), status.u64);

	if (status.bits.addrv) {
		paniclog_append_noflush(" IA32_MC%d_ADDR(0x%x):   0x%016qx\n",
		    i, IA32_MCi_ADDR(i), bank->mca_mci_addr);
	}

	if (status.bits.miscv) {
		paniclog_append_noflush(" IA32_MC%d_MISC(0x%x):   0x%016qx\n",
		    i, IA32_MCi_MISC(i), bank->mca_mci_misc);
	}
}

static void
mca_cpu_dump_error_banks(mca_state_t *state)
{
	unsigned int            i;

	if (!state->mca_is_valid) {
		return;
	}

	for (i = 0; i < mca_error_bank_count; i++) {
		mca_dump_bank(state, i);
	}
}

void
mca_dump(void)
{
	mca_state_t     *mca_state = current_cpu_datap()->cpu_mca_state;
	uint64_t        deadline;
	unsigned int    i = 0;

	/*
	 * Capture local MCA registers to per-cpu data.
	 */
	mca_save_state(mca_state);

	/*
	 * Serialize: the first caller controls dumping MCA registers,
	 * other threads spin meantime.
	 */
	simple_lock(&mca_lock, LCK_GRP_NULL);
	if (mca_dump_state > CLEAR) {
		simple_unlock(&mca_lock);
		while (mca_dump_state == DUMPING) {
			cpu_pause();
		}
		return;
	}
	mca_dump_state = DUMPING;
	simple_unlock(&mca_lock);

	/*
	 * Wait for all other hardware threads to save their state.
	 * Or timeout.
	 */
	deadline = mach_absolute_time() + LockTimeOut;
	while (mach_absolute_time() < deadline && i < real_ncpus) {
		if (!cpu_datap(i)->cpu_mca_state->mca_is_saved) {
			cpu_pause();
			continue;
		}
		i += 1;
	}

	/*
	 * Report machine-check capabilities:
	 */
	paniclog_append_noflush("Machine-check capabilities: 0x%016qx\n", ia32_mcg_cap.u64);

	mca_report_cpu_info();

	paniclog_append_noflush(" %d error-reporting banks\n", mca_error_bank_count);

	/*
	 * Dump all processor state:
	 */
	for (i = 0; i < real_ncpus; i++) {
		mca_state_t             *mcsp = cpu_datap(i)->cpu_mca_state;
		ia32_mcg_status_t       status;

		if (mcsp == NULL ||
		    mcsp->mca_is_saved == FALSE ||
		    mcsp->mca_mcg_status.u64 == 0 ||
		    !mcsp->mca_is_valid) {
			continue;
		}
		status = mcsp->mca_mcg_status;
		paniclog_append_noflush("Processor %d: IA32_MCG_STATUS: 0x%016qx\n",
		    i, status.u64);
		mca_cpu_dump_error_banks(mcsp);
	}

	/* Update state to release any other threads. */
	mca_dump_state = DUMPED;
}


#if DEVELOPMENT || DEBUG
extern void mca_exception_panic(void);
extern void lapic_trigger_MC(void);
void
mca_exception_panic(void)
{
	lapic_trigger_MC();
}
#endif
Commit	Line	Data
0c530ab8	1	/*
316670eb	2	* Copyright (c) 2007-2011 Apple Inc. All rights reserved.
0c530ab8 A	3	*
0c530ab8 A	4	* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
0a7de745	5	*
0c530ab8 A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. The rights granted to you under the License
	10	* may not be used to create, or enable the creation or redistribution of,
	11	* unlawful or unlicensed copies of an Apple operating system, or to
	12	* circumvent, violate, or enable the circumvention or violation of, any
	13	* terms of an Apple operating system software license agreement.
0a7de745	14	*
0c530ab8 A	15	* Please obtain a copy of the License at
0c530ab8 A	16	* http://www.opensource.apple.com/apsl/ and read it before using this file.
0a7de745	17	*
0c530ab8 A	18	* The Original Code and all software distributed under the License are
	19	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
	20	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
	21	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	23	* Please see the License for the specific language governing rights and
	24	* limitations under the License.
0a7de745	25	*
0c530ab8 A	26	* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
	27	*/
	28
f427ee49	29	#include <kern/zalloc.h>
593a1d5f	30	#include <mach/mach_time.h>
0c530ab8 A	31	#include <i386/cpu_data.h>
0c530ab8 A	32	#include <i386/cpuid.h>
593a1d5f A	33	#include <i386/cpu_topology.h>
593a1d5f A	34	#include <i386/cpu_threads.h>
15129b1c	35	#include <i386/lapic.h>
593a1d5f	36	#include <i386/machine_cpu.h>
0c530ab8 A	37	#include <i386/machine_check.h>
	38	#include <i386/proc_reg.h>
	39
316670eb A	40	/*
	41	* At the time of the machine-check exception, all hardware-threads panic.
	42	* Each thread saves the state of its MCA registers to its per-cpu data area.
	43	*
	44	* State reporting is serialized so one thread dumps all valid state for all
	45	* threads to the panic log. This may entail spinning waiting for other
	46	* threads to complete saving state to memory. A timeout applies to this wait
	47	* -- in particular, a 3-strikes timeout may prevent a thread from taking
	48	* part is the affair.
	49	*/
	50
0a7de745	51	#define IF(bool, str) ((bool) ? (str) : "")
0c530ab8	52
0a7de745 A	53	static boolean_t mca_initialized = FALSE;
	54	static boolean_t mca_MCE_present = FALSE;
	55	static boolean_t mca_MCA_present = FALSE;
	56	static uint32_t mca_family = 0;
	57	static unsigned int mca_error_bank_count = 0;
	58	static boolean_t mca_control_MSR_present = FALSE;
	59	static boolean_t mca_cmci_present = FALSE;
	60	static ia32_mcg_cap_t ia32_mcg_cap;
2d21ac55 A	61	decl_simple_lock_data(static, mca_lock);
	62
	63	typedef struct {
0a7de745 A	64	ia32_mci_ctl_t mca_mci_ctl;
	65	ia32_mci_status_t mca_mci_status;
	66	ia32_mci_misc_t mca_mci_misc;
	67	ia32_mci_addr_t mca_mci_addr;
2d21ac55 A	68	} mca_mci_bank_t;
	69
	70	typedef struct mca_state {
0a7de745 A	71	boolean_t mca_is_saved;
	72	boolean_t mca_is_valid; /* some state is valid */
	73	ia32_mcg_ctl_t mca_mcg_ctl;
	74	ia32_mcg_status_t mca_mcg_status;
	75	mca_mci_bank_t mca_error_bank[0];
2d21ac55	76	} mca_state_t;
0c530ab8	77
593a1d5f A	78	typedef enum {
	79	CLEAR,
	80	DUMPING,
	81	DUMPED
	82	} mca_dump_state_t;
	83	static volatile mca_dump_state_t mca_dump_state = CLEAR;
	84
0c530ab8 A	85	static void
	86	mca_get_availability(void)
	87	{
0a7de745 A	88	uint64_t features = cpuid_info()->cpuid_features;
	89	uint32_t family = cpuid_info()->cpuid_family;
	90	uint32_t model = cpuid_info()->cpuid_model;
	91	uint32_t stepping = cpuid_info()->cpuid_stepping;
0c530ab8	92
0a7de745	93	if ((model == CPUID_MODEL_HASWELL && stepping < 3) \|\|
bd504ef0	94	(model == CPUID_MODEL_HASWELL_ULT && stepping < 1) \|\|
0a7de745	95	(model == CPUID_MODEL_CRYSTALWELL && stepping < 1)) {
bd504ef0	96	panic("Haswell pre-C0 steppings are not supported");
0a7de745	97	}
bd504ef0	98
39236c6e A	99	mca_MCE_present = (features & CPUID_FEATURE_MCE) != 0;
	100	mca_MCA_present = (features & CPUID_FEATURE_MCA) != 0;
	101	mca_family = family;
	102
0c530ab8 A	103	/*
	104	* If MCA, the number of banks etc is reported by the IA32_MCG_CAP MSR.
	105	*/
	106	if (mca_MCA_present) {
	107	ia32_mcg_cap.u64 = rdmsr64(IA32_MCG_CAP);
	108	mca_error_bank_count = ia32_mcg_cap.bits.count;
	109	mca_control_MSR_present = ia32_mcg_cap.bits.mcg_ctl_p;
c910b4d9	110	mca_cmci_present = ia32_mcg_cap.bits.mcg_ext_corr_err_p;
0c530ab8 A	111	}
	112	}
	113
	114	void
	115	mca_cpu_init(void)
	116	{
0a7de745	117	unsigned int i;
0c530ab8 A	118
	119	/*
	120	* The first (boot) processor is responsible for discovering the
	121	* machine check architecture present on this machine.
	122	*/
	123	if (!mca_initialized) {
	124	mca_get_availability();
	125	mca_initialized = TRUE;
2d21ac55	126	simple_lock_init(&mca_lock, 0);
0c530ab8 A	127	}
	128
	129	if (mca_MCA_present) {
0c530ab8	130	/* Enable all MCA features */
0a7de745	131	if (mca_control_MSR_present) {
0c530ab8	132	wrmsr64(IA32_MCG_CTL, IA32_MCG_CTL_ENABLE);
0a7de745 A	133	}
0a7de745 A	134
2d21ac55	135	switch (mca_family) {
0c530ab8 A	136	case 0x06:
0c530ab8 A	137	/* Enable all but mc0 */
0a7de745 A	138	for (i = 1; i < mca_error_bank_count; i++) {
	139	wrmsr64(IA32_MCi_CTL(i), 0xFFFFFFFFFFFFFFFFULL);
	140	}
	141
0c530ab8	142	/* Clear all errors */
0a7de745	143	for (i = 0; i < mca_error_bank_count; i++) {
0c530ab8	144	wrmsr64(IA32_MCi_STATUS(i), 0ULL);
0a7de745	145	}
0c530ab8 A	146	break;
	147	case 0x0F:
	148	/* Enable all banks */
0a7de745 A	149	for (i = 0; i < mca_error_bank_count; i++) {
	150	wrmsr64(IA32_MCi_CTL(i), 0xFFFFFFFFFFFFFFFFULL);
	151	}
	152
0c530ab8	153	/* Clear all errors */
0a7de745	154	for (i = 0; i < mca_error_bank_count; i++) {
0c530ab8	155	wrmsr64(IA32_MCi_STATUS(i), 0ULL);
0a7de745	156	}
0c530ab8 A	157	break;
	158	}
	159	}
	160
	161	/* Enable machine check exception handling if available */
	162	if (mca_MCE_present) {
0a7de745	163	set_cr4(get_cr4() \| CR4_MCE);
0c530ab8 A	164	}
	165	}
	166
c910b4d9 A	167	boolean_t
	168	mca_is_cmci_present(void)
	169	{
0a7de745	170	if (!mca_initialized) {
c910b4d9	171	mca_cpu_init();
0a7de745	172	}
c910b4d9 A	173	return mca_cmci_present;
	174	}
	175
2d21ac55	176	void
0a7de745	177	mca_cpu_alloc(cpu_data_t *cdp)
2d21ac55	178	{
0a7de745	179	vm_size_t mca_state_size;
2d21ac55 A	180
	181	/*
	182	* Allocate space for an array of error banks.
	183	*/
	184	mca_state_size = sizeof(mca_state_t) +
0a7de745	185	sizeof(mca_mci_bank_t) * mca_error_bank_count;
f427ee49	186	cdp->cpu_mca_state = zalloc_permanent(mca_state_size, ZALIGN_PTR);
2d21ac55 A	187	if (cdp->cpu_mca_state == NULL) {
	188	printf("mca_cpu_alloc() failed for cpu %d\n", cdp->cpu_number);
	189	return;
	190	}
2d21ac55 A	191
	192	/*
	193	* If the boot processor is yet have its allocation made,
	194	* do this now.
	195	*/
0a7de745	196	if (cpu_datap(master_cpu)->cpu_mca_state == NULL) {
2d21ac55	197	mca_cpu_alloc(cpu_datap(master_cpu));
0a7de745	198	}
2d21ac55 A	199	}
	200
	201	static void
593a1d5f	202	mca_save_state(mca_state_t *mca_state)
2d21ac55	203	{
2d21ac55	204	mca_mci_bank_t *bank;
0a7de745	205	unsigned int i;
2d21ac55 A	206
	207	assert(!ml_get_interrupts_enabled() \|\| get_preemption_level() > 0);
	208
0a7de745	209	if (mca_state == NULL) {
2d21ac55	210	return;
0a7de745	211	}
2d21ac55 A	212
2d21ac55 A	213	mca_state->mca_mcg_ctl = mca_control_MSR_present ?
0a7de745	214	rdmsr64(IA32_MCG_CTL) : 0ULL;
2d21ac55 A	215	mca_state->mca_mcg_status.u64 = rdmsr64(IA32_MCG_STATUS);
2d21ac55 A	216
0a7de745	217	bank = (mca_mci_bank_t *) &mca_state->mca_error_bank[0];
2d21ac55	218	for (i = 0; i < mca_error_bank_count; i++, bank++) {
0a7de745 A	219	bank->mca_mci_ctl = rdmsr64(IA32_MCi_CTL(i));
	220	bank->mca_mci_status.u64 = rdmsr64(IA32_MCi_STATUS(i));
	221	if (!bank->mca_mci_status.bits.val) {
2d21ac55	222	continue;
0a7de745	223	}
2d21ac55	224	bank->mca_mci_misc = (bank->mca_mci_status.bits.miscv)?
0a7de745	225	rdmsr64(IA32_MCi_MISC(i)) : 0ULL;
2d21ac55	226	bank->mca_mci_addr = (bank->mca_mci_status.bits.addrv)?
0a7de745	227	rdmsr64(IA32_MCi_ADDR(i)) : 0ULL;
316670eb	228	mca_state->mca_is_valid = TRUE;
0a7de745	229	}
c910b4d9 A	230
	231	/*
	232	* If we're the first thread with MCA state, point our package to it
	233	* and don't care about races
	234	*/
0a7de745	235	if (x86_package()->mca_state == NULL) {
15129b1c	236	x86_package()->mca_state = mca_state;
0a7de745	237	}
316670eb A	238
316670eb A	239	mca_state->mca_is_saved = TRUE;
2d21ac55 A	240	}
	241
	242	void
	243	mca_check_save(void)
	244	{
0a7de745	245	if (mca_dump_state > CLEAR) {
593a1d5f	246	mca_save_state(current_cpu_datap()->cpu_mca_state);
0a7de745	247	}
2d21ac55 A	248	}
2d21ac55 A	249
cf7d32b8 A	250	static void
	251	mca_report_cpu_info(void)
	252	{
cf7d32b8 A	253	i386_cpu_info_t *infop = cpuid_info();
cf7d32b8 A	254
5ba3f43e	255	paniclog_append_noflush(" family: %d model: %d stepping: %d microcode: %d\n",
0a7de745 A	256	infop->cpuid_family,
	257	infop->cpuid_model,
	258	infop->cpuid_stepping,
	259	infop->cpuid_microcode_version);
5ba3f43e	260	paniclog_append_noflush(" signature: 0x%x\n",
0a7de745	261	infop->cpuid_signature);
5ba3f43e	262	paniclog_append_noflush(" %s\n",
0a7de745	263	infop->cpuid_brand_string);
c910b4d9 A	264	}
c910b4d9 A	265
0c530ab8	266	static void
593a1d5f	267	mca_dump_bank(mca_state_t *state, int i)
0c530ab8	268	{
0a7de745 A	269	mca_mci_bank_t *bank;
0a7de745 A	270	ia32_mci_status_t status;
0c530ab8	271
593a1d5f A	272	bank = &state->mca_error_bank[i];
593a1d5f A	273	status = bank->mca_mci_status;
0a7de745	274	if (!status.bits.val) {
593a1d5f	275	return;
0a7de745	276	}
593a1d5f	277
5ba3f43e	278	paniclog_append_noflush(" IA32_MC%d_STATUS(0x%x): 0x%016qx\n",
0a7de745	279	i, IA32_MCi_STATUS(i), status.u64);
15129b1c	280
0a7de745	281	if (status.bits.addrv) {
5ba3f43e	282	paniclog_append_noflush(" IA32_MC%d_ADDR(0x%x): 0x%016qx\n",
0a7de745 A	283	i, IA32_MCi_ADDR(i), bank->mca_mci_addr);
0a7de745 A	284	}
15129b1c	285
0a7de745	286	if (status.bits.miscv) {
5ba3f43e	287	paniclog_append_noflush(" IA32_MC%d_MISC(0x%x): 0x%016qx\n",
0a7de745 A	288	i, IA32_MCi_MISC(i), bank->mca_mci_misc);
0a7de745 A	289	}
593a1d5f A	290	}
	291
	292	static void
316670eb	293	mca_cpu_dump_error_banks(mca_state_t *state)
593a1d5f	294	{
0a7de745	295	unsigned int i;
593a1d5f	296
0a7de745	297	if (!state->mca_is_valid) {
316670eb	298	return;
0a7de745	299	}
316670eb	300
0a7de745	301	for (i = 0; i < mca_error_bank_count; i++) {
593a1d5f	302	mca_dump_bank(state, i);
0c530ab8 A	303	}
	304	}
	305
	306	void
	307	mca_dump(void)
	308	{
0a7de745 A	309	mca_state_t *mca_state = current_cpu_datap()->cpu_mca_state;
	310	uint64_t deadline;
	311	unsigned int i = 0;
0c530ab8	312
593a1d5f A	313	/*
	314	* Capture local MCA registers to per-cpu data.
	315	*/
	316	mca_save_state(mca_state);
2d21ac55	317
4a3eedf9	318	/*
316670eb	319	* Serialize: the first caller controls dumping MCA registers,
593a1d5f	320	* other threads spin meantime.
4a3eedf9	321	*/
0a7de745	322	simple_lock(&mca_lock, LCK_GRP_NULL);
593a1d5f	323	if (mca_dump_state > CLEAR) {
4a3eedf9	324	simple_unlock(&mca_lock);
0a7de745	325	while (mca_dump_state == DUMPING) {
593a1d5f	326	cpu_pause();
0a7de745	327	}
4a3eedf9 A	328	return;
4a3eedf9 A	329	}
593a1d5f A	330	mca_dump_state = DUMPING;
593a1d5f A	331	simple_unlock(&mca_lock);
2d21ac55	332
316670eb A	333	/*
	334	* Wait for all other hardware threads to save their state.
	335	* Or timeout.
	336	*/
	337	deadline = mach_absolute_time() + LockTimeOut;
	338	while (mach_absolute_time() < deadline && i < real_ncpus) {
	339	if (!cpu_datap(i)->cpu_mca_state->mca_is_saved) {
	340	cpu_pause();
	341	continue;
	342	}
	343	i += 1;
	344	}
	345
0c530ab8 A	346	/*
	347	* Report machine-check capabilities:
	348	*/
5ba3f43e	349	paniclog_append_noflush("Machine-check capabilities: 0x%016qx\n", ia32_mcg_cap.u64);
cf7d32b8 A	350
	351	mca_report_cpu_info();
	352
5ba3f43e	353	paniclog_append_noflush(" %d error-reporting banks\n", mca_error_bank_count);
0a7de745	354
0c530ab8	355	/*
316670eb	356	* Dump all processor state:
0c530ab8	357	*/
316670eb	358	for (i = 0; i < real_ncpus; i++) {
0a7de745 A	359	mca_state_t *mcsp = cpu_datap(i)->cpu_mca_state;
0a7de745 A	360	ia32_mcg_status_t status;
316670eb	361
316670eb A	362	if (mcsp == NULL \|\|
316670eb A	363	mcsp->mca_is_saved == FALSE \|\|
15129b1c A	364	mcsp->mca_mcg_status.u64 == 0 \|\|
15129b1c A	365	!mcsp->mca_is_valid) {
316670eb A	366	continue;
	367	}
	368	status = mcsp->mca_mcg_status;
5ba3f43e	369	paniclog_append_noflush("Processor %d: IA32_MCG_STATUS: 0x%016qx\n",
0a7de745	370	i, status.u64);
316670eb A	371	mca_cpu_dump_error_banks(mcsp);
316670eb A	372	}
0c530ab8	373
593a1d5f A	374	/* Update state to release any other threads. */
593a1d5f A	375	mca_dump_state = DUMPED;
0c530ab8	376	}
316670eb A	377
316670eb A	378
39037602	379	#if DEVELOPMENT \|\| DEBUG
316670eb	380	extern void mca_exception_panic(void);
15129b1c	381	extern void lapic_trigger_MC(void);
0a7de745 A	382	void
0a7de745 A	383	mca_exception_panic(void)
316670eb	384	{
15129b1c	385	lapic_trigger_MC();
316670eb	386	}
39037602	387	#endif