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1c79356b | 1 | /* |
e2fac8b1 | 2 | * Copyright (c) 2000-2009 Apple Inc. All rights reserved. |
1c79356b | 3 | * |
2d21ac55 | 4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ |
0a7de745 | 5 | * |
2d21ac55 A |
6 | * This file contains Original Code and/or Modifications of Original Code |
7 | * as defined in and that are subject to the Apple Public Source License | |
8 | * Version 2.0 (the 'License'). You may not use this file except in | |
9 | * compliance with the License. The rights granted to you under the License | |
10 | * may not be used to create, or enable the creation or redistribution of, | |
11 | * unlawful or unlicensed copies of an Apple operating system, or to | |
12 | * circumvent, violate, or enable the circumvention or violation of, any | |
13 | * terms of an Apple operating system software license agreement. | |
0a7de745 | 14 | * |
2d21ac55 A |
15 | * Please obtain a copy of the License at |
16 | * http://www.opensource.apple.com/apsl/ and read it before using this file. | |
0a7de745 | 17 | * |
2d21ac55 A |
18 | * The Original Code and all software distributed under the License are |
19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
8f6c56a5 A |
20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
2d21ac55 A |
22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
23 | * Please see the License for the specific language governing rights and | |
24 | * limitations under the License. | |
0a7de745 | 25 | * |
2d21ac55 | 26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ |
1c79356b A |
27 | */ |
28 | /* | |
29 | * File: i386/cpu.c | |
30 | * | |
31 | * cpu specific routines | |
32 | */ | |
33 | ||
1c79356b | 34 | #include <kern/misc_protos.h> |
0a7de745 | 35 | #include <kern/lock_group.h> |
91447636 | 36 | #include <kern/machine.h> |
1c79356b | 37 | #include <mach/processor_info.h> |
b0d623f7 | 38 | #include <i386/pmap.h> |
55e303ae A |
39 | #include <i386/machine_cpu.h> |
40 | #include <i386/machine_routines.h> | |
91447636 A |
41 | #include <i386/misc_protos.h> |
42 | #include <i386/cpu_threads.h> | |
6d2010ae | 43 | #include <i386/rtclock_protos.h> |
b0d623f7 A |
44 | #include <i386/cpuid.h> |
45 | #if CONFIG_VMX | |
46 | #include <i386/vmx/vmx_cpu.h> | |
47 | #endif | |
91447636 | 48 | #include <vm/vm_kern.h> |
6d2010ae | 49 | #include <kern/timer_call.h> |
1c79356b | 50 | |
0a7de745 A |
51 | const char *processor_to_datastring(const char *prefix, processor_t target_processor); |
52 | ||
53 | struct processor processor_master; | |
9bccf70c | 54 | |
1c79356b A |
55 | /*ARGSUSED*/ |
56 | kern_return_t | |
57 | cpu_control( | |
0a7de745 A |
58 | int slot_num, |
59 | processor_info_t info, | |
60 | unsigned int count) | |
1c79356b | 61 | { |
2d21ac55 | 62 | printf("cpu_control(%d,%p,%d) not implemented\n", |
0a7de745 A |
63 | slot_num, info, count); |
64 | return KERN_FAILURE; | |
1c79356b A |
65 | } |
66 | ||
67 | /*ARGSUSED*/ | |
68 | kern_return_t | |
69 | cpu_info_count( | |
0a7de745 A |
70 | __unused processor_flavor_t flavor, |
71 | unsigned int *count) | |
1c79356b A |
72 | { |
73 | *count = 0; | |
0a7de745 | 74 | return KERN_FAILURE; |
1c79356b A |
75 | } |
76 | ||
77 | /*ARGSUSED*/ | |
78 | kern_return_t | |
79 | cpu_info( | |
0a7de745 A |
80 | processor_flavor_t flavor, |
81 | int slot_num, | |
82 | processor_info_t info, | |
83 | unsigned int *count) | |
1c79356b | 84 | { |
2d21ac55 | 85 | printf("cpu_info(%d,%d,%p,%p) not implemented\n", |
0a7de745 A |
86 | flavor, slot_num, info, count); |
87 | return KERN_FAILURE; | |
1c79356b A |
88 | } |
89 | ||
90 | void | |
91447636 | 91 | cpu_sleep(void) |
1c79356b | 92 | { |
0a7de745 | 93 | cpu_data_t *cdp = current_cpu_datap(); |
55e303ae | 94 | |
cb323159 | 95 | /* This calls IOCPURunPlatformQuiesceActions when sleeping the boot cpu */ |
2d21ac55 | 96 | PE_cpu_machine_quiesce(cdp->cpu_id); |
55e303ae | 97 | |
91447636 | 98 | cpu_thread_halt(); |
55e303ae A |
99 | } |
100 | ||
91447636 A |
101 | void |
102 | cpu_init(void) | |
55e303ae | 103 | { |
0a7de745 | 104 | cpu_data_t *cdp = current_cpu_datap(); |
55e303ae | 105 | |
39236c6e | 106 | timer_call_queue_init(&cdp->rtclock_timer.queue); |
6d2010ae A |
107 | cdp->rtclock_timer.deadline = EndOfAllTime; |
108 | ||
0c530ab8 A |
109 | cdp->cpu_type = cpuid_cputype(); |
110 | cdp->cpu_subtype = cpuid_cpusubtype(); | |
111 | ||
2d21ac55 | 112 | i386_activate_cpu(); |
55e303ae A |
113 | } |
114 | ||
115 | kern_return_t | |
116 | cpu_start( | |
117 | int cpu) | |
118 | { | |
0a7de745 | 119 | kern_return_t ret; |
55e303ae A |
120 | |
121 | if (cpu == cpu_number()) { | |
91447636 | 122 | cpu_machine_init(); |
55e303ae | 123 | return KERN_SUCCESS; |
593a1d5f A |
124 | } |
125 | ||
126 | /* | |
127 | * Try to bring the CPU back online without a reset. | |
128 | * If the fast restart doesn't succeed, fall back to | |
129 | * the slow way. | |
130 | */ | |
131 | ret = intel_startCPU_fast(cpu); | |
132 | if (ret != KERN_SUCCESS) { | |
55e303ae A |
133 | /* |
134 | * Should call out through PE. | |
135 | * But take the shortcut here. | |
136 | */ | |
137 | ret = intel_startCPU(cpu); | |
55e303ae | 138 | } |
593a1d5f | 139 | |
0a7de745 | 140 | if (ret != KERN_SUCCESS) { |
593a1d5f | 141 | kprintf("cpu: cpu_start(%d) returning failure!\n", cpu); |
0a7de745 | 142 | } |
593a1d5f | 143 | |
0a7de745 | 144 | return ret; |
55e303ae A |
145 | } |
146 | ||
91447636 A |
147 | void |
148 | cpu_exit_wait( | |
2d21ac55 | 149 | int cpu) |
91447636 | 150 | { |
0a7de745 A |
151 | cpu_data_t *cdp = cpu_datap(cpu); |
152 | boolean_t intrs_enabled; | |
153 | uint64_t tsc_timeout; | |
2d21ac55 | 154 | |
e2fac8b1 A |
155 | /* |
156 | * Wait until the CPU indicates that it has stopped. | |
39236c6e A |
157 | * Disable interrupts while the topo lock is held -- arguably |
158 | * this should always be done but in this instance it can lead to | |
159 | * a timeout if long-running interrupt were to occur here. | |
e2fac8b1 | 160 | */ |
39236c6e | 161 | intrs_enabled = ml_set_interrupts_enabled(FALSE); |
5ba3f43e | 162 | mp_safe_spin_lock(&x86_topo_lock); |
39236c6e A |
163 | /* Set a generous timeout of several seconds (in TSC ticks) */ |
164 | tsc_timeout = rdtsc64() + (10ULL * 1000 * 1000 * 1000); | |
593a1d5f | 165 | while ((cdp->lcpu.state != LCPU_HALT) |
0a7de745 A |
166 | && (cdp->lcpu.state != LCPU_OFF) |
167 | && !cdp->lcpu.stopped) { | |
168 | simple_unlock(&x86_topo_lock); | |
169 | ml_set_interrupts_enabled(intrs_enabled); | |
170 | cpu_pause(); | |
171 | if (rdtsc64() > tsc_timeout) { | |
172 | panic("cpu_exit_wait(%d) timeout", cpu); | |
173 | } | |
174 | ml_set_interrupts_enabled(FALSE); | |
175 | mp_safe_spin_lock(&x86_topo_lock); | |
2d21ac55 A |
176 | } |
177 | simple_unlock(&x86_topo_lock); | |
39236c6e | 178 | ml_set_interrupts_enabled(intrs_enabled); |
91447636 A |
179 | } |
180 | ||
55e303ae A |
181 | void |
182 | cpu_machine_init( | |
183 | void) | |
184 | { | |
0a7de745 | 185 | cpu_data_t *cdp = current_cpu_datap(); |
55e303ae | 186 | |
0c530ab8 A |
187 | PE_cpu_machine_init(cdp->cpu_id, !cdp->cpu_boot_complete); |
188 | cdp->cpu_boot_complete = TRUE; | |
189 | cdp->cpu_running = TRUE; | |
55e303ae | 190 | ml_init_interrupt(); |
2d21ac55 | 191 | |
b0d623f7 | 192 | #if CONFIG_VMX |
fe8ab488 A |
193 | /* initialize VMX for every CPU */ |
194 | vmx_cpu_init(); | |
b0d623f7 | 195 | #endif |
55e303ae A |
196 | } |
197 | ||
91447636 A |
198 | processor_t |
199 | current_processor(void) | |
200 | { | |
201 | return current_cpu_datap()->cpu_processor; | |
202 | } | |
203 | ||
204 | processor_t | |
205 | cpu_to_processor( | |
0a7de745 | 206 | int cpu) |
91447636 A |
207 | { |
208 | return cpu_datap(cpu)->cpu_processor; | |
209 | } | |
210 | ||
211 | ast_t * | |
212 | ast_pending(void) | |
213 | { | |
0a7de745 | 214 | return ¤t_cpu_datap()->cpu_pending_ast; |
91447636 A |
215 | } |
216 | ||
217 | cpu_type_t | |
218 | slot_type( | |
0a7de745 | 219 | int slot_num) |
91447636 | 220 | { |
0a7de745 | 221 | return cpu_datap(slot_num)->cpu_type; |
91447636 A |
222 | } |
223 | ||
224 | cpu_subtype_t | |
225 | slot_subtype( | |
0a7de745 | 226 | int slot_num) |
91447636 | 227 | { |
0a7de745 | 228 | return cpu_datap(slot_num)->cpu_subtype; |
91447636 A |
229 | } |
230 | ||
231 | cpu_threadtype_t | |
232 | slot_threadtype( | |
0a7de745 | 233 | int slot_num) |
91447636 | 234 | { |
0a7de745 | 235 | return cpu_datap(slot_num)->cpu_threadtype; |
91447636 A |
236 | } |
237 | ||
238 | cpu_type_t | |
239 | cpu_type(void) | |
240 | { | |
0a7de745 | 241 | return current_cpu_datap()->cpu_type; |
91447636 A |
242 | } |
243 | ||
244 | cpu_subtype_t | |
245 | cpu_subtype(void) | |
246 | { | |
0a7de745 | 247 | return current_cpu_datap()->cpu_subtype; |
91447636 A |
248 | } |
249 | ||
250 | cpu_threadtype_t | |
251 | cpu_threadtype(void) | |
252 | { | |
0a7de745 A |
253 | return current_cpu_datap()->cpu_threadtype; |
254 | } | |
255 | ||
256 | const char * | |
257 | processor_to_datastring(const char *prefix, processor_t target_processor) | |
258 | { | |
259 | static char printBuf[256]; | |
260 | uint32_t cpu_num = target_processor->cpu_id; | |
261 | ||
262 | cpu_data_t *cpup = cpu_datap(cpu_num); | |
263 | thread_t act; | |
264 | ||
265 | act = ml_validate_nofault((vm_offset_t)cpup->cpu_active_thread, | |
266 | sizeof(struct thread)) ? cpup->cpu_active_thread : NULL; | |
267 | ||
268 | snprintf(printBuf, sizeof(printBuf), | |
269 | "%s: tCPU %u (%d) [tid=0x%llx(bp=%d sp=%d) s=0x%x ps=0x%x cpa=0x%x spa=0x%llx pl=%d il=%d r=%d]", | |
270 | prefix, | |
271 | cpu_num, | |
272 | target_processor->state, | |
273 | act ? act->thread_id : ~0ULL, | |
274 | act ? act->base_pri : -1, | |
275 | act ? act->sched_pri : -1, | |
276 | cpup->cpu_signals, | |
277 | cpup->cpu_prior_signals, | |
278 | cpup->cpu_pending_ast, | |
279 | target_processor->processor_set->pending_AST_URGENT_cpu_mask, | |
280 | cpup->cpu_preemption_level, | |
281 | cpup->cpu_interrupt_level, | |
282 | cpup->cpu_running); | |
283 | ||
284 | return (const char *)&printBuf[0]; | |
91447636 | 285 | } |