[apple/xnu.git] / osfmk / i386 / perfmon.h

/*
 * Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
 *
 * @APPLE_LICENSE_HEADER_START@
 * 
 * This file contains Original Code and/or Modifications of Original Code
 * as defined in and that are subject to the Apple Public Source License
 * Version 2.0 (the 'License'). You may not use this file except in
 * compliance with the License. Please obtain a copy of the License at
 * http://www.opensource.apple.com/apsl/ and read it before using this
 * file.
 * 
 * The Original Code and all software distributed under the License are
 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
 * Please see the License for the specific language governing rights and
 * limitations under the License.
 * 
 * @APPLE_LICENSE_HEADER_END@
 */
#ifndef _I386_PERFMON_H_
#define _I386_PERFMON_H_

#include <i386/proc_reg.h>

/*
 * Handy macros for bit/bitfield definition and manipulations:
 */
#define bit(n)			(1ULL << (n))
#define field(n,m)		((bit((m)+1)-1) & ~(bit(n)-1))
#define field_nbit(fld)		(ffs(fld)-1)
#define field_select(fld,x)	((x) & (fld))
#define field_clear(fld,x)	((x) & ~(fld))
#define field_unshift(fld,x)	((x) >> field_nbit(fld))
#define field_shift(fld,x)	((x) << field_nbit(fld))
#define field_get(fld,x)	(field_unshift(fld,field_select(fld,x)))
#define field_set(fld,x,val)	(field_clear(fld,x) | field_shift(fld,val))

#define PERFMON_AVAILABLE	bit(7)
#define BTS_UNAVAILABLE		bit(11)

static inline boolean_t
pmc_is_available(void)
{
	uint32_t	lo;
	uint32_t	hi;
	int		ret;

	ret = rdmsr_carefully(MSR_IA32_MISC_ENABLE, &lo, &hi);

	return (ret == 0) && ((lo & PERFMON_AVAILABLE) != 0);
}

/*
 * Counter layout:
 */
#define	PMC_COUNTER_COUNTER		field(0,39)
#define	PMC_COUNTER_RESERVED		field(40,64)
#define PMC_COUNTER_MAX			((uint64_t) PMC_COUNTER_COUNTER)
typedef struct {
	uint64_t	counter		: 40;
	uint64_t	reserved	: 24;
} pmc_counter_t;
#define	PMC_COUNTER_ZERO { 0, 0 }


/*
 * There are 2 basic flavors of PMCsL: P6 and P4/Xeon:
 */
typedef enum {
	pmc_none,
	pmc_P6,
	pmc_P4_Xeon,
	pmc_unknown
} pmc_machine_t;

/*
 * P6 MSRs...
 */
#define	MSR_P6_COUNTER_ADDR(n)	(0x0c1 + (n))
#define	MSR_P6_PES_ADDR(n)	(0x186 + (n))

typedef struct {
	uint64_t	event_select	: 8;
	uint64_t	umask		: 8;
	uint64_t	usr		: 1;
	uint64_t	os		: 1;
	uint64_t	e		: 1;
	uint64_t	pc		: 1;
	uint64_t	apic_int	: 1;
	uint64_t	reserved1	: 1;
	uint64_t	en		: 1;
	uint64_t	inv		: 1;
	uint64_t	cmask		: 8;
} pmc_evtsel_t;
#define PMC_EVTSEL_ZERO	((pmc_evtsel_t){ 0,0,0,0,0,0,0,0,0,0,0 }) 

#define	MSR_P6_PERFCTR0	0
#define	MSR_P6_PERFCTR1	1

/*
 * P4/Xeon MSRs...
 */
#define	MSR_COUNTER_ADDR(n)	(0x300 + (n))
#define	MSR_CCCR_ADDR(n)	(0x360 + (n))

typedef enum {
	MSR_BPU_COUNTER0	= 0,
	MSR_BPU_COUNTER1	= 1,
		#define MSR_BSU_ESCR0	7
		#define MSR_FSB_ESCR0	6
		#define MSR_MOB_ESCR0	2
		#define MSR_PMH_ESCR0	4
		#define MSR_BPU_ESCR0	0
		#define MSR_IS_ESCR0	1
		#define MSR_ITLB_ESCR0	3
		#define MSR_IX_ESCR0	5
	MSR_BPU_COUNTER2	= 2,
	MSR_BPU_COUNTER3	= 3,
		#define MSR_BSU_ESCR1	7
		#define MSR_FSB_ESCR1	6
		#define MSR_MOB_ESCR1	2
		#define MSR_PMH_ESCR1	4
		#define MSR_BPU_ESCR1	0
		#define MSR_IS_ESCR1	1
		#define MSR_ITLB_ESCR1	3
		#define MSR_IX_ESCR1	5
	MSR_MS_COUNTER0		= 4,
	MSR_MS_COUNTER1		= 5,
		#define MSR_MS_ESCR0	0
		#define MSR_TBPU_ESCR0	2
		#define MSR_TC_ESCR0	1
	MSR_MS_COUNTER2		= 6,
	MSR_MS_COUNTER3		= 7,
		#define MSR_MS_ESCR1	0
		#define MSR_TBPU_ESCR1	2
		#define MSR_TC_ESCR1	1
	MSR_FLAME_COUNTER0	= 8,
	MSR_FLAME_COUNTER1	= 9,
		#define MSR_FIRM_ESCR0	1
		#define MSR_FLAME_ESCR0	0
		#define MSR_DAC_ESCR0	5
		#define MSR_SAT_ESCR0	2
		#define MSR_U2L_ESCR0	3
	MSR_FLAME_COUNTER2	= 10,
	MSR_FLAME_COUNTER3	= 11,
		#define MSR_FIRM_ESCR1	1
		#define MSR_FLAME_ESCR1	0
		#define MSR_DAC_ESCR1	5
		#define MSR_SAT_ESCR1	2
		#define MSR_U2L_ESCR1	3
	MSR_IQ_COUNTER0		= 12,
	MSR_IQ_COUNTER1		= 13,
	MSR_IQ_COUNTER4		= 16,
		#define MSR_CRU_ESCR0	4
		#define MSR_CRU_ESCR2	5
		#define MSR_CRU_ESCR4	6
		#define MSR_IQ_ESCR0	0
		#define MSR_RAT_ESCR0	2
		#define MSR_SSU_ESCR0	3
		#define MSR_AFL_ESCR0	1
	MSR_IQ_COUNTER2		= 14,
	MSR_IQ_COUNTER3		= 15,
	MSR_IQ_COUNTER5		= 17,
		#define MSR_CRU_ESCR1	4
		#define MSR_CRU_ESCR3	5
		#define MSR_CRU_ESCR5	6
		#define MSR_IQ_ESCR1	0
		#define MSR_RAT_ESCR1	2
		#define MSR_AFL_ESCR1	1
} pmc_id_t;

typedef int pmc_escr_id_t;
#define PMC_ESID_MAX			7

/*
 * ESCR MSR layout:
 */
#define	PMC_ECSR_NOHTT_RESERVED		field(0,1)
#define	PMC_ECSR_T0_USR			bit(0)
#define	PMC_ECSR_T0_OS			bit(1)
#define	PMC_ECSR_T1_USR			bit(2)
#define	PMC_ECSR_T1_OS			bit(3)
#define	PMC_ECSR_USR			bit(2)
#define	PMC_ECSR_OS			bit(3)
#define	PMC_ECSR_TAG_ENABLE		bit(4)
#define	PMC_ECSR_TAG_VALUE		field(5,8)
#define	PMC_ECSR_EVENT_MASK		field(9,24)
#define	PMC_ECSR_EVENT_SELECT		field(25,30)
#define	PMC_ECSR_RESERVED2		field(30,64)
typedef struct {
	uint64_t	reserved1	: 2;
	uint64_t	usr		: 1;
	uint64_t	os		: 1;
	uint64_t	tag_enable	: 1;
	uint64_t	tag_value 	: 4;
	uint64_t	event_mask	: 16;
	uint64_t	event_select	: 6;
	uint64_t	reserved2	: 33;
} pmc_escr_nohtt_t;
typedef struct {
	uint64_t	t0_usr		: 1;
	uint64_t	t0_os		: 1;
	uint64_t	t1_usr		: 1;
	uint64_t	t1_os		: 1;
	uint64_t	tag_enable	: 1;
	uint64_t	tag_value 	: 4;
	uint64_t	event_mask	: 16;
	uint64_t	event_select	: 6;
	uint64_t	reserved2	: 33;
} pmc_escr_htt_t;
typedef union {
	pmc_escr_nohtt_t	u_nohtt;
	pmc_escr_htt_t		u_htt;
	uint64_t		u_u64;
} pmc_escr_t;
#define PMC_ESCR_ZERO	{ .u_u64 = 0ULL }

/*
 * CCCR MSR layout:
 */
#define	PMC_CCCR_RESERVED1		field(1,11)
#define	PMC_CCCR_ENABLE			bit(12)
#define	PMC_CCCR_ECSR_SELECT		field(13,15)
#define PMC_CCCR_RESERVED2		field(16,17)
#define PMC_CCCR_HTT_ACTIVE		field(16,17)
#define	PMC_CCCR_COMPARE		bit(18)
#define	PMC_CCCR_COMPLEMENT		bit(19)
#define	PMC_CCCR_THRESHOLD		field(20,23)
#define	PMC_CCCR_EDGE			bit(24)
#define	PMC_CCCR_FORCE_OVF		bit(25)
#define	PMC_CCCR_OVF_PMI		bit(26)
#define PMC_CCCR_NOHTT_RESERVED2	field(27,29)
#define	PMC_CCCR_OVF_PMI_T0		bit(26)
#define	PMC_CCCR_OVF_PMI_T1		bit(27)
#define PMC_CCCR_HTT_RESERVED2		field(28,29)
#define	PMC_CCCR_CASCADE		bit(30)
#define	PMC_CCCR_OVF			bit(31)
typedef struct {
	uint64_t	reserved1	: 12;
	uint64_t	enable		: 1;
	uint64_t	escr_select	: 3;
	uint64_t	reserved2	: 2;
	uint64_t	compare		: 1;
	uint64_t	complement	: 1;
	uint64_t	threshold	: 4;
	uint64_t	edge		: 1;
	uint64_t	force_ovf	: 1;
	uint64_t	ovf_pmi		: 1;
	uint64_t	reserved3	: 3;
	uint64_t	cascade		: 1;
	uint64_t	ovf		: 1;
	uint64_t	reserved4	: 32;
} pmc_cccr_nohtt_t;
typedef struct {
	uint64_t	reserved1	: 12;
	uint64_t	enable		: 1;
	uint64_t	escr_select	: 3;
	uint64_t	active_thread	: 2;
	uint64_t	compare		: 1;
	uint64_t	complement	: 1;
	uint64_t	threshold	: 4;
	uint64_t	edge		: 1;
	uint64_t	force_OVF	: 1;
	uint64_t	ovf_pmi_t0	: 1;
	uint64_t	ovf_pmi_t1	: 1;
	uint64_t	reserved3	: 2;
	uint64_t	cascade		: 1;
	uint64_t	ovf		: 1;
	uint64_t	reserved4	: 32;
} pmc_cccr_htt_t;
typedef union {
	pmc_cccr_nohtt_t	u_nohtt;
	pmc_cccr_htt_t		u_htt;
	uint64_t		u_u64;
} pmc_cccr_t;
#define PMC_CCCR_ZERO	{ .u_u64 = 0ULL }

typedef void (pmc_ovf_func_t)(pmc_id_t id, void *state);

/*
 * In-kernel PMC access primitives:
 */
/* Generic: */
extern int pmc_init(void);
extern int pmc_machine_type(pmc_machine_t *type);
extern boolean_t pmc_is_reserved(pmc_id_t id);
extern int pmc_reserve(pmc_id_t id);
extern int pmc_free(pmc_id_t id);
extern int pmc_counter_read(pmc_id_t id, pmc_counter_t *val);
extern int pmc_counter_write(pmc_id_t id, pmc_counter_t *val);

/* P6-specific: */
extern int pmc_evtsel_read(pmc_id_t id, pmc_evtsel_t *evtsel);
extern int pmc_evtsel_write(pmc_id_t id, pmc_evtsel_t *evtsel);

/* P4/Xeon-specific: */
extern int pmc_cccr_read(pmc_id_t id, pmc_cccr_t *cccr);
extern int pmc_cccr_write(pmc_id_t id, pmc_cccr_t *cccr);
extern int pmc_escr_read(pmc_id_t id, pmc_escr_id_t esid, pmc_escr_t *escr);
extern int pmc_escr_write(pmc_id_t id, pmc_escr_id_t esid, pmc_escr_t *escr);
extern int pmc_set_ovf_func(pmc_id_t id, pmc_ovf_func_t *func);

#endif /* _I386_PERFMON_H_ */
Commit	Line	Data
91447636 A	1	/*
	2	* Copyright (c) 2003 Apple Computer, Inc. All rights reserved.
	3	*
	4	* @APPLE_LICENSE_HEADER_START@
	5	*
ff6e181a A	6	* This file contains Original Code and/or Modifications of Original Code
	7	* as defined in and that are subject to the Apple Public Source License
	8	* Version 2.0 (the 'License'). You may not use this file except in
	9	* compliance with the License. Please obtain a copy of the License at
	10	* http://www.opensource.apple.com/apsl/ and read it before using this
	11	* file.
91447636	12	*
ff6e181a A	13	* The Original Code and all software distributed under the License are
ff6e181a A	14	* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
91447636 A	15	* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
91447636 A	16	* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
ff6e181a A	17	* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
	18	* Please see the License for the specific language governing rights and
	19	* limitations under the License.
91447636 A	20	*
	21	* @APPLE_LICENSE_HEADER_END@
	22	*/
	23	#ifndef _I386_PERFMON_H_
	24	#define _I386_PERFMON_H_
	25
	26	#include <i386/proc_reg.h>
	27
	28	/*
	29	* Handy macros for bit/bitfield definition and manipulations:
	30	*/
	31	#define bit(n) (1ULL << (n))
	32	#define field(n,m) ((bit((m)+1)-1) & ~(bit(n)-1))
	33	#define field_nbit(fld) (ffs(fld)-1)
	34	#define field_select(fld,x) ((x) & (fld))
	35	#define field_clear(fld,x) ((x) & ~(fld))
	36	#define field_unshift(fld,x) ((x) >> field_nbit(fld))
	37	#define field_shift(fld,x) ((x) << field_nbit(fld))
	38	#define field_get(fld,x) (field_unshift(fld,field_select(fld,x)))
	39	#define field_set(fld,x,val) (field_clear(fld,x) \| field_shift(fld,val))
	40
	41	#define PERFMON_AVAILABLE bit(7)
	42	#define BTS_UNAVAILABLE bit(11)
	43
	44	static inline boolean_t
	45	pmc_is_available(void)
	46	{
	47	uint32_t lo;
	48	uint32_t hi;
	49	int ret;
	50
	51	ret = rdmsr_carefully(MSR_IA32_MISC_ENABLE, &lo, &hi);
	52
	53	return (ret == 0) && ((lo & PERFMON_AVAILABLE) != 0);
	54	}
	55
	56	/*
	57	* Counter layout:
	58	*/
	59	#define PMC_COUNTER_COUNTER field(0,39)
	60	#define PMC_COUNTER_RESERVED field(40,64)
	61	#define PMC_COUNTER_MAX ((uint64_t) PMC_COUNTER_COUNTER)
	62	typedef struct {
	63	uint64_t counter : 40;
	64	uint64_t reserved : 24;
	65	} pmc_counter_t;
	66	#define PMC_COUNTER_ZERO { 0, 0 }
	67
	68
	69	/*
	70	* There are 2 basic flavors of PMCsL: P6 and P4/Xeon:
	71	*/
	72	typedef enum {
	73	pmc_none,
	74	pmc_P6,
	75	pmc_P4_Xeon,
	76	pmc_unknown
	77	} pmc_machine_t;
	78
	79	/*
	80	* P6 MSRs...
	81	*/
	82	#define MSR_P6_COUNTER_ADDR(n) (0x0c1 + (n))
	83	#define MSR_P6_PES_ADDR(n) (0x186 + (n))
84
85	typedef struct {
86	uint64_t event_select : 8;
87	uint64_t umask : 8;
88	uint64_t usr : 1;
89	uint64_t os : 1;
90	uint64_t e : 1;
91	uint64_t pc : 1;
92	uint64_t apic_int : 1;
93	uint64_t reserved1 : 1;
94	uint64_t en : 1;
95	uint64_t inv : 1;
96	uint64_t cmask : 8;
97	} pmc_evtsel_t;
98	#define PMC_EVTSEL_ZERO ((pmc_evtsel_t){ 0,0,0,0,0,0,0,0,0,0,0 })
99
100	#define MSR_P6_PERFCTR0 0
101	#define MSR_P6_PERFCTR1 1
102
103	/*
104	* P4/Xeon MSRs...
105	*/
106	#define MSR_COUNTER_ADDR(n) (0x300 + (n))
107	#define MSR_CCCR_ADDR(n) (0x360 + (n))
108
109	typedef enum {
110	MSR_BPU_COUNTER0 = 0,
111	MSR_BPU_COUNTER1 = 1,
112	#define MSR_BSU_ESCR0 7
113	#define MSR_FSB_ESCR0 6
114	#define MSR_MOB_ESCR0 2
115	#define MSR_PMH_ESCR0 4
116	#define MSR_BPU_ESCR0 0
117	#define MSR_IS_ESCR0 1
118	#define MSR_ITLB_ESCR0 3
119	#define MSR_IX_ESCR0 5
120	MSR_BPU_COUNTER2 = 2,
121	MSR_BPU_COUNTER3 = 3,
122	#define MSR_BSU_ESCR1 7
123	#define MSR_FSB_ESCR1 6
124	#define MSR_MOB_ESCR1 2
125	#define MSR_PMH_ESCR1 4
126	#define MSR_BPU_ESCR1 0
127	#define MSR_IS_ESCR1 1
128	#define MSR_ITLB_ESCR1 3
129	#define MSR_IX_ESCR1 5
130	MSR_MS_COUNTER0 = 4,
131	MSR_MS_COUNTER1 = 5,
132	#define MSR_MS_ESCR0 0
133	#define MSR_TBPU_ESCR0 2
134	#define MSR_TC_ESCR0 1
135	MSR_MS_COUNTER2 = 6,
136	MSR_MS_COUNTER3 = 7,
137	#define MSR_MS_ESCR1 0
138	#define MSR_TBPU_ESCR1 2
139	#define MSR_TC_ESCR1 1
140	MSR_FLAME_COUNTER0 = 8,
141	MSR_FLAME_COUNTER1 = 9,
142	#define MSR_FIRM_ESCR0 1
143	#define MSR_FLAME_ESCR0 0
144	#define MSR_DAC_ESCR0 5
145	#define MSR_SAT_ESCR0 2
146	#define MSR_U2L_ESCR0 3
147	MSR_FLAME_COUNTER2 = 10,
148	MSR_FLAME_COUNTER3 = 11,
149	#define MSR_FIRM_ESCR1 1
150	#define MSR_FLAME_ESCR1 0
151	#define MSR_DAC_ESCR1 5
152	#define MSR_SAT_ESCR1 2
153	#define MSR_U2L_ESCR1 3
154	MSR_IQ_COUNTER0 = 12,
155	MSR_IQ_COUNTER1 = 13,
156	MSR_IQ_COUNTER4 = 16,
157	#define MSR_CRU_ESCR0 4
158	#define MSR_CRU_ESCR2 5
159	#define MSR_CRU_ESCR4 6
160	#define MSR_IQ_ESCR0 0
161	#define MSR_RAT_ESCR0 2
162	#define MSR_SSU_ESCR0 3
163	#define MSR_AFL_ESCR0 1
164	MSR_IQ_COUNTER2 = 14,
165	MSR_IQ_COUNTER3 = 15,
166	MSR_IQ_COUNTER5 = 17,
167	#define MSR_CRU_ESCR1 4
168	#define MSR_CRU_ESCR3 5
169	#define MSR_CRU_ESCR5 6
170	#define MSR_IQ_ESCR1 0
171	#define MSR_RAT_ESCR1 2
172	#define MSR_AFL_ESCR1 1
173	} pmc_id_t;
174
175	typedef int pmc_escr_id_t;
176	#define PMC_ESID_MAX 7
177
178	/*
179	* ESCR MSR layout:
180	*/
181	#define PMC_ECSR_NOHTT_RESERVED field(0,1)
182	#define PMC_ECSR_T0_USR bit(0)
183	#define PMC_ECSR_T0_OS bit(1)
184	#define PMC_ECSR_T1_USR bit(2)
185	#define PMC_ECSR_T1_OS bit(3)
186	#define PMC_ECSR_USR bit(2)
187	#define PMC_ECSR_OS bit(3)
188	#define PMC_ECSR_TAG_ENABLE bit(4)
189	#define PMC_ECSR_TAG_VALUE field(5,8)
190	#define PMC_ECSR_EVENT_MASK field(9,24)
191	#define PMC_ECSR_EVENT_SELECT field(25,30)
192	#define PMC_ECSR_RESERVED2 field(30,64)
193	typedef struct {
194	uint64_t reserved1 : 2;
195	uint64_t usr : 1;
196	uint64_t os : 1;
197	uint64_t tag_enable : 1;
198	uint64_t tag_value : 4;
199	uint64_t event_mask : 16;
200	uint64_t event_select : 6;
201	uint64_t reserved2 : 33;
202	} pmc_escr_nohtt_t;
203	typedef struct {
204	uint64_t t0_usr : 1;
205	uint64_t t0_os : 1;
206	uint64_t t1_usr : 1;
207	uint64_t t1_os : 1;
208	uint64_t tag_enable : 1;
209	uint64_t tag_value : 4;
210	uint64_t event_mask : 16;
211	uint64_t event_select : 6;
212	uint64_t reserved2 : 33;
213	} pmc_escr_htt_t;
214	typedef union {
215	pmc_escr_nohtt_t u_nohtt;
216	pmc_escr_htt_t u_htt;
217	uint64_t u_u64;
218	} pmc_escr_t;
219	#define PMC_ESCR_ZERO { .u_u64 = 0ULL }
220
221	/*
222	* CCCR MSR layout:
223	*/
224	#define PMC_CCCR_RESERVED1 field(1,11)
225	#define PMC_CCCR_ENABLE bit(12)
226	#define PMC_CCCR_ECSR_SELECT field(13,15)
227	#define PMC_CCCR_RESERVED2 field(16,17)
228	#define PMC_CCCR_HTT_ACTIVE field(16,17)
229	#define PMC_CCCR_COMPARE bit(18)
230	#define PMC_CCCR_COMPLEMENT bit(19)
231	#define PMC_CCCR_THRESHOLD field(20,23)
232	#define PMC_CCCR_EDGE bit(24)
233	#define PMC_CCCR_FORCE_OVF bit(25)
234	#define PMC_CCCR_OVF_PMI bit(26)
235	#define PMC_CCCR_NOHTT_RESERVED2 field(27,29)
236	#define PMC_CCCR_OVF_PMI_T0 bit(26)
237	#define PMC_CCCR_OVF_PMI_T1 bit(27)
238	#define PMC_CCCR_HTT_RESERVED2 field(28,29)
239	#define PMC_CCCR_CASCADE bit(30)
240	#define PMC_CCCR_OVF bit(31)
241	typedef struct {
242	uint64_t reserved1 : 12;
243	uint64_t enable : 1;
244	uint64_t escr_select : 3;
245	uint64_t reserved2 : 2;
246	uint64_t compare : 1;
247	uint64_t complement : 1;
248	uint64_t threshold : 4;
249	uint64_t edge : 1;
250	uint64_t force_ovf : 1;
251	uint64_t ovf_pmi : 1;
252	uint64_t reserved3 : 3;
253	uint64_t cascade : 1;
254	uint64_t ovf : 1;
255	uint64_t reserved4 : 32;
256	} pmc_cccr_nohtt_t;
257	typedef struct {
258	uint64_t reserved1 : 12;
259	uint64_t enable : 1;
260	uint64_t escr_select : 3;
261	uint64_t active_thread : 2;
262	uint64_t compare : 1;
263	uint64_t complement : 1;
264	uint64_t threshold : 4;
265	uint64_t edge : 1;
266	uint64_t force_OVF : 1;
267	uint64_t ovf_pmi_t0 : 1;
268	uint64_t ovf_pmi_t1 : 1;
269	uint64_t reserved3 : 2;
270	uint64_t cascade : 1;
271	uint64_t ovf : 1;
272	uint64_t reserved4 : 32;
273	} pmc_cccr_htt_t;
274	typedef union {
275	pmc_cccr_nohtt_t u_nohtt;
276	pmc_cccr_htt_t u_htt;
277	uint64_t u_u64;
278	} pmc_cccr_t;
279	#define PMC_CCCR_ZERO { .u_u64 = 0ULL }
280
281	typedef void (pmc_ovf_func_t)(pmc_id_t id, void *state);
282
283	/*
284	* In-kernel PMC access primitives:
285	*/
286	/* Generic: */
287	extern int pmc_init(void);
288	extern int pmc_machine_type(pmc_machine_t *type);
289	extern boolean_t pmc_is_reserved(pmc_id_t id);
290	extern int pmc_reserve(pmc_id_t id);
291	extern int pmc_free(pmc_id_t id);
292	extern int pmc_counter_read(pmc_id_t id, pmc_counter_t *val);
293	extern int pmc_counter_write(pmc_id_t id, pmc_counter_t *val);
294
295	/* P6-specific: */
296	extern int pmc_evtsel_read(pmc_id_t id, pmc_evtsel_t *evtsel);
297	extern int pmc_evtsel_write(pmc_id_t id, pmc_evtsel_t *evtsel);
298
299	/* P4/Xeon-specific: */
300	extern int pmc_cccr_read(pmc_id_t id, pmc_cccr_t *cccr);
301	extern int pmc_cccr_write(pmc_id_t id, pmc_cccr_t *cccr);
302	extern int pmc_escr_read(pmc_id_t id, pmc_escr_id_t esid, pmc_escr_t *escr);
303	extern int pmc_escr_write(pmc_id_t id, pmc_escr_id_t esid, pmc_escr_t *escr);
304	extern int pmc_set_ovf_func(pmc_id_t id, pmc_ovf_func_t *func);
305
306	#endif /* _I386_PERFMON_H_ */