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1/*
2 * Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
3 *
4 * @APPLE_LICENSE_HEADER_START@
5 *
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6 * This file contains Original Code and/or Modifications of Original Code
7 * as defined in and that are subject to the Apple Public Source License
8 * Version 2.0 (the 'License'). You may not use this file except in
9 * compliance with the License. Please obtain a copy of the License at
10 * http://www.opensource.apple.com/apsl/ and read it before using this
11 * file.
1c79356b 12 *
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13 * The Original Code and all software distributed under the License are
14 * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
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15 * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
16 * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
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17 * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
18 * Please see the License for the specific language governing rights and
19 * limitations under the License.
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20 *
21 * @APPLE_LICENSE_HEADER_END@
22 */
23/*
24 * @OSF_COPYRIGHT@
25 */
26/*
27 * Mach Operating System
28 * Copyright (c) 1991 Carnegie Mellon University
29 * All Rights Reserved.
30 *
31 * Permission to use, copy, modify and distribute this software and its
32 * documentation is hereby granted, provided that both the copyright
33 * notice and this permission notice appear in all copies of the
34 * software, derivative works or modified versions, and any portions
35 * thereof, and that both notices appear in supporting documentation.
36 *
37 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
38 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
39 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
40 *
41 * Carnegie Mellon requests users of this software to return to
42 *
43 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
44 * School of Computer Science
45 * Carnegie Mellon University
46 * Pittsburgh PA 15213-3890
47 *
48 * any improvements or extensions that they make and grant Carnegie Mellon
49 * the rights to redistribute these changes.
50 */
51
52/*
53 */
54
55#ifndef _I386_FPU_H_
56#define _I386_FPU_H_
57
58/*
59 * Macro definitions for routines to manipulate the
60 * floating-point processor.
61 */
62
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63#include <i386/proc_reg.h>
64#include <i386/thread.h>
65#include <kern/kern_types.h>
66#include <mach/i386/kern_return.h>
67#include <mach/i386/thread_status.h>
68
69/*
70 * FPU instructions.
71 */
72#define fninit() \
73 __asm__ volatile("fninit")
74
75#define fnstcw(control) \
76 __asm__("fnstcw %0" : "=m" (*(unsigned short *)(control)))
77
78#define fldcw(control) \
79 __asm__ volatile("fldcw %0" : : "m" (*(unsigned short *) &(control)) )
80
81extern unsigned short fnstsw(void);
82
83extern __inline__ unsigned short fnstsw(void)
84{
85 unsigned short status;
86 __asm__ volatile("fnstsw %0" : "=ma" (status));
87 return(status);
88}
89
90#define fnclex() \
91 __asm__ volatile("fnclex")
92
55e303ae 93#define fnsave(state) \
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94 __asm__ volatile("fnsave %0" : "=m" (*state))
95
96#define frstor(state) \
97 __asm__ volatile("frstor %0" : : "m" (state))
98
99#define fwait() \
100 __asm__("fwait");
101
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102#define fxrstor(addr) __asm("fxrstor %0" : : "m" (*(addr)))
103#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
104
105#define FXSAFE() (fp_kind == FP_FXSR)
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106
107#define fpu_load_context(pcb)
108
109/*
110 * Save thread`s FPU context.
111 * If only one CPU, we just set the task-switched bit,
112 * to keep the new thread from using the coprocessor.
113 * If multiple CPUs, we save the entire state.
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114 * NOTE: in order to provide backwards compatible support in the kernel. When saving SSE2 state, we also save the
115 * FP state in it's old location. Otherwise fpu_get_state() and fpu_set_state() will stop working
1c79356b 116 */
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117#define fpu_save_context(thread) \
118 { \
119 register struct i386_fpsave_state *ifps; \
91447636 120 ifps = (thread)->machine.pcb->ims.ifps; \
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121 if (ifps != 0 && !ifps->fp_valid) { \
122 /* registers are in FPU - save to memory */ \
123 ifps->fp_valid = TRUE; \
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124 ifps->fp_save_flavor = FP_387; \
125 if (FXSAFE()) { \
126 fxsave(&ifps->fx_save_state); \
127 ifps->fp_save_flavor = FP_FXSR; \
128 } \
129 fnsave(&ifps->fp_save_state); \
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130 } \
131 set_ts(); \
132 }
133
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134
135
136extern int fp_kind;
137
138extern void init_fpu(void);
139extern void fpu_module_init(void);
91447636 140extern void fpu_free(
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141 struct i386_fpsave_state * fps);
142extern kern_return_t fpu_set_state(
91447636 143 thread_t thr_act,
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144 struct i386_float_state * st);
145extern kern_return_t fpu_get_state(
91447636 146 thread_t thr_act,
1c79356b 147 struct i386_float_state * st);
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148extern kern_return_t fpu_set_fxstate(
149 thread_t thr_act,
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150 struct i386_float_state * st);
151extern kern_return_t fpu_get_fxstate(
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152 thread_t thr_act,
153 struct i386_float_state * st);
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154extern void fpnoextflt(void);
155extern void fpextovrflt(void);
156extern void fpexterrflt(void);
157extern void fp_state_alloc(void);
158extern void fpintr(void);
91447636 159extern void fpflush(thread_t);
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160
161#endif /* _I386_FPU_H_ */