projects / apple / xnu.git / blame
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|---|---|---|
| 1c79356b A |
1 | /* |
| 2 | * Copyright (c) 2000 Apple Computer, Inc. All rights reserved. | |
| 3 | * | |
| 4 | * @APPLE_LICENSE_HEADER_START@ | |
| 5 | * | |
| ff6e181a A |
6 | * This file contains Original Code and/or Modifications of Original Code |
| 7 | * as defined in and that are subject to the Apple Public Source License | |
| 8 | * Version 2.0 (the 'License'). You may not use this file except in | |
| 9 | * compliance with the License. Please obtain a copy of the License at | |
| 10 | * http://www.opensource.apple.com/apsl/ and read it before using this | |
| 11 | * file. | |
| 12 | * | |
| 13 | * The Original Code and all software distributed under the License are | |
| 14 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
| 1c79356b A |
15 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, |
| 16 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
| ff6e181a A |
17 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. |
| 18 | * Please see the License for the specific language governing rights and | |
| 19 | * limitations under the License. | |
| 1c79356b A |
20 | * |
| 21 | * @APPLE_LICENSE_HEADER_END@ | |
| 22 | */ | |
| 23 | /* | |
| 24 | * @OSF_COPYRIGHT@ | |
| 25 | */ | |
| 26 | /* | |
| 27 | * HISTORY | |
| 28 | * | |
| 29 | * Revision 1.1.1.1 1998/09/22 21:05:39 wsanchez | |
| 30 | * Import of Mac OS X kernel (~semeria) | |
| 31 | * | |
| 32 | * Revision 1.1.1.1 1998/03/07 02:25:40 wsanchez | |
| 33 | * Import of OSF Mach kernel (~mburg) | |
| 34 | * | |
| 35 | * Revision 1.1.6.1 1994/09/23 01:47:30 ezf | |
| 36 | * change marker to not FREE | |
| 37 | * [1994/09/22 21:20:22 ezf] | |
| 38 | * | |
| 39 | * Revision 1.1.2.3 1993/08/09 19:39:04 dswartz | |
| 40 | * Add ANSI prototypes - CR#9523 | |
| 41 | * [1993/08/06 17:51:17 dswartz] | |
| 42 | * | |
| 43 | * Revision 1.1.2.2 1993/06/02 23:21:32 jeffc | |
| 44 | * Added to OSF/1 R1.3 from NMK15.0. | |
| 45 | * [1993/06/02 21:03:17 jeffc] | |
| 46 | * | |
| 47 | * Revision 1.1 1992/09/30 02:27:20 robert | |
| 48 | * Initial revision | |
| 49 | * | |
| 50 | * $EndLog$ | |
| 51 | */ | |
| 52 | /* CMU_HIST */ | |
| 53 | /* | |
| 54 | * Revision 2.7 91/05/14 16:30:03 mrt | |
| 55 | * Correcting copyright | |
| 56 | * | |
| 57 | * Revision 2.6 91/03/16 14:47:03 rpd | |
| 58 | * Fixed ioctl definitions for ANSI C. | |
| 59 | * [91/02/20 rpd] | |
| 60 | * | |
| 61 | * Revision 2.5 91/02/05 17:20:25 mrt | |
| 62 | * Changed to new Mach copyright | |
| 63 | * [91/02/01 17:47:16 mrt] | |
| 64 | * | |
| 65 | * Revision 2.4 90/11/26 14:51:02 rvb | |
| 66 | * jsb bet me to XMK34, sigh ... | |
| 67 | * [90/11/26 rvb] | |
| 68 | * Synched 2.5 & 3.0 at I386q (r1.5.1.3) & XMK35 (r2.4) | |
| 69 | * [90/11/15 rvb] | |
| 70 | * | |
| 71 | * Revision 1.5.1.2 90/07/27 11:27:06 rvb | |
| 72 | * Fix Intel Copyright as per B. Davies authorization. | |
| 73 | * [90/07/27 rvb] | |
| 74 | * | |
| 75 | * Revision 2.2 90/05/03 15:46:11 dbg | |
| 76 | * First checkin. | |
| 77 | * | |
| 78 | * Revision 1.5.1.1 90/01/08 13:29:46 rvb | |
| 79 | * Add Intel copyright. | |
| 80 | * [90/01/08 rvb] | |
| 81 | * | |
| 82 | * Revision 1.5 89/09/25 12:27:37 rvb | |
| 83 | * File was provided by Intel 9/18/89. | |
| 84 | * [89/09/23 rvb] | |
| 85 | * | |
| 86 | */ | |
| 87 | /* CMU_ENDHIST */ | |
| 88 | /* | |
| 89 | * Mach Operating System | |
| 90 | * Copyright (c) 1991,1990,1989 Carnegie Mellon University | |
| 91 | * All Rights Reserved. | |
| 92 | * | |
| 93 | * Permission to use, copy, modify and distribute this software and its | |
| 94 | * documentation is hereby granted, provided that both the copyright | |
| 95 | * notice and this permission notice appear in all copies of the | |
| 96 | * software, derivative works or modified versions, and any portions | |
| 97 | * thereof, and that both notices appear in supporting documentation. | |
| 98 | * | |
| 99 | * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" | |
| 100 | * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR | |
| 101 | * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. | |
| 102 | * | |
| 103 | * Carnegie Mellon requests users of this software to return to | |
| 104 | * | |
| 105 | * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU | |
| 106 | * School of Computer Science | |
| 107 | * Carnegie Mellon University | |
| 108 | * Pittsburgh PA 15213-3890 | |
| 109 | * | |
| 110 | * any improvements or extensions that they make and grant Carnegie Mellon | |
| 111 | * the rights to redistribute these changes. | |
| 112 | */ | |
| 113 | /* | |
| 114 | */ | |
| 115 | ||
| 116 | /* | |
| 117 | * Copyright 1988, 1989 by Intel Corporation, Santa Clara, California. | |
| 118 | * | |
| 119 | * All Rights Reserved | |
| 120 | * | |
| 121 | * Permission to use, copy, modify, and distribute this software and | |
| 122 | * its documentation for any purpose and without fee is hereby | |
| 123 | * granted, provided that the above copyright notice appears in all | |
| 124 | * copies and that both the copyright notice and this permission notice | |
| 125 | * appear in supporting documentation, and that the name of Intel | |
| 126 | * not be used in advertising or publicity pertaining to distribution | |
| 127 | * of the software without specific, written prior permission. | |
| 128 | * | |
| 129 | * INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE | |
| 130 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, | |
| 131 | * IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR | |
| 132 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM | |
| 133 | * LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, | |
| 134 | * NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION | |
| 135 | * WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| 136 | */ | |
| 137 | ||
| 138 | #define RTC_ADDR 0x70 /* I/O port address for register select */ | |
| 139 | #define RTC_DATA 0x71 /* I/O port address for data read/write */ | |
| 140 | ||
| 141 | /* | |
| 142 | * Register A definitions | |
| 143 | */ | |
| 144 | #define RTC_A 0x0a /* register A address */ | |
| 145 | #define RTC_UIP 0x80 /* Update in progress bit */ | |
| 146 | #define RTC_DIV0 0x00 /* Time base of 4.194304 MHz */ | |
| 147 | #define RTC_DIV1 0x10 /* Time base of 1.048576 MHz */ | |
| 148 | #define RTC_DIV2 0x20 /* Time base of 32.768 KHz */ | |
| 149 | #define RTC_RATE6 0x06 /* interrupt rate of 976.562 */ | |
| 150 | ||
| 151 | /* | |
| 152 | * Register B definitions | |
| 153 | */ | |
| 154 | #define RTC_B 0x0b /* register B address */ | |
| 155 | #define RTC_SET 0x80 /* stop updates for time set */ | |
| 156 | #define RTC_PIE 0x40 /* Periodic interrupt enable */ | |
| 157 | #define RTC_AIE 0x20 /* Alarm interrupt enable */ | |
| 158 | #define RTC_UIE 0x10 /* Update ended interrupt enable */ | |
| 159 | #define RTC_SQWE 0x08 /* Square wave enable */ | |
| 160 | #define RTC_DM 0x04 /* Date mode, 1 = binary, 0 = BCD */ | |
| 161 | #define RTC_HM 0x02 /* hour mode, 1 = 24 hour, 0 = 12 hour */ | |
| 162 | #define RTC_DSE 0x01 /* Daylight savings enable */ | |
| 163 | ||
| 164 | /* | |
| 165 | * Register C definitions | |
| 166 | */ | |
| 167 | #define RTC_C 0x0c /* register C address */ | |
| 168 | #define RTC_IRQF 0x80 /* IRQ flag */ | |
| 169 | #define RTC_PF 0x40 /* PF flag bit */ | |
| 170 | #define RTC_AF 0x20 /* AF flag bit */ | |
| 171 | #define RTC_UF 0x10 /* UF flag bit */ | |
| 172 | ||
| 173 | /* | |
| 174 | * Register D definitions | |
| 175 | */ | |
| 176 | #define RTC_D 0x0d /* register D address */ | |
| 177 | #define RTC_VRT 0x80 /* Valid RAM and time bit */ | |
| 178 | ||
| 179 | #define RTC_NREG 0x0e /* number of RTC registers */ | |
| 180 | #define RTC_NREGP 0x0a /* number of RTC registers to set time */ | |
| 181 | ||
| 182 | #define RTCRTIME _IOR('c', 0x01, struct rtc_st) /* Read time from RTC */ | |
| 183 | #define RTCSTIME _IOW('c', 0x02, struct rtc_st) /* Set time into RTC */ | |
| 184 | ||
| 185 | struct rtc_st { | |
| 186 | char rtc_sec; | |
| 187 | char rtc_asec; | |
| 188 | char rtc_min; | |
| 189 | char rtc_amin; | |
| 190 | char rtc_hr; | |
| 191 | char rtc_ahr; | |
| 192 | char rtc_dow; | |
| 193 | char rtc_dom; | |
| 194 | char rtc_mon; | |
| 195 | char rtc_yr; | |
| 196 | char rtc_statusa; | |
| 197 | char rtc_statusb; | |
| 198 | char rtc_statusc; | |
| 199 | char rtc_statusd; | |
| 200 | }; | |
| 201 | ||
| 202 | /* | |
| 203 | * this macro reads contents of real time clock to specified buffer | |
| 204 | */ | |
| 205 | #define load_rtc(regs) \ | |
| 206 | {\ | |
| 207 | register int i; \ | |
| 208 | \ | |
| 209 | for (i = 0; i < RTC_NREG; i++) { \ | |
| 210 | outb(RTC_ADDR, i); \ | |
| 211 | (regs)[i] = inb(RTC_DATA); \ | |
| 212 | } \ | |
| 213 | } | |
| 214 | ||
| 215 | /* | |
| 216 | * this macro writes contents of specified buffer to real time clock | |
| 217 | */ | |
| 218 | #define save_rtc(regs) \ | |
| 219 | { \ | |
| 220 | register int i; \ | |
| 221 | for (i = 0; i < RTC_NREGP; i++) { \ | |
| 222 | outb(RTC_ADDR, i); \ | |
| 223 | outb(RTC_DATA, (regs)[i]);\ | |
| 224 | } \ | |
| 225 | } | |
| 226 | ||
| 227 |