[apple/xnu.git] / pexpert / pexpert / arm64 / board_config.h

/*
 * Copyright (c) 2007-2020 Apple Inc. All rights reserved.
 * Copyright (c) 2005-2006 Apple Computer, Inc. All rights reserved.
 */
#ifndef _PEXPERT_ARM_BOARD_CONFIG_H
#define _PEXPERT_ARM_BOARD_CONFIG_H

#include <mach/machine.h>

/*
 * Per-SoC configuration.  General order is:
 *
 * CPU type
 * CPU configuration
 * CPU feature disables / workarounds
 * CPU topology
 * Other platform configuration (e.g. DARTs, PPL)
 *
 * This should answer the question: "what's unique about this SoC?"
 *
 * arm64/H*.h should answer the question: "what's unique about this CPU core?"
 *
 * For __ARM_AMP__ systems that have different cache line sizes on different
 * clusters, MAX_L2_CLINE must reflect the largest L2 cache line size
 * across all clusters.
 */


#ifdef ARM64_BOARD_CONFIG_T7000
#include <pexpert/arm64/H7.h>

#define MAX_L2_CLINE                   6
#define MAX_CPUS                       3
#define MAX_CPU_CLUSTERS               1
#endif  /* ARM64_BOARD_CONFIG_T7000 */

#ifdef ARM64_BOARD_CONFIG_T7001
#include <pexpert/arm64/H7.h>

#define MAX_L2_CLINE                   6
#define MAX_CPUS                       3
#define MAX_CPU_CLUSTERS               1
#endif  /* ARM64_BOARD_CONFIG_T7001 */

#ifdef ARM64_BOARD_CONFIG_S8000
#include <pexpert/arm64/H8.h>
#define MAX_CPUS                       2
#define MAX_CPU_CLUSTERS               1
/*
 * The L2 size for twister is in fact 3MB, not 4MB; we round up due
 * to the code being architected for power of 2 cache sizes, and rely
 * on the expected behavior that out of bounds operations will be
 * ignored.
 */
#define MAX_L2_CLINE                   6
#endif  /* ARM64_BOARD_CONFIG_S8000 */

#ifdef ARM64_BOARD_CONFIG_S8001
#include <pexpert/arm64/H8.h>
#define MAX_CPUS                       2
#define MAX_CPU_CLUSTERS               1
/*
 * The L2 size for twister is in fact 3MB, not 4MB; we round up due
 * to the code being architected for power of 2 cache sizes, and rely
 * on the expect behavior that out of bounds operations will be
 * ignored.
 */
#define MAX_L2_CLINE                   6
#endif  /* ARM64_BOARD_CONFIG_S8001 */

#ifdef ARM64_BOARD_CONFIG_T8010
#include <pexpert/arm64/H9.h>
#define MAX_CPUS                       3
#define MAX_CPU_CLUSTERS               1
/*
 * The L2 size for hurricane/zephyr is in fact 3MB, not 4MB; we round up due
 * to the code being architected for power of 2 cache sizes, and rely
 * on the expect behavior that out of bounds operations will be
 * ignored.
 */
#define MAX_L2_CLINE                   7

#if DEVELOPMENT || DEBUG
#define PMAP_CS                        1
#define PMAP_CS_ENABLE                 0
#endif
#endif  /* ARM64_BOARD_CONFIG_T8010 */

#ifdef ARM64_BOARD_CONFIG_T8011
#include <pexpert/arm64/H9.h>

#define MAX_L2_CLINE                   7
#define MAX_CPUS                       3
#define MAX_CPU_CLUSTERS               1

#if DEVELOPMENT || DEBUG
#define PMAP_CS                        1
#define PMAP_CS_ENABLE                 0
#endif
#endif  /* ARM64_BOARD_CONFIG_T8011 */

#ifdef ARM64_BOARD_CONFIG_T8015
#include <pexpert/arm64/H10.h>

#define MAX_L2_CLINE                   7
#define MAX_CPUS                       6
#define MAX_CPU_CLUSTERS               2

#define BROKEN_FRIGGING_SLEEP          1 /* Spurious wake: See rdar://problem/29762505 */

#if DEVELOPMENT || DEBUG
#define PMAP_CS                        1
#define PMAP_CS_ENABLE                 0
#endif
#endif  /* ARM64_BOARD_CONFIG_T8015 */

#ifdef ARM64_BOARD_CONFIG_T8020
#include <pexpert/arm64/H11.h>

#define MAX_L2_CLINE                   7
#define MAX_CPUS                       8
#define MAX_CPU_CLUSTERS               2

#define XNU_MONITOR                    1 /* Secure pmap runtime */
#define XNU_MONITOR_T8020_DART         1 /* T8020 DART plugin for secure pmap runtime */
#define T8020_DART_ALLOW_BYPASS        (1 << 1) /* DART allows translation bypass in certain cases */
#define XNU_MONITOR_NVME_PPL           1 /* NVMe PPL plugin for secure pmap runtime */
#define XNU_MONITOR_ANS2_SART          1 /* ANS2 SART plugin for secure pmap runtime */
#define PMAP_CS                        1
#define PMAP_CS_ENABLE                 1
#endif  /* ARM64_BOARD_CONFIG_T8020 */

#ifdef ARM64_BOARD_CONFIG_T8006
/*
 * The T8006 consists of 2 Tempest cores (i.e. T8020 eCores) and for most
 * of our purposes here may be considered a functional subset of T8020.
 */
#include <pexpert/arm64/H11.h>

#undef HAS_UNCORE_CTRS
#ifdef XNU_TARGET_OS_WATCH // This check might be redundant
#undef __APRR_SHADOW_SUPPORTED__
#endif

#define MAX_L2_CLINE                   7
#define MAX_CPUS                       2
#define MAX_CPU_CLUSTERS               1

#define XNU_MONITOR                    1 /* Secure pmap runtime */
#define XNU_MONITOR_T8020_DART         1 /* T8020 DART plugin for secure pmap runtime */
#define T8020_DART_ALLOW_BYPASS        (1 << 1) /* DART allows translation bypass in certain cases */
#define XNU_MONITOR_NVME_PPL           1 /* NVMe PPL plugin for secure pmap runtime */
#define XNU_MONITOR_ANS2_SART          1 /* ANS2 SART plugin for secure pmap runtime */
#define PMAP_CS                        1
#define PMAP_CS_ENABLE                 1
#define PREFER_ARM64_32_BINARIES
#define PEXPERT_NO_3X_IMAGES           1
#endif /* ARM64_BOARD_CONFIG_T8006 */

#ifdef ARM64_BOARD_CONFIG_T8027
#include <pexpert/arm64/H11.h>

#define MAX_L2_CLINE                   7
#define MAX_CPUS                       8
#define MAX_CPU_CLUSTERS               2

#define XNU_MONITOR                    1 /* Secure pmap runtime */
#define XNU_MONITOR_T8020_DART         1 /* T8020 DART plugin for secure pmap runtime */
#define T8020_DART_ALLOW_BYPASS        (1 << 1) /* DART allows translation bypass in certain cases */
#define XNU_MONITOR_NVME_PPL           1 /* NVMe PPL plugin for secure pmap runtime */
#define XNU_MONITOR_ANS2_SART          1 /* ANS2 SART plugin for secure pmap runtime */
#define PMAP_CS                        1
#define PMAP_CS_ENABLE                 1
#endif  /* ARM64_BOARD_CONFIG_T8027 */

#ifdef ARM64_BOARD_CONFIG_T8028
#include <pexpert/arm64/H11.h>

#define MAX_L2_CLINE                   7
#define MAX_CPUS                       8
#define MAX_CPU_CLUSTERS               2

#define XNU_MONITOR                    1 /* Secure pmap runtime */
#define XNU_MONITOR_T8020_DART         1 /* T8020 DART plugin for secure pmap runtime */
#define T8020_DART_ALLOW_BYPASS        (1 << 1) /* DART allows translation bypass in certain cases */
#define XNU_MONITOR_NVME_PPL           1 /* NVMe PPL plugin for secure pmap runtime */
#define XNU_MONITOR_ANS2_SART          1 /* ANS2 SART plugin for secure pmap runtime */
#define PMAP_CS                        1
#define PMAP_CS_ENABLE                 1
#endif  /* ARM64_BOARD_CONFIG_T8028 */

#ifdef ARM64_BOARD_CONFIG_T8030
#include <pexpert/arm64/H12.h>

#define MAX_L2_CLINE                   7
#define MAX_CPUS                       6
#define MAX_CPU_CLUSTERS               2

#define XNU_MONITOR                    1 /* Secure pmap runtime */
#define XNU_MONITOR_T8020_DART         1 /* T8020 DART plugin for secure pmap runtime */
#define T8020_DART_ALLOW_BYPASS        (1 << 1) /* DART allows translation bypass in certain cases */
#define XNU_MONITOR_NVME_PPL           1 /* NVMe PPL plugin for secure pmap runtime */
#define XNU_MONITOR_ANS2_SART          1 /* ANS2 SART plugin for secure pmap runtime */
#define XNU_MONITOR_UAT_PPL            1 /* UAT PPL plugin for secure pmap runtime */
#define PMAP_CS                        1
#define PMAP_CS_ENABLE                 1
#endif  /* ARM64_BOARD_CONFIG_T8030 */


#ifdef ARM64_BOARD_CONFIG_BCM2837
#include <pexpert/arm64/BCM2837.h>

#define MAX_L2_CLINE                   6
#define MAX_CPUS                       4
#define MAX_CPU_CLUSTERS               1

#define CORE_NCTRS                     8 /* Placeholder; KPC is not enabled for this target */
#endif  /* ARM64_BOARD_CONFIG_BCM2837 */

#ifndef HAS_UNCORE_CTRS
#undef UNCORE_VERSION
#undef UNCORE_PER_CLUSTER
#undef UNCORE_NCTRS
#endif

#if MAX_CPU_CLUSTERS == 1
#undef __ARM_AMP__
#endif

#ifndef MAX_CPU_CLUSTER_PHY_ID
#define MAX_CPU_CLUSTER_PHY_ID (MAX_CPU_CLUSTERS - 1)
#endif

#ifdef PREFER_ARM64_32_BINARIES
#define PREFERRED_USER_CPU_TYPE CPU_TYPE_ARM64_32
#define PREFERRED_USER_CPU_SUBTYPE CPU_SUBTYPE_ARM64_32_V8
#endif

#endif /* ! _PEXPERT_ARM_BOARD_CONFIG_H */
Commit	Line	Data
5ba3f43e	1	/*
f427ee49	2	* Copyright (c) 2007-2020 Apple Inc. All rights reserved.
5ba3f43e A	3	* Copyright (c) 2005-2006 Apple Computer, Inc. All rights reserved.
	4	*/
	5	#ifndef _PEXPERT_ARM_BOARD_CONFIG_H
	6	#define _PEXPERT_ARM_BOARD_CONFIG_H
	7
d9a64523 A	8	#include <mach/machine.h>
d9a64523 A	9
f427ee49 A	10	/*
	11	* Per-SoC configuration. General order is:
	12	*
	13	* CPU type
	14	* CPU configuration
	15	* CPU feature disables / workarounds
	16	* CPU topology
	17	* Other platform configuration (e.g. DARTs, PPL)
	18	*
	19	* This should answer the question: "what's unique about this SoC?"
	20	*
	21	* arm64/H*.h should answer the question: "what's unique about this CPU core?"
	22	*
	23	* For __ARM_AMP__ systems that have different cache line sizes on different
	24	* clusters, MAX_L2_CLINE must reflect the largest L2 cache line size
	25	* across all clusters.
	26	*/
	27
5ba3f43e A	28
5ba3f43e A	29	#ifdef ARM64_BOARD_CONFIG_T7000
f427ee49 A	30	#include <pexpert/arm64/H7.h>
	31
	32	#define MAX_L2_CLINE 6
	33	#define MAX_CPUS 3
	34	#define MAX_CPU_CLUSTERS 1
5ba3f43e A	35	#endif /* ARM64_BOARD_CONFIG_T7000 */
	36
	37	#ifdef ARM64_BOARD_CONFIG_T7001
f427ee49 A	38	#include <pexpert/arm64/H7.h>
	39
	40	#define MAX_L2_CLINE 6
	41	#define MAX_CPUS 3
	42	#define MAX_CPU_CLUSTERS 1
5ba3f43e A	43	#endif /* ARM64_BOARD_CONFIG_T7001 */
	44
	45	#ifdef ARM64_BOARD_CONFIG_S8000
f427ee49 A	46	#include <pexpert/arm64/H8.h>
	47	#define MAX_CPUS 2
	48	#define MAX_CPU_CLUSTERS 1
5ba3f43e A	49	/*
	50	* The L2 size for twister is in fact 3MB, not 4MB; we round up due
	51	* to the code being architected for power of 2 cache sizes, and rely
	52	* on the expected behavior that out of bounds operations will be
	53	* ignored.
	54	*/
f427ee49	55	#define MAX_L2_CLINE 6
5ba3f43e A	56	#endif /* ARM64_BOARD_CONFIG_S8000 */
	57
	58	#ifdef ARM64_BOARD_CONFIG_S8001
f427ee49 A	59	#include <pexpert/arm64/H8.h>
	60	#define MAX_CPUS 2
	61	#define MAX_CPU_CLUSTERS 1
5ba3f43e A	62	/*
	63	* The L2 size for twister is in fact 3MB, not 4MB; we round up due
	64	* to the code being architected for power of 2 cache sizes, and rely
	65	* on the expect behavior that out of bounds operations will be
	66	* ignored.
	67	*/
f427ee49	68	#define MAX_L2_CLINE 6
5ba3f43e A	69	#endif /* ARM64_BOARD_CONFIG_S8001 */
	70
	71	#ifdef ARM64_BOARD_CONFIG_T8010
f427ee49 A	72	#include <pexpert/arm64/H9.h>
	73	#define MAX_CPUS 3
	74	#define MAX_CPU_CLUSTERS 1
5ba3f43e A	75	/*
	76	* The L2 size for hurricane/zephyr is in fact 3MB, not 4MB; we round up due
	77	* to the code being architected for power of 2 cache sizes, and rely
	78	* on the expect behavior that out of bounds operations will be
	79	* ignored.
	80	*/
f427ee49 A	81	#define MAX_L2_CLINE 7
f427ee49 A	82
d9a64523	83	#if DEVELOPMENT \|\| DEBUG
f427ee49 A	84	#define PMAP_CS 1
f427ee49 A	85	#define PMAP_CS_ENABLE 0
d9a64523	86	#endif
5ba3f43e A	87	#endif /* ARM64_BOARD_CONFIG_T8010 */
	88
	89	#ifdef ARM64_BOARD_CONFIG_T8011
f427ee49 A	90	#include <pexpert/arm64/H9.h>
	91
	92	#define MAX_L2_CLINE 7
	93	#define MAX_CPUS 3
	94	#define MAX_CPU_CLUSTERS 1
	95
d9a64523	96	#if DEVELOPMENT \|\| DEBUG
f427ee49 A	97	#define PMAP_CS 1
f427ee49 A	98	#define PMAP_CS_ENABLE 0
d9a64523	99	#endif
5ba3f43e A	100	#endif /* ARM64_BOARD_CONFIG_T8011 */
5ba3f43e A	101
d9a64523	102	#ifdef ARM64_BOARD_CONFIG_T8015
f427ee49 A	103	#include <pexpert/arm64/H10.h>
	104
	105	#define MAX_L2_CLINE 7
	106	#define MAX_CPUS 6
	107	#define MAX_CPU_CLUSTERS 2
	108
	109	#define BROKEN_FRIGGING_SLEEP 1 /* Spurious wake: See rdar://problem/29762505 */
	110
d9a64523	111	#if DEVELOPMENT \|\| DEBUG
f427ee49 A	112	#define PMAP_CS 1
f427ee49 A	113	#define PMAP_CS_ENABLE 0
d9a64523 A	114	#endif
	115	#endif /* ARM64_BOARD_CONFIG_T8015 */
	116
c6bf4f31	117	#ifdef ARM64_BOARD_CONFIG_T8020
f427ee49 A	118	#include <pexpert/arm64/H11.h>
	119
	120	#define MAX_L2_CLINE 7
	121	#define MAX_CPUS 8
	122	#define MAX_CPU_CLUSTERS 2
	123
	124	#define XNU_MONITOR 1 /* Secure pmap runtime */
	125	#define XNU_MONITOR_T8020_DART 1 /* T8020 DART plugin for secure pmap runtime */
	126	#define T8020_DART_ALLOW_BYPASS (1 << 1) /* DART allows translation bypass in certain cases */
	127	#define XNU_MONITOR_NVME_PPL 1 /* NVMe PPL plugin for secure pmap runtime */
	128	#define XNU_MONITOR_ANS2_SART 1 /* ANS2 SART plugin for secure pmap runtime */
	129	#define PMAP_CS 1
	130	#define PMAP_CS_ENABLE 1
c6bf4f31	131	#endif /* ARM64_BOARD_CONFIG_T8020 */
5ba3f43e	132
c6bf4f31 A	133	#ifdef ARM64_BOARD_CONFIG_T8006
	134	/*
	135	* The T8006 consists of 2 Tempest cores (i.e. T8020 eCores) and for most
	136	* of our purposes here may be considered a functional subset of T8020.
	137	*/
f427ee49 A	138	#include <pexpert/arm64/H11.h>
	139
	140	#undef HAS_UNCORE_CTRS
	141	#ifdef XNU_TARGET_OS_WATCH // This check might be redundant
	142	#undef __APRR_SHADOW_SUPPORTED__
	143	#endif
	144
	145	#define MAX_L2_CLINE 7
	146	#define MAX_CPUS 2
	147	#define MAX_CPU_CLUSTERS 1
	148
	149	#define XNU_MONITOR 1 /* Secure pmap runtime */
	150	#define XNU_MONITOR_T8020_DART 1 /* T8020 DART plugin for secure pmap runtime */
	151	#define T8020_DART_ALLOW_BYPASS (1 << 1) /* DART allows translation bypass in certain cases */
	152	#define XNU_MONITOR_NVME_PPL 1 /* NVMe PPL plugin for secure pmap runtime */
	153	#define XNU_MONITOR_ANS2_SART 1 /* ANS2 SART plugin for secure pmap runtime */
	154	#define PMAP_CS 1
	155	#define PMAP_CS_ENABLE 1
	156	#define PREFER_ARM64_32_BINARIES
	157	#define PEXPERT_NO_3X_IMAGES 1
c6bf4f31	158	#endif /* ARM64_BOARD_CONFIG_T8006 */
5ba3f43e	159
c6bf4f31	160	#ifdef ARM64_BOARD_CONFIG_T8027
f427ee49 A	161	#include <pexpert/arm64/H11.h>
	162
	163	#define MAX_L2_CLINE 7
	164	#define MAX_CPUS 8
	165	#define MAX_CPU_CLUSTERS 2
	166
	167	#define XNU_MONITOR 1 /* Secure pmap runtime */
	168	#define XNU_MONITOR_T8020_DART 1 /* T8020 DART plugin for secure pmap runtime */
	169	#define T8020_DART_ALLOW_BYPASS (1 << 1) /* DART allows translation bypass in certain cases */
	170	#define XNU_MONITOR_NVME_PPL 1 /* NVMe PPL plugin for secure pmap runtime */
	171	#define XNU_MONITOR_ANS2_SART 1 /* ANS2 SART plugin for secure pmap runtime */
	172	#define PMAP_CS 1
	173	#define PMAP_CS_ENABLE 1
c6bf4f31	174	#endif /* ARM64_BOARD_CONFIG_T8027 */
5ba3f43e	175
c6bf4f31	176	#ifdef ARM64_BOARD_CONFIG_T8028
f427ee49 A	177	#include <pexpert/arm64/H11.h>
	178
	179	#define MAX_L2_CLINE 7
	180	#define MAX_CPUS 8
	181	#define MAX_CPU_CLUSTERS 2
	182
	183	#define XNU_MONITOR 1 /* Secure pmap runtime */
	184	#define XNU_MONITOR_T8020_DART 1 /* T8020 DART plugin for secure pmap runtime */
	185	#define T8020_DART_ALLOW_BYPASS (1 << 1) /* DART allows translation bypass in certain cases */
	186	#define XNU_MONITOR_NVME_PPL 1 /* NVMe PPL plugin for secure pmap runtime */
	187	#define XNU_MONITOR_ANS2_SART 1 /* ANS2 SART plugin for secure pmap runtime */
	188	#define PMAP_CS 1
	189	#define PMAP_CS_ENABLE 1
c6bf4f31	190	#endif /* ARM64_BOARD_CONFIG_T8028 */
5ba3f43e	191
c6bf4f31	192	#ifdef ARM64_BOARD_CONFIG_T8030
f427ee49 A	193	#include <pexpert/arm64/H12.h>
	194
	195	#define MAX_L2_CLINE 7
	196	#define MAX_CPUS 6
	197	#define MAX_CPU_CLUSTERS 2
	198
	199	#define XNU_MONITOR 1 /* Secure pmap runtime */
	200	#define XNU_MONITOR_T8020_DART 1 /* T8020 DART plugin for secure pmap runtime */
	201	#define T8020_DART_ALLOW_BYPASS (1 << 1) /* DART allows translation bypass in certain cases */
	202	#define XNU_MONITOR_NVME_PPL 1 /* NVMe PPL plugin for secure pmap runtime */
	203	#define XNU_MONITOR_ANS2_SART 1 /* ANS2 SART plugin for secure pmap runtime */
	204	#define XNU_MONITOR_UAT_PPL 1 /* UAT PPL plugin for secure pmap runtime */
	205	#define PMAP_CS 1
	206	#define PMAP_CS_ENABLE 1
c6bf4f31	207	#endif /* ARM64_BOARD_CONFIG_T8030 */
5ba3f43e	208
cb323159 A	209
	210
	211
f427ee49 A	212
f427ee49 A	213
d9a64523	214	#ifdef ARM64_BOARD_CONFIG_BCM2837
d9a64523	215	#include <pexpert/arm64/BCM2837.h>
f427ee49 A	216
	217	#define MAX_L2_CLINE 6
	218	#define MAX_CPUS 4
	219	#define MAX_CPU_CLUSTERS 1
	220
	221	#define CORE_NCTRS 8 /* Placeholder; KPC is not enabled for this target */
d9a64523 A	222	#endif /* ARM64_BOARD_CONFIG_BCM2837 */
d9a64523 A	223
f427ee49 A	224	#ifndef HAS_UNCORE_CTRS
	225	#undef UNCORE_VERSION
	226	#undef UNCORE_PER_CLUSTER
	227	#undef UNCORE_NCTRS
	228	#endif
	229
	230	#if MAX_CPU_CLUSTERS == 1
	231	#undef __ARM_AMP__
	232	#endif
	233
	234	#ifndef MAX_CPU_CLUSTER_PHY_ID
	235	#define MAX_CPU_CLUSTER_PHY_ID (MAX_CPU_CLUSTERS - 1)
	236	#endif
	237
	238	#ifdef PREFER_ARM64_32_BINARIES
	239	#define PREFERRED_USER_CPU_TYPE CPU_TYPE_ARM64_32
	240	#define PREFERRED_USER_CPU_SUBTYPE CPU_SUBTYPE_ARM64_32_V8
	241	#endif
	242
5ba3f43e	243	#endif /* ! _PEXPERT_ARM_BOARD_CONFIG_H */