projects / apple / xnu.git / blame
| Commit | Line | Data |
|---|---|---|
| 5ba3f43e | 1 | /* |
| cb323159 | 2 | * Copyright (c) 2007-2018 Apple Inc. All rights reserved. |
| 5ba3f43e A |
3 | * |
| 4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@ | |
| 5 | * | |
| 6 | * This file contains Original Code and/or Modifications of Original Code | |
| 7 | * as defined in and that are subject to the Apple Public Source License | |
| 8 | * Version 2.0 (the 'License'). You may not use this file except in | |
| 9 | * compliance with the License. The rights granted to you under the License | |
| 10 | * may not be used to create, or enable the creation or redistribution of, | |
| 11 | * unlawful or unlicensed copies of an Apple operating system, or to | |
| 12 | * circumvent, violate, or enable the circumvention or violation of, any | |
| 13 | * terms of an Apple operating system software license agreement. | |
| 14 | * | |
| 15 | * Please obtain a copy of the License at | |
| 16 | * http://www.opensource.apple.com/apsl/ and read it before using this file. | |
| 17 | * | |
| 18 | * The Original Code and all software distributed under the License are | |
| 19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER | |
| 20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES, | |
| 21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY, | |
| 22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT. | |
| 23 | * Please see the License for the specific language governing rights and | |
| 24 | * limitations under the License. | |
| 25 | * | |
| 26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@ | |
| 27 | */ | |
| 28 | /* | |
| 29 | * @OSF_COPYRIGHT@ | |
| 30 | */ | |
| 31 | /* CMU_ENDHIST */ | |
| 0a7de745 | 32 | /* |
| 5ba3f43e A |
33 | * Mach Operating System |
| 34 | * Copyright (c) 1991,1990 Carnegie Mellon University | |
| 35 | * All Rights Reserved. | |
| 0a7de745 | 36 | * |
| 5ba3f43e A |
37 | * Permission to use, copy, modify and distribute this software and its |
| 38 | * documentation is hereby granted, provided that both the copyright | |
| 39 | * notice and this permission notice appear in all copies of the | |
| 40 | * software, derivative works or modified versions, and any portions | |
| 41 | * thereof, and that both notices appear in supporting documentation. | |
| 0a7de745 | 42 | * |
| 5ba3f43e A |
43 | * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" |
| 44 | * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR | |
| 45 | * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. | |
| 0a7de745 | 46 | * |
| 5ba3f43e | 47 | * Carnegie Mellon requests users of this software to return to |
| 0a7de745 | 48 | * |
| 5ba3f43e A |
49 | * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU |
| 50 | * School of Computer Science | |
| 51 | * Carnegie Mellon University | |
| 52 | * Pittsburgh PA 15213-3890 | |
| 0a7de745 | 53 | * |
| 5ba3f43e A |
54 | * any improvements or extensions that they make and grant Carnegie Mellon |
| 55 | * the rights to redistribute these changes. | |
| 56 | */ | |
| 57 | ||
| 58 | /* | |
| 59 | */ | |
| 60 | ||
| 61 | /* | |
| 62 | * Processor registers for ARM | |
| 63 | */ | |
| 0a7de745 A |
64 | #ifndef _ARM_PROC_REG_H_ |
| 65 | #define _ARM_PROC_REG_H_ | |
| 5ba3f43e A |
66 | |
| 67 | #if defined (__arm64__) | |
| 68 | #include <pexpert/arm64/board_config.h> | |
| 69 | #elif defined (__arm__) | |
| 70 | #include <pexpert/arm/board_config.h> | |
| 71 | #endif | |
| 72 | ||
| 73 | #if defined (ARMA7) | |
| cb323159 A |
74 | #define __ARM_ARCH__ 7 |
| 75 | #define __ARM_SUB_ARCH__ CPU_ARCH_ARMv7k | |
| 76 | #define __ARM_VMSA__ 7 | |
| 77 | #define __ARM_VFP__ 3 | |
| 5ba3f43e | 78 | #if defined(__XNU_UP__) |
| cb323159 | 79 | #define __ARM_SMP__ 0 |
| 5ba3f43e | 80 | #else |
| cb323159 | 81 | #define __ARM_SMP__ 1 |
| 5ba3f43e A |
82 | /* For SMP kernels, force physical aperture to be mapped at PTE level so that its mappings |
| 83 | * can be updated to reflect cache attribute changes on alias mappings. This prevents | |
| 84 | * prefetched physical aperture cachelines from becoming dirty in L1 due to a write to | |
| 85 | * an uncached alias mapping on the same core. Subsequent uncached writes from another | |
| 86 | * core may not snoop this line, and the dirty line may end up being evicted later to | |
| 87 | * effectively overwrite the uncached writes from other cores. */ | |
| cb323159 | 88 | #define __ARM_PTE_PHYSMAP__ 1 |
| 5ba3f43e A |
89 | #endif |
| 90 | /* __ARMA7_SMP__ controls whether we are consistent with the A7 MP_CORE spec; needed because entities other than | |
| 91 | * the xnu-managed processors may need to snoop our cache operations. | |
| 92 | */ | |
| cb323159 A |
93 | #define __ARMA7_SMP__ 1 |
| 94 | #define __ARM_COHERENT_CACHE__ 1 | |
| 95 | #define __ARM_DEBUG__ 7 | |
| 96 | #define __ARM_USER_PROTECT__ 1 | |
| 97 | #define __ARM_TIME_TIMEBASE_ONLY__ 1 | |
| 5ba3f43e A |
98 | |
| 99 | #elif defined (APPLETYPHOON) | |
| cb323159 A |
100 | #define __ARM_ARCH__ 8 |
| 101 | #define __ARM_VMSA__ 8 | |
| 102 | #define __ARM_SMP__ 1 | |
| 103 | #define __ARM_VFP__ 4 | |
| 104 | #define __ARM_COHERENT_CACHE__ 1 | |
| 105 | #define __ARM_COHERENT_IO__ 1 | |
| 106 | #define __ARM_IC_NOALIAS_ICACHE__ 1 | |
| 107 | #define __ARM_DEBUG__ 7 | |
| 108 | #define __ARM_ENABLE_SWAP__ 1 | |
| 5ba3f43e | 109 | #define __ARM_V8_CRYPTO_EXTENSIONS__ 1 |
| cb323159 A |
110 | #define __ARM64_PMAP_SUBPAGE_L1__ 1 |
| 111 | #define __ARM_KERNEL_PROTECT__ 1 | |
| 5ba3f43e A |
112 | |
| 113 | #elif defined (APPLETWISTER) | |
| cb323159 A |
114 | #define __ARM_ARCH__ 8 |
| 115 | #define __ARM_VMSA__ 8 | |
| 116 | #define __ARM_SMP__ 1 | |
| 117 | #define __ARM_VFP__ 4 | |
| 118 | #define __ARM_COHERENT_CACHE__ 1 | |
| 119 | #define __ARM_COHERENT_IO__ 1 | |
| 120 | #define __ARM_IC_NOALIAS_ICACHE__ 1 | |
| 121 | #define __ARM_DEBUG__ 7 | |
| 122 | #define __ARM_ENABLE_SWAP__ 1 | |
| 5ba3f43e | 123 | #define __ARM_V8_CRYPTO_EXTENSIONS__ 1 |
| cb323159 A |
124 | #define __ARM_16K_PG__ 1 |
| 125 | #define __ARM64_PMAP_SUBPAGE_L1__ 1 | |
| 126 | #define __ARM_KERNEL_PROTECT__ 1 | |
| 5ba3f43e A |
127 | |
| 128 | #elif defined (APPLEHURRICANE) | |
| cb323159 A |
129 | #define __ARM_ARCH__ 8 |
| 130 | #define __ARM_VMSA__ 8 | |
| 131 | #define __ARM_SMP__ 1 | |
| 132 | #define __ARM_VFP__ 4 | |
| 133 | #define __ARM_COHERENT_CACHE__ 1 | |
| 134 | #define __ARM_COHERENT_IO__ 1 | |
| 135 | #define __ARM_IC_NOALIAS_ICACHE__ 1 | |
| 136 | #define __ARM_DEBUG__ 7 | |
| 137 | #define __ARM_ENABLE_SWAP__ 1 | |
| 5ba3f43e | 138 | #define __ARM_V8_CRYPTO_EXTENSIONS__ 1 |
| cb323159 A |
139 | #define __ARM_16K_PG__ 1 |
| 140 | #define __ARM64_PMAP_SUBPAGE_L1__ 1 | |
| 141 | #define __ARM_KERNEL_PROTECT__ 1 | |
| 142 | #define __ARM_GLOBAL_SLEEP_BIT__ 1 | |
| 143 | #define __ARM_PAN_AVAILABLE__ 1 | |
| 5ba3f43e | 144 | |
| d9a64523 | 145 | #elif defined (APPLEMONSOON) |
| cb323159 A |
146 | #define __ARM_ARCH__ 8 |
| 147 | #define __ARM_VMSA__ 8 | |
| 148 | #define __ARM_SMP__ 1 | |
| 149 | #define __ARM_AMP__ 1 | |
| 150 | #define __ARM_VFP__ 4 | |
| 151 | #define __ARM_COHERENT_CACHE__ 1 | |
| 152 | #define __ARM_COHERENT_IO__ 1 | |
| 153 | #define __ARM_IC_NOALIAS_ICACHE__ 1 | |
| 154 | #define __ARM_DEBUG__ 7 | |
| 155 | #define __ARM_ENABLE_SWAP__ 1 | |
| 156 | #define __ARM_V8_CRYPTO_EXTENSIONS__ 1 | |
| 157 | #define __ARM_16K_PG__ 1 | |
| 158 | #define __ARM64_PMAP_SUBPAGE_L1__ 1 | |
| 159 | #define __ARM_KERNEL_PROTECT__ 1 | |
| 160 | #define __ARM_GLOBAL_SLEEP_BIT__ 1 | |
| 161 | #define __ARM_PAN_AVAILABLE__ 1 | |
| 162 | #define __ARM_WKDM_ISA_AVAILABLE__ 1 | |
| 163 | #define __PLATFORM_WKDM_ALIGNMENT_MASK__ (0x3FULL) | |
| d9a64523 | 164 | #define __PLATFORM_WKDM_ALIGNMENT_BOUNDARY__ (64) |
| cb323159 | 165 | #define __ARM_CLUSTER_COUNT__ 2 |
| d9a64523 | 166 | |
| c6bf4f31 A |
167 | #elif defined (APPLEVORTEX) |
| 168 | #define __ARM_ARCH__ 8 | |
| 169 | #define __ARM_VMSA__ 8 | |
| 170 | #define __ARM_SMP__ 1 | |
| 171 | #define __ARM_VFP__ 4 | |
| 172 | #define __ARM_COHERENT_CACHE__ 1 | |
| 173 | #define __ARM_COHERENT_IO__ 1 | |
| 174 | #define __ARM_IC_NOALIAS_ICACHE__ 1 | |
| 175 | #define __ARM_DEBUG__ 7 | |
| 176 | #define __ARM_ENABLE_SWAP__ 1 | |
| 177 | #define __ARM_V8_CRYPTO_EXTENSIONS__ 1 | |
| 178 | #define __ARM_16K_PG__ 1 | |
| 179 | #define __ARM64_PMAP_SUBPAGE_L1__ 1 | |
| 180 | #define __ARM_GLOBAL_SLEEP_BIT__ 1 | |
| 181 | #define __ARM_PAN_AVAILABLE__ 1 | |
| 182 | #define __ARM_WKDM_ISA_AVAILABLE__ 1 | |
| 183 | #define __PLATFORM_WKDM_ALIGNMENT_MASK__ (0x3FULL) | |
| 184 | #define __PLATFORM_WKDM_ALIGNMENT_BOUNDARY__ (64) | |
| 185 | #define __ARM_CLUSTER_COUNT__ 2 | |
| 186 | ||
| 187 | #elif defined (APPLELIGHTNING) | |
| 188 | #define __ARM_ARCH__ 8 | |
| 189 | #define __ARM_VMSA__ 8 | |
| 190 | #define __ARM_SMP__ 1 | |
| 191 | #define __ARM_AMP__ 1 | |
| 192 | #define __ARM_VFP__ 4 | |
| 193 | #define __ARM_COHERENT_CACHE__ 1 | |
| 194 | #define __ARM_COHERENT_IO__ 1 | |
| 195 | #define __ARM_IC_NOALIAS_ICACHE__ 1 | |
| 196 | #define __ARM_DEBUG__ 7 | |
| 197 | #define __ARM_ENABLE_SWAP__ 1 | |
| 198 | #define __ARM_V8_CRYPTO_EXTENSIONS__ 1 | |
| 199 | #define __ARM_16K_PG__ 1 | |
| 200 | #define __ARM64_PMAP_SUBPAGE_L1__ 1 | |
| 201 | #define __ARM_GLOBAL_SLEEP_BIT__ 1 | |
| 202 | #define __ARM_PAN_AVAILABLE__ 1 | |
| 203 | #define __ARM_WKDM_ISA_AVAILABLE__ 1 | |
| 204 | #define __PLATFORM_WKDM_ALIGNMENT_MASK__ (0x3FULL) | |
| 205 | #define __PLATFORM_WKDM_ALIGNMENT_BOUNDARY__ (64) | |
| 206 | #define __ARM_CLUSTER_COUNT__ 2 | |
| 207 | #define | |
| 208 | #define __APCFG_SUPPORTED__ 1 | |
| 209 | #define __ARM_RANGE_TLBI__ 1 | |
| 210 | ||
| d9a64523 | 211 | #elif defined (BCM2837) |
| cb323159 A |
212 | #define __ARM_ARCH__ 8 |
| 213 | #define __ARM_VMSA__ 8 | |
| 214 | #define __ARM_SMP__ 1 | |
| 215 | #define __ARM_VFP__ 4 | |
| 216 | #define __ARM_COHERENT_CACHE__ 1 | |
| 217 | #define __ARM_DEBUG__ 7 | |
| d9a64523 | 218 | #define __ARM64_PMAP_SUBPAGE_L1__ 1 |
| 5ba3f43e A |
219 | #else |
| 220 | #error processor not supported | |
| 221 | #endif | |
| 222 | ||
| cb323159 A |
223 | #if __ARM_42BIT_PA_SPACE__ |
| 224 | /* For now, force the issue! */ | |
| 225 | #undef __ARM64_PMAP_SUBPAGE_L1__ | |
| 226 | #endif /* __ARM_42BIT_PA_SPACE__ */ | |
| 227 | ||
| d9a64523 A |
228 | #if __ARM_KERNEL_PROTECT__ |
| 229 | /* | |
| 230 | * This feature is not currently implemented for 32-bit ARM CPU architectures. | |
| 231 | * A discussion of this feature for 64-bit ARM CPU architectures can be found | |
| 232 | * in the ARM64 version of this file. | |
| 233 | */ | |
| 234 | #if __arm__ | |
| 235 | #error __ARM_KERNEL_PROTECT__ is not supported on ARM32 | |
| cb323159 | 236 | #endif /* __arm__ */ |
| d9a64523 A |
237 | #endif /* __ARM_KERNEL_PROTECT__ */ |
| 238 | ||
| 5ba3f43e A |
239 | #if defined(ARM_BOARD_WFE_TIMEOUT_NS) |
| 240 | #define __ARM_ENABLE_WFE_ 1 | |
| cb323159 | 241 | #else /* defined(ARM_BOARD_WFE_TIMEOUT_NS) */ |
| 5ba3f43e | 242 | #define __ARM_ENABLE_WFE_ 0 |
| cb323159 | 243 | #endif /* defined(ARM_BOARD_WFE_TIMEOUT_NS) */ |
| 5ba3f43e | 244 | |
| cb323159 A |
245 | /* |
| 246 | * The clutch scheduler is enabled only on non-AMP platforms for now. | |
| 247 | */ | |
| 248 | #if !__ARM_AMP__ && CONFIG_CLUTCH | |
| 249 | #define CONFIG_SCHED_CLUTCH 1 | |
| 250 | #else /* !__ARM_AMP__ && CONFIG_CLUTCH */ | |
| 251 | #define CONFIG_SCHED_CLUTCH 0 | |
| 252 | #endif /* !__ARM_AMP__ && CONFIG_CLUTCH */ | |
| 253 | ||
| 254 | #if __ARM_AMP__ || CONFIG_SCHED_CLUTCH | |
| 255 | #define CONFIG_THREAD_GROUPS 1 | |
| 256 | #else /* __ARM_AMP__ || CONFIG_SCHED_CLUTCH */ | |
| 5ba3f43e | 257 | #define CONFIG_THREAD_GROUPS 0 |
| cb323159 | 258 | #endif |
| 5ba3f43e | 259 | |
| cb323159 | 260 | #ifdef XNU_KERNEL_PRIVATE |
| 5ba3f43e | 261 | |
| cb323159 A |
262 | #if __ARM_VFP__ |
| 263 | #define ARM_VFP_DEBUG 0 | |
| 264 | #endif /* __ARM_VFP__ */ | |
| 5ba3f43e | 265 | |
| cb323159 | 266 | #endif /* XNU_KERNEL_PRIVATE */ |
| 5ba3f43e A |
267 | |
| 268 | ||
| 269 | ||
| 270 | /* | |
| 271 | * FSR registers | |
| 272 | * | |
| 273 | * CPSR: Current Program Status Register | |
| 274 | * SPSR: Saved Program Status Registers | |
| 275 | * | |
| 276 | * 31 30 29 28 27 24 19 16 9 8 7 6 5 4 0 | |
| 277 | * +-----------------------------------------------------------+ | |
| 278 | * | N| Z| C| V| Q|...| J|...|GE[3:0]|...| E| A| I| F| T| MODE | | |
| 279 | * +-----------------------------------------------------------+ | |
| 280 | */ | |
| 281 | ||
| 0a7de745 A |
282 | /* |
| 283 | * Flags | |
| 5ba3f43e | 284 | */ |
| cb323159 A |
285 | #define PSR_NF 0x80000000 /* Negative/Less than */ |
| 286 | #define PSR_ZF 0x40000000 /* Zero */ | |
| 287 | #define PSR_CF 0x20000000 /* Carry/Borrow/Extend */ | |
| 288 | #define PSR_VF 0x10000000 /* Overflow */ | |
| 289 | #define PSR_QF 0x08000000 /* saturation flag (QADD ARMv5) */ | |
| 5ba3f43e A |
290 | |
| 291 | /* | |
| 292 | * Modified execution mode flags | |
| 293 | */ | |
| cb323159 A |
294 | #define PSR_JF 0x01000000 /* Jazelle flag (BXJ ARMv5) */ |
| 295 | #define PSR_EF 0x00000200 /* mixed-endian flag (SETEND ARMv6) */ | |
| 296 | #define PSR_AF 0x00000100 /* precise abort flag (ARMv6) */ | |
| 297 | #define PSR_TF 0x00000020 /* thumb flag (BX ARMv4T) */ | |
| 298 | #define PSR_TFb 5 /* thumb flag (BX ARMv4T) */ | |
| 5ba3f43e A |
299 | |
| 300 | /* | |
| 301 | * Interrupts | |
| 302 | */ | |
| cb323159 A |
303 | #define PSR_IRQFb 7 /* IRQ : 0 = IRQ enable */ |
| 304 | #define PSR_IRQF 0x00000080 /* IRQ : 0 = IRQ enable */ | |
| 305 | #define PSR_FIQF 0x00000040 /* FIQ : 0 = FIQ enable */ | |
| 5ba3f43e A |
306 | |
| 307 | /* | |
| 308 | * CPU mode | |
| 309 | */ | |
| cb323159 A |
310 | #define PSR_USER_MODE 0x00000010 /* User mode */ |
| 311 | #define PSR_FIQ_MODE 0x00000011 /* FIQ mode */ | |
| 312 | #define PSR_IRQ_MODE 0x00000012 /* IRQ mode */ | |
| 313 | #define PSR_SVC_MODE 0x00000013 /* Supervisor mode */ | |
| 314 | #define PSR_ABT_MODE 0x00000017 /* Abort mode */ | |
| 315 | #define PSR_UND_MODE 0x0000001B /* Undefined mode */ | |
| 5ba3f43e | 316 | |
| cb323159 A |
317 | #define PSR_MODE_MASK 0x0000001F |
| 318 | #define PSR_IS_KERNEL(psr) (((psr) & PSR_MODE_MASK) != PSR_USER_MODE) | |
| 319 | #define PSR_IS_USER(psr) (((psr) & PSR_MODE_MASK) == PSR_USER_MODE) | |
| 5ba3f43e | 320 | |
| cb323159 A |
321 | #define PSR_USERDFLT PSR_USER_MODE |
| 322 | #define PSR_USER_MASK (PSR_AF | PSR_IRQF | PSR_FIQF | PSR_MODE_MASK) | |
| 323 | #define PSR_USER_SET PSR_USER_MODE | |
| 5ba3f43e | 324 | |
| cb323159 | 325 | #define PSR_INTMASK PSR_IRQF /* Interrupt disable */ |
| 5ba3f43e A |
326 | |
| 327 | /* | |
| 328 | * FPEXC: Floating-Point Exception Register | |
| 329 | */ | |
| 330 | ||
| cb323159 A |
331 | #define FPEXC_EX 0x80000000 /* Exception status */ |
| 332 | #define FPEXC_EX_BIT 31 | |
| 333 | #define FPEXC_EN 0x40000000 /* VFP : 1 = EN enable */ | |
| 334 | #define FPEXC_EN_BIT 30 | |
| 5ba3f43e A |
335 | |
| 336 | ||
| 337 | /* | |
| 338 | * FPSCR: Floating-point Status and Control Register | |
| 339 | */ | |
| 340 | ||
| cb323159 A |
341 | #define FPSCR_DN 0x02000000 /* Default NaN */ |
| 342 | #define FPSCR_FZ 0x01000000 /* Flush to zero */ | |
| 5ba3f43e | 343 | |
| cb323159 | 344 | #define FPSCR_DEFAULT FPSCR_DN | FPSCR_FZ |
| 5ba3f43e A |
345 | |
| 346 | ||
| 347 | /* | |
| 0a7de745 | 348 | * FSR registers |
| 5ba3f43e A |
349 | * |
| 350 | * IFSR: Instruction Fault Status Register | |
| 351 | * DFSR: Data Fault Status Register | |
| 352 | */ | |
| cb323159 A |
353 | #define FSR_ALIGN 0x00000001 /* Alignment */ |
| 354 | #define FSR_DEBUG 0x00000002 /* Debug (watch/break) */ | |
| 355 | #define FSR_ICFAULT 0x00000004 /* Fault on instruction cache maintenance */ | |
| 356 | #define FSR_SFAULT 0x00000005 /* Translation Section */ | |
| 357 | #define FSR_PFAULT 0x00000007 /* Translation Page */ | |
| 358 | #define FSR_SACCESS 0x00000003 /* Section access */ | |
| 359 | #define FSR_PACCESS 0x00000006 /* Page Access */ | |
| 360 | #define FSR_SDOM 0x00000009 /* Domain Section */ | |
| 361 | #define FSR_PDOM 0x0000000B /* Domain Page */ | |
| 362 | #define FSR_SPERM 0x0000000D /* Permission Section */ | |
| 363 | #define FSR_PPERM 0x0000000F /* Permission Page */ | |
| 364 | #define FSR_EXT 0x00001000 /* External (Implementation Defined Classification) */ | |
| 365 | ||
| 366 | #define FSR_MASK 0x0000040F /* Valid bits */ | |
| 367 | #define FSR_ALIGN_MASK 0x0000040D /* Valid bits to check align */ | |
| 368 | ||
| 369 | #define DFSR_WRITE 0x00000800 /* write data abort fault */ | |
| 5ba3f43e | 370 | |
| d9a64523 | 371 | #if defined (ARMA7) || defined (APPLE_ARM64_ARCH_FAMILY) || defined (BCM2837) |
| 5ba3f43e | 372 | |
| cb323159 A |
373 | #define TEST_FSR_VMFAULT(status) \ |
| 374 | (((status) == FSR_PFAULT) \ | |
| 375 | || ((status) == FSR_PPERM) \ | |
| 376 | || ((status) == FSR_SFAULT) \ | |
| 377 | || ((status) == FSR_SPERM) \ | |
| 378 | || ((status) == FSR_ICFAULT) \ | |
| 379 | || ((status) == FSR_SACCESS) \ | |
| 380 | || ((status) == FSR_PACCESS)) | |
| 5ba3f43e | 381 | |
| 0a7de745 A |
382 | #define TEST_FSR_TRANSLATION_FAULT(status) \ |
| 383 | (((status) == FSR_SFAULT) \ | |
| 384 | || ((status) == FSR_PFAULT)) | |
| d9a64523 | 385 | |
| 5ba3f43e A |
386 | #else |
| 387 | ||
| 388 | #error Incompatible CPU type configured | |
| 389 | ||
| 390 | #endif | |
| 391 | ||
| 392 | /* | |
| 393 | * Cache configuration | |
| 394 | */ | |
| 395 | ||
| 396 | #if defined (ARMA7) | |
| 397 | ||
| 398 | /* I-Cache */ | |
| cb323159 | 399 | #define MMU_I_CLINE 5 /* cache line size as 1<<MMU_I_CLINE (32) */ |
| 5ba3f43e A |
400 | |
| 401 | /* D-Cache */ | |
| cb323159 A |
402 | #define MMU_CSIZE 15 /* cache size as 1<<MMU_CSIZE (32K) */ |
| 403 | #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ | |
| 404 | #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */ | |
| 405 | #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ | |
| 406 | #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ | |
| 5ba3f43e | 407 | |
| cb323159 A |
408 | #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */ |
| 409 | #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */ | |
| 5ba3f43e | 410 | |
| 0a7de745 | 411 | #define __ARM_L2CACHE__ 1 |
| 5ba3f43e | 412 | |
| cb323159 A |
413 | #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<MMU_CSIZE */ |
| 414 | #define L2_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ | |
| 415 | #define L2_NWAY 3 /* set associativity 1<<MMU_NWAY (8) */ | |
| 416 | #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ | |
| 417 | #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ | |
| 418 | #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<MMU_I9WAY */ | |
| 5ba3f43e | 419 | |
| cb323159 A |
420 | #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<MMU_SWAY */ |
| 421 | #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<MMU_NSET */ | |
| 5ba3f43e A |
422 | |
| 423 | #elif defined (APPLETYPHOON) | |
| 424 | ||
| 425 | /* I-Cache */ | |
| cb323159 | 426 | #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ |
| 5ba3f43e A |
427 | |
| 428 | /* D-Cache */ | |
| cb323159 A |
429 | #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */ |
| 430 | #define MMU_CLINE 6 /* cache line size as 1<<MMU_CLINE (64) */ | |
| 431 | #define MMU_NWAY 1 /* set associativity 1<<MMU_NWAY (2) */ | |
| 432 | #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ | |
| 433 | #define MMU_I7WAY 31 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ | |
| 434 | #define MMU_I9WAY 31 /* cp15 c9 way incrementer 1<<MMU_I9WAY */ | |
| 5ba3f43e | 435 | |
| cb323159 A |
436 | #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */ |
| 437 | #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */ | |
| 5ba3f43e | 438 | |
| 0a7de745 | 439 | #define __ARM_L2CACHE__ 1 |
| 5ba3f43e | 440 | |
| cb323159 A |
441 | #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */ |
| 442 | #define L2_CLINE 6 /* cache line size as 1<<L2_CLINE (64) */ | |
| 443 | #define L2_NWAY 3 /* set associativity 1<<L2_NWAY (8) */ | |
| 444 | #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */ | |
| 445 | #define L2_I7WAY 29 /* cp15 c7 way incrementer 1<<L2_I7WAY */ | |
| 446 | #define L2_I9WAY 29 /* cp15 c9 way incrementer 1<<L2_I9WAY */ | |
| 5ba3f43e | 447 | |
| cb323159 A |
448 | #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */ |
| 449 | #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */ | |
| 5ba3f43e A |
450 | |
| 451 | #elif defined (APPLETWISTER) | |
| 452 | ||
| 453 | /* I-Cache */ | |
| cb323159 | 454 | #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ |
| 5ba3f43e A |
455 | |
| 456 | /* D-Cache */ | |
| cb323159 A |
457 | #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */ |
| 458 | #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ | |
| 459 | #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */ | |
| 460 | #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ | |
| 461 | #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ | |
| 462 | #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */ | |
| 5ba3f43e | 463 | |
| cb323159 A |
464 | #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */ |
| 465 | #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */ | |
| 5ba3f43e A |
466 | |
| 467 | /* L2-Cache */ | |
| 468 | #define __ARM_L2CACHE__ 1 | |
| 469 | ||
| 470 | /* | |
| 471 | * For reasons discussed in the platform expert code, we round the reported | |
| 472 | * L2 size to 4MB, and adjust the other parameters accordingly. | |
| 473 | */ | |
| cb323159 A |
474 | #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */ |
| 475 | #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */ | |
| 476 | #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */ | |
| 477 | #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */ | |
| 478 | #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */ | |
| 479 | #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */ | |
| 5ba3f43e | 480 | |
| cb323159 A |
481 | #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */ |
| 482 | #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */ | |
| 5ba3f43e A |
483 | |
| 484 | #elif defined (APPLEHURRICANE) | |
| 485 | ||
| 486 | /* I-Cache */ | |
| cb323159 | 487 | #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ |
| 5ba3f43e A |
488 | |
| 489 | /* D-Cache */ | |
| cb323159 A |
490 | #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */ |
| 491 | #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ | |
| 492 | #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */ | |
| 493 | #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ | |
| 494 | #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ | |
| 495 | #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */ | |
| 5ba3f43e | 496 | |
| cb323159 A |
497 | #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */ |
| 498 | #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */ | |
| 5ba3f43e A |
499 | |
| 500 | /* L2-Cache */ | |
| 501 | #define __ARM_L2CACHE__ 1 | |
| 502 | ||
| 503 | /* | |
| 504 | * For reasons discussed in the platform expert code, we round the reported | |
| 505 | * L2 size to 4MB, and adjust the other parameters accordingly. | |
| 506 | */ | |
| cb323159 A |
507 | #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */ |
| 508 | #define L2_CLINE 6 /* cache line size as 1<<L2_CSIZE (64) */ | |
| 509 | #define L2_NWAY 4 /* set associativity as 1<<L2_CLINE (16, is actually 12) */ | |
| 510 | #define L2_I7SET 6 /* cp15 c7 set incrementer 1<<L2_I7SET */ | |
| 511 | #define L2_I7WAY 28 /* cp15 c7 way incrementer 1<<L2_I7WAY */ | |
| 512 | #define L2_I9WAY 28 /* cp15 c9 way incremenber 1<<L2_I9WAY */ | |
| 5ba3f43e | 513 | |
| cb323159 A |
514 | #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */ |
| 515 | #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */ | |
| 5ba3f43e | 516 | |
| d9a64523 A |
517 | #elif defined (APPLEMONSOON) |
| 518 | ||
| 519 | /* I-Cache, 96KB for Monsoon, 48KB for Mistral, 6-way. */ | |
| cb323159 | 520 | #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ |
| d9a64523 A |
521 | |
| 522 | /* D-Cache, 64KB for Monsoon, 32KB for Mistral, 4-way. */ | |
| cb323159 A |
523 | #define MMU_CSIZE 16 /* cache size as 1<<MMU_CSIZE (64K) */ |
| 524 | #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ | |
| 525 | #define MMU_NWAY 2 /* set associativity 1<<MMU_NWAY (4) */ | |
| 526 | #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ | |
| 527 | #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ | |
| 528 | #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */ | |
| d9a64523 | 529 | |
| cb323159 A |
530 | #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */ |
| 531 | #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */ | |
| d9a64523 A |
532 | |
| 533 | /* L2-Cache */ | |
| 534 | #define __ARM_L2CACHE__ 1 | |
| 535 | ||
| 536 | /* | |
| 537 | * LLC (Monsoon L2, Mistral L3): 8MB, 128-byte lines, 16-way. | |
| 538 | * L2E (Mistral L2): 1MB, 64-byte lines, 8-way. | |
| 539 | * | |
| 540 | * TODO: Our L2 cahes have different line sizes. I begin to suspect | |
| 541 | * this may be a problem. | |
| 542 | */ | |
| cb323159 A |
543 | #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */ |
| 544 | #define L2_CLINE 7 /* cache line size as 1<<L2_CLINE (128) */ | |
| 545 | #define L2_NWAY 4 /* set associativity as 1<<L2_NWAY (16) */ | |
| 546 | #define L2_I7SET 6 /* TODO: cp15 c7 set incrementer 1<<L2_I7SET */ | |
| c6bf4f31 A |
547 | #define L2_I7WAY 28 /* TODO: cp15 c7 way incrementer 1<<L2_I7WAY */ |
| 548 | #define L2_I9WAY 28 /* TODO: cp15 c9 way incremenber 1<<L2_I9WAY */ | |
| 549 | ||
| 550 | #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */ | |
| 551 | #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */ | |
| 552 | ||
| 553 | #elif defined (APPLEVORTEX) | |
| 554 | ||
| 555 | /* I-Cache, 128KB 8-way for Vortex, 48KB 6-way for Tempest. */ | |
| 556 | #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ | |
| 557 | ||
| 558 | /* D-Cache, 128KB 8-way for Vortex, 32KB 4-way for Tempest. */ | |
| 559 | #define MMU_CSIZE 17 /* cache size as 1<<MMU_CSIZE (128K) */ | |
| 560 | #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ | |
| 561 | #define MMU_NWAY 3 /* set associativity 1<<MMU_NWAY (8) */ | |
| 562 | #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ | |
| 563 | #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ | |
| 564 | #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */ | |
| 565 | ||
| 566 | #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */ | |
| 567 | #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */ | |
| 568 | ||
| 569 | /* L2-Cache */ | |
| 570 | #define __ARM_L2CACHE__ 1 | |
| 571 | ||
| 572 | /* | |
| 573 | * LLC (Vortex L2): 8MB, 128-byte lines, 16-way. | |
| 574 | * LLC (Tempest L2): 2MB, 128-byte lines, 16-way. | |
| 575 | */ | |
| 576 | #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */ | |
| 577 | #define L2_CLINE 7 /* cache line size as 1<<L2_CLINE (128) */ | |
| 578 | #define L2_NWAY 4 /* set associativity as 1<<L2_NWAY (16) */ | |
| 579 | #define L2_I7SET 6 /* TODO: cp15 c7 set incrementer 1<<L2_I7SET */ | |
| 580 | #define L2_I7WAY 28 /* TODO: cp15 c7 way incrementer 1<<L2_I7WAY */ | |
| 581 | #define L2_I9WAY 28 /* TODO: cp15 c9 way incremenber 1<<L2_I9WAY */ | |
| 582 | ||
| 583 | #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */ | |
| 584 | #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */ | |
| 585 | ||
| 586 | #elif defined (APPLELIGHTNING) | |
| 587 | ||
| 588 | /* I-Cache, 192KB for Lightning, 96KB for Thunder, 6-way. */ | |
| 589 | #define MMU_I_CLINE 6 /* cache line size as 1<<MMU_I_CLINE (64) */ | |
| 590 | ||
| 591 | /* D-Cache, 128KB for Lightning, 8-way. 48KB for Thunder, 6-way. */ | |
| 592 | #define MMU_CSIZE 17 /* cache size as 1<<MMU_CSIZE (128K) */ | |
| 593 | #define MMU_CLINE 6 /* cache line size is 1<<MMU_CLINE (64) */ | |
| 594 | #define MMU_NWAY 3 /* set associativity 1<<MMU_NWAY (8) */ | |
| 595 | #define MMU_I7SET 6 /* cp15 c7 set incrementer 1<<MMU_I7SET */ | |
| 596 | #define MMU_I7WAY 30 /* cp15 c7 way incrementer 1<<MMU_I7WAY */ | |
| 597 | #define MMU_I9WAY 30 /* cp15 c9 way incrementer 1<<MMU_I9WAY */ | |
| 598 | ||
| 599 | #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) /* set size 1<<MMU_SWAY */ | |
| 600 | #define MMU_NSET (MMU_SWAY - MMU_CLINE) /* lines per way 1<<MMU_NSET */ | |
| 601 | ||
| 602 | /* L2-Cache */ | |
| 603 | #define __ARM_L2CACHE__ 1 | |
| 604 | ||
| 605 | /* | |
| 606 | * LLC (Lightning L2): 8MB, 128-byte lines, 16-way. | |
| 607 | * LLC (Thunder L2): 4MB, 128-byte lines, 16-way. | |
| 608 | */ | |
| 609 | #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ /* cache size as 1<<L2_CSIZE */ | |
| 610 | #define L2_CLINE 7 /* cache line size as 1<<L2_CLINE (128) */ | |
| 611 | #define L2_NWAY 4 /* set associativity as 1<<L2_NWAY (16) */ | |
| 612 | #define L2_I7SET 6 /* TODO: cp15 c7 set incrementer 1<<L2_I7SET */ | |
| cb323159 A |
613 | #define L2_I7WAY 28 /* TODO: cp15 c7 way incrementer 1<<L2_I7WAY */ |
| 614 | #define L2_I9WAY 28 /* TODO: cp15 c9 way incremenber 1<<L2_I9WAY */ | |
| d9a64523 | 615 | |
| cb323159 A |
616 | #define L2_SWAY (L2_CSIZE - L2_NWAY) /* set size 1<<L2_SWAY */ |
| 617 | #define L2_NSET (L2_SWAY - L2_CLINE) /* lines per way 1<<L2_NSET */ | |
| d9a64523 A |
618 | |
| 619 | #elif defined (BCM2837) /* Raspberry Pi 3 */ | |
| 620 | ||
| 621 | /* I-Cache. We don't have detailed spec so we just follow the ARM technical reference. */ | |
| cb323159 | 622 | #define MMU_I_CLINE 6 |
| d9a64523 A |
623 | |
| 624 | /* D-Cache. */ | |
| cb323159 A |
625 | #define MMU_CSIZE 15 |
| 626 | #define MMU_CLINE 6 | |
| 627 | #define MMU_NWAY 2 | |
| d9a64523 | 628 | |
| cb323159 A |
629 | #define MMU_I7SET 6 |
| 630 | #define MMU_I7WAY 30 | |
| 631 | #define MMU_I9WAY 30 | |
| d9a64523 | 632 | |
| cb323159 A |
633 | #define MMU_SWAY (MMU_CSIZE - MMU_NWAY) |
| 634 | #define MMU_NSET (MMU_SWAY - MMU_CLINE) | |
| d9a64523 A |
635 | |
| 636 | #define __ARM_L2CACHE__ 1 | |
| 637 | ||
| 0a7de745 A |
638 | #define L2_CSIZE __ARM_L2CACHE_SIZE_LOG__ |
| 639 | #define L2_CLINE 6 | |
| 640 | #define L2_NWAY 4 | |
| 641 | #define L2_I7SET 6 | |
| 642 | #define L2_I7WAY 28 | |
| 643 | #define L2_I9WAY 28 | |
| cb323159 A |
644 | #define L2_SWAY (L2_CSIZE - L2_NWAY) |
| 645 | #define L2_NSET (L2_SWAY - L2_CLINE) | |
| d9a64523 | 646 | |
| 5ba3f43e A |
647 | #else |
| 648 | #error processor not supported | |
| 649 | #endif | |
| 650 | ||
| 651 | ||
| 652 | #if (__ARM_VMSA__ <= 7) | |
| 653 | ||
| 654 | /* | |
| 655 | * SCTLR: System Control Register | |
| 656 | */ | |
| 657 | /* | |
| 658 | * System Control Register (SCTLR) | |
| 659 | * | |
| 660 | * 31 30 29 28 27 25 24 22 21 20 19 17 15 14 13 12 11 10 5 2 1 0 | |
| 661 | * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+ | |
| 662 | * |0|TE|AFE|TRE|NMFI|0|EE|VE|11|FI|UWXN|WXN|1|HA|1|0|RR| V| I| Z|SW|000|1|C15BEN|11|C|A|M| | |
| 663 | * +-+--+---+---+----+-+--+--+--+--+----+---+-+--+-+-+--+--+--+--+--+---+-+------+--+-+-+-+ | |
| 664 | * | |
| cb323159 A |
665 | * Where: |
| 666 | * TE: Thumb Exception enable | |
| 667 | * AFE: Access flag enable | |
| 668 | * TRE: TEX remap enable | |
| 669 | * NMFI: Non-maskable FIQ (NMFI) support | |
| 670 | * EE: Exception Endianness | |
| 671 | * VE: Interrupt Vectors Enable | |
| 672 | * FI: Fast interrupts configuration enable | |
| 673 | * ITD: IT Disable | |
| 674 | * UWXN: Unprivileged write permission implies PL1 XN | |
| 675 | * WXN: Write permission implies XN | |
| 676 | * HA: Hardware Access flag enable | |
| 677 | * RR: Round Robin select | |
| 678 | * V: High exception vectors | |
| 679 | * I: Instruction cache enable | |
| 680 | * Z: Branch prediction enable | |
| 681 | * SW: SWP/SWPB enable | |
| 682 | * C15BEN: CP15 barrier enable | |
| 683 | * C: Cache enable | |
| 684 | * A: Alignment check enable | |
| 685 | * M: MMU enable | |
| 5ba3f43e A |
686 | */ |
| 687 | ||
| cb323159 | 688 | #define SCTLR_RESERVED 0x82DD8394 |
| 5ba3f43e | 689 | |
| cb323159 A |
690 | #define SCTLR_ENABLE 0x00000001 /* MMU enable */ |
| 691 | #define SCTLR_ALIGN 0x00000002 /* Alignment check enable */ | |
| 692 | #define SCTLR_DCACHE 0x00000004 /* Data or Unified Cache enable */ | |
| 693 | #define SCTLR_BEN 0x00000040 /* CP15 barrier enable */ | |
| 694 | #define SCTLR_SW 0x00000400 /* SWP/SWPB Enable */ | |
| 695 | #define SCTLR_PREDIC 0x00000800 /* Branch prediction enable */ | |
| 696 | #define SCTLR_ICACHE 0x00001000 /* Instruction cache enabled. */ | |
| 697 | #define SCTLR_HIGHVEC 0x00002000 /* Vector table at 0xffff0000 */ | |
| 698 | #define SCTLR_RROBIN 0x00004000 /* Round Robin replacement */ | |
| 699 | #define SCTLR_HA 0x00020000 /* Hardware Access flag enable */ | |
| 700 | #define SCTLR_NMFI 0x08000000 /* Non-maskable FIQ */ | |
| 701 | #define SCTLR_TRE 0x10000000 /* TEX remap enable */ | |
| 702 | #define SCTLR_AFE 0x20000000 /* Access flag enable */ | |
| 703 | #define SCTLR_TE 0x40000000 /* Thumb Exception enable */ | |
| 5ba3f43e | 704 | |
| cb323159 A |
705 | #define SCTLR_DEFAULT \ |
| 706 | (SCTLR_AFE|SCTLR_TRE|SCTLR_HIGHVEC|SCTLR_ICACHE|SCTLR_PREDIC|SCTLR_DCACHE|SCTLR_ENABLE) | |
| 5ba3f43e A |
707 | |
| 708 | ||
| 709 | /* | |
| 710 | * PRRR: Primary Region Remap Register | |
| 711 | * | |
| 712 | * 31 24 20 19 18 17 16 0 | |
| 713 | * +---------------------------------------------------------------+ | |
| 714 | * | NOSn | Res |NS1|NS0|DS1|DS0| TRn | | |
| 715 | * +---------------------------------------------------------------+ | |
| 716 | */ | |
| 717 | ||
| cb323159 A |
718 | #define PRRR_NS1 0x00080000 |
| 719 | #define PRRR_NS0 0x00040000 | |
| 720 | #define PRRR_DS1 0x00020000 | |
| 721 | #define PRRR_DS0 0x00010000 | |
| 722 | ||
| 723 | #define PRRR_NOSn_ISH(region) (0x1<<((region)+24)) | |
| 5ba3f43e A |
724 | |
| 725 | #if defined (ARMA7) | |
| cb323159 | 726 | #define PRRR_SETUP (0x1F08022A) |
| 5ba3f43e A |
727 | #else |
| 728 | #error processor not supported | |
| 729 | #endif | |
| 730 | ||
| 731 | /* | |
| 732 | * NMRR, Normal Memory Remap Register | |
| 733 | * | |
| 0a7de745 | 734 | * 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 |
| 5ba3f43e A |
735 | * +---------------------------------------------------------------+ |
| 736 | * |OR7|OR6|OR5|OR4|OR3|OR2|OR1|OR0|IR7|IR6|IR5|IR4|IR3|IR2|IR1|IR0| | |
| 737 | * +---------------------------------------------------------------+ | |
| 738 | */ | |
| 739 | ||
| cb323159 A |
740 | #define NMRR_DISABLED 0x0 /* Non-cacheable */ |
| 741 | #define NMRR_WRITEBACK 0x1 /* Write-Back, Write-Allocate */ | |
| 742 | #define NMRR_WRITETHRU 0x2 /* Write-Through, no Write-Allocate */ | |
| 743 | #define NMRR_WRITEBACKNO 0x3 /* Write-Back, no Write-Allocate */ | |
| 5ba3f43e A |
744 | |
| 745 | #if defined (ARMA7) | |
| cb323159 | 746 | #define NMRR_SETUP (0x01210121) |
| 5ba3f43e A |
747 | #else |
| 748 | #error processor not supported | |
| 749 | #endif | |
| 750 | ||
| 751 | /* | |
| 752 | * TTBR: Translation Table Base Register | |
| 753 | * | |
| 754 | */ | |
| 755 | ||
| cb323159 A |
756 | #define TTBR_IRGN_DISBALED 0x00000000 /* inner non-cacheable */ |
| 757 | #define TTBR_IRGN_WRITEBACK 0x00000040 /* inner write back and allocate */ | |
| 758 | #define TTBR_IRGN_WRITETHRU 0x00000001 /* inner write thru */ | |
| 759 | #define TTBR_IRGN_WRITEBACKNO 0x00000041 /* inner write back no allocate */ | |
| 5ba3f43e | 760 | |
| cb323159 A |
761 | #define TTBR_RGN_DISBALED 0x00000000 /* outer non-cacheable */ |
| 762 | #define TTBR_RGN_WRITEBACK 0x00000008 /* outer write back and allocate */ | |
| 763 | #define TTBR_RGN_WRITETHRU 0x00000010 /* outer write thru outer cache */ | |
| 764 | #define TTBR_RGN_WRITEBACKNO 0x00000018 /* outer write back no allocate */ | |
| 5ba3f43e | 765 | |
| cb323159 A |
766 | #define TTBR_SHARED 0x00000002 /* Shareable memory atribute */ |
| 767 | #define TTBR_SHARED_NOTOUTER 0x00000020 /* Outer not shareable memory atribute */ | |
| 5ba3f43e A |
768 | |
| 769 | #if defined (ARMA7) | |
| cb323159 | 770 | #define TTBR_SETUP (TTBR_RGN_WRITEBACK|TTBR_IRGN_WRITEBACK|TTBR_SHARED) |
| 5ba3f43e A |
771 | #else |
| 772 | #error processor not supported | |
| 773 | #endif | |
| 774 | ||
| 775 | /* | |
| 776 | * TTBCR: Translation Table Base Control register | |
| 777 | * | |
| cb323159 A |
778 | * 31 3 2 0 |
| 779 | * +----------+ | |
| 780 | * | zero | N | | |
| 781 | * +----------+ | |
| 5ba3f43e A |
782 | * |
| 783 | * If N=0, always use translation table base register 0. Otherwise, if | |
| 784 | * bits [31:32-N] of the address are all zero use base register 0. Otherwise, | |
| 785 | * use base register 1. | |
| 786 | * | |
| 787 | * Reading from this register also returns the page table boundary for TTB0. | |
| 788 | * Writing to it updates the boundary for TTB0. (0=16KB, 1=8KB, 2=4KB, etc...) | |
| 789 | */ | |
| 790 | ||
| cb323159 A |
791 | #define TTBCR_N_1GB_TTB0 0x2 /* 1 GB TTB0, 3GB TTB1 */ |
| 792 | #define TTBCR_N_2GB_TTB0 0x1 /* 2 GB TTB0, 2GB TTB1 */ | |
| 793 | #define TTBCR_N_4GB_TTB0 0x0 /* 4 GB TTB0 */ | |
| 794 | #define TTBCR_N_MASK 0x3 | |
| 5ba3f43e A |
795 | |
| 796 | ||
| 797 | ||
| 798 | /* | |
| 799 | * ARM Page Granule | |
| 800 | */ | |
| 0a7de745 | 801 | #define ARM_PGSHIFT 12 |
| 5ba3f43e A |
802 | #define ARM_PGBYTES (1 << ARM_PGSHIFT) |
| 803 | #define ARM_PGMASK (ARM_PGBYTES-1) | |
| 804 | ||
| 805 | /* | |
| 806 | * DACR: Domain Access Control register | |
| 807 | */ | |
| 808 | ||
| cb323159 A |
809 | #define DAC_FAULT 0x0 /* invalid domain - everyone loses */ |
| 810 | #define DAC_CLIENT 0x1 /* client domain - use AP bits */ | |
| 811 | #define DAC_RESERVE 0x2 /* reserved domain - undefined */ | |
| 812 | #define DAC_MANAGER 0x3 /* manager domain - all access */ | |
| 5ba3f43e | 813 | |
| cb323159 | 814 | #define DACR_SET(dom, x) ((x)<<((dom)<<1)) |
| 5ba3f43e | 815 | |
| cb323159 A |
816 | |
| 817 | #define ARM_DOM_DEFAULT 0 /* domain that forces AP use */ | |
| 818 | #define ARM_DAC_SETUP 0x1 | |
| 5ba3f43e A |
819 | |
| 820 | /* | |
| cb323159 | 821 | * ARM 2-level Page Table support |
| 5ba3f43e A |
822 | */ |
| 823 | ||
| 824 | /* | |
| 825 | * Memory Attribute Index | |
| 826 | */ | |
| cb323159 A |
827 | #define CACHE_ATTRINDX_WRITEBACK 0x0 /* cache enabled, buffer enabled */ |
| 828 | #define CACHE_ATTRINDX_WRITECOMB 0x1 /* no cache, buffered writes */ | |
| 829 | #define CACHE_ATTRINDX_WRITETHRU 0x2 /* cache enabled, buffer disabled */ | |
| 830 | #define CACHE_ATTRINDX_DISABLE 0x3 /* no cache, no buffer */ | |
| 831 | #define CACHE_ATTRINDX_INNERWRITEBACK 0x4 /* inner cache enabled, buffer enabled, write allocate */ | |
| 832 | #define CACHE_ATTRINDX_POSTED CACHE_ATTRINDX_DISABLE | |
| 833 | #define CACHE_ATTRINDX_POSTED_REORDERED CACHE_ATTRINDX_DISABLE | |
| 834 | #define CACHE_ATTRINDX_POSTED_COMBINED_REORDERED CACHE_ATTRINDX_DISABLE | |
| 835 | #define CACHE_ATTRINDX_DEFAULT CACHE_ATTRINDX_WRITEBACK | |
| 5ba3f43e A |
836 | |
| 837 | ||
| 838 | /* | |
| 839 | * Access protection bit values | |
| 840 | */ | |
| cb323159 A |
841 | #define AP_RWNA 0x0 /* priv=read-write, user=no-access */ |
| 842 | #define AP_RWRW 0x1 /* priv=read-write, user=read-write */ | |
| 843 | #define AP_RONA 0x2 /* priv=read-only , user=no-access */ | |
| 844 | #define AP_RORO 0x3 /* priv=read-only , user=read-only */ | |
| 5ba3f43e A |
845 | |
| 846 | /* | |
| 847 | * L1 Translation table | |
| 848 | * | |
| 849 | * Each translation table is up to 16KB | |
| 850 | * 4096 32-bit entries of 1MB of address space. | |
| 851 | */ | |
| 852 | ||
| cb323159 A |
853 | #define ARM_TT_L1_SIZE 0x00100000 /* size of area covered by a tte */ |
| 854 | #define ARM_TT_L1_OFFMASK 0x000FFFFF /* offset within an L1 entry */ | |
| 855 | #define ARM_TT_L1_TABLE_OFFMASK 0x000FFFFF /* offset within an L1 entry */ | |
| 856 | #define ARM_TT_L1_BLOCK_OFFMASK 0x000FFFFF /* offset within an L1 entry */ | |
| 857 | #define ARM_TT_L1_SUPER_OFFMASK 0x00FFFFFF /* offset within an L1 entry */ | |
| 858 | #define ARM_TT_L1_SHIFT 20 /* page descriptor shift */ | |
| 859 | #define ARM_TT_L1_INDEX_MASK 0xfff00000 /* mask for getting index in L1 table from virtual address */ | |
| 5ba3f43e | 860 | |
| cb323159 A |
861 | #define ARM_TT_L1_PT_SIZE (4 * ARM_TT_L1_SIZE) /* 4 L1 table entries required to consume 1 L2 pagetable page */ |
| 862 | #define ARM_TT_L1_PT_OFFMASK (ARM_TT_L1_PT_SIZE - 1) | |
| 5ba3f43e A |
863 | |
| 864 | /* | |
| 865 | * L2 Translation table | |
| 866 | * | |
| 867 | * Each translation table is up to 1KB | |
| 868 | * 4096 32-bit entries of 1MB (2^30) of address space. | |
| 869 | */ | |
| 870 | ||
| cb323159 A |
871 | #define ARM_TT_L2_SIZE 0x00001000 /* size of area covered by a tte */ |
| 872 | #define ARM_TT_L2_OFFMASK 0x00000FFF /* offset within an L2 entry */ | |
| 873 | #define ARM_TT_L2_SHIFT 12 /* page descriptor shift */ | |
| 874 | #define ARM_TT_L2_INDEX_MASK 0x000ff000 /* mask for getting index in L2 table from virtual address */ | |
| 5ba3f43e A |
875 | |
| 876 | /* | |
| 877 | * Convenience definitions for: | |
| 878 | * ARM_TT_LEAF: The last level of the configured page table format. | |
| 879 | * ARM_TT_TWIG: The second to last level of the configured page table format. | |
| 5c9f4661 | 880 | * ARM_TT_ROOT: The first level of the configured page table format. |
| 5ba3f43e A |
881 | * |
| 882 | * My apologies to any botanists who may be reading this. | |
| 883 | */ | |
| cb323159 A |
884 | #define ARM_TT_LEAF_SIZE ARM_TT_L2_SIZE |
| 885 | #define ARM_TT_LEAF_OFFMASK ARM_TT_L2_OFFMASK | |
| 886 | #define ARM_TT_LEAF_SHIFT ARM_TT_L2_SHIFT | |
| 887 | #define ARM_TT_LEAF_INDEX_MASK ARM_TT_L2_INDEX_MASK | |
| 5ba3f43e | 888 | |
| cb323159 A |
889 | #define ARM_TT_TWIG_SIZE ARM_TT_L1_SIZE |
| 890 | #define ARM_TT_TWIG_OFFMASK ARM_TT_L1_OFFMASK | |
| 891 | #define ARM_TT_TWIG_SHIFT ARM_TT_L1_SHIFT | |
| 892 | #define ARM_TT_TWIG_INDEX_MASK ARM_TT_L1_INDEX_MASK | |
| 5ba3f43e | 893 | |
| cb323159 A |
894 | #define ARM_TT_ROOT_SIZE ARM_TT_L1_SIZE |
| 895 | #define ARM_TT_ROOT_OFFMASK ARM_TT_L1_OFFMASK | |
| 896 | #define ARM_TT_ROOT_SHIFT ARM_TT_L1_SHIFT | |
| 897 | #define ARM_TT_ROOT_INDEX_MASK ARM_TT_L1_INDEX_MASK | |
| 5c9f4661 | 898 | |
| 5ba3f43e | 899 | /* |
| cb323159 | 900 | * Level 1 Translation Table Entry |
| 5ba3f43e | 901 | * |
| cb323159 | 902 | * page table entry |
| 5ba3f43e | 903 | * |
| cb323159 A |
904 | * 31 10 9 8 5 4 2 0 |
| 905 | * +----------------------+-+----+--+--+--+ | |
| 906 | * | page table base addr | |dom |XN|00|01| | |
| 907 | * +----------------------+-+----+--+--+--+ | |
| 5ba3f43e | 908 | * |
| cb323159 | 909 | * direct (1MB) section entry |
| 5ba3f43e | 910 | * |
| cb323159 A |
911 | * 31 20 18 15 12 10 9 8 5 4 2 0 |
| 912 | * +------------+--+-+-+-+---+--+-+----+--+--+--+ | |
| 913 | * | base addr |00|G|S|A|TEX|AP| |dom |XN|CB|10| | |
| 914 | * +------------+--+-+-+-+---+--+-+----+--+--+--+ | |
| 5ba3f43e A |
915 | * |
| 916 | * super (16MB) section entry | |
| 917 | * | |
| cb323159 A |
918 | * 31 24 23 18 15 12 10 9 8 5 4 2 0 |
| 919 | * +---------+------+-+-+-+---+--+-+----+--+--+--+ | |
| 920 | * |base addr|000001|G|S|A|TEX|AP| |dom |XN|CB|10| | |
| 921 | * +---------+------+-+-+-+---+--+-+----+--+--+--+ | |
| 5ba3f43e A |
922 | * |
| 923 | * where: | |
| cb323159 A |
924 | * 'G' is the notGlobal bit |
| 925 | * 'S' is the shared bit | |
| 926 | * 'A' in the access permission extension (APX) bit | |
| 927 | * 'TEX' remap register control bits | |
| 928 | * 'AP' is the access protection | |
| 929 | * 'dom' is the domain for the translation | |
| 930 | * 'XN' is the eXecute Never bit | |
| 931 | * 'CB' is the cache/buffer attribute | |
| 5ba3f43e A |
932 | */ |
| 933 | ||
| cb323159 | 934 | #define ARM_TTE_EMPTY 0x00000000 /* unasigned entry */ |
| 5ba3f43e | 935 | |
| cb323159 A |
936 | #define ARM_TTE_TYPE_FAULT 0x00000000 /* fault entry type */ |
| 937 | #define ARM_TTE_TYPE_TABLE 0x00000001 /* page table type */ | |
| 938 | #define ARM_TTE_TYPE_BLOCK 0x00000002 /* section entry type */ | |
| 939 | #define ARM_TTE_TYPE_MASK 0x00000003 /* mask for extracting the type */ | |
| 5ba3f43e | 940 | |
| cb323159 A |
941 | #define ARM_TTE_BLOCK_NGSHIFT 17 |
| 942 | #define ARM_TTE_BLOCK_NG_MASK 0x00020000 /* mask to determine notGlobal bit */ | |
| 943 | #define ARM_TTE_BLOCK_NG 0x00020000 /* value for a per-process mapping */ | |
| 5ba3f43e | 944 | |
| cb323159 A |
945 | #define ARM_TTE_BLOCK_SHSHIFT 16 |
| 946 | #define ARM_TTE_BLOCK_SH_MASK 0x00010000 /* shared (SMP) mapping mask */ | |
| 947 | #define ARM_TTE_BLOCK_SH 0x00010000 /* shared (SMP) mapping */ | |
| 5ba3f43e | 948 | |
| cb323159 A |
949 | #define ARM_TTE_BLOCK_CBSHIFT 2 |
| 950 | #define ARM_TTE_BLOCK_CB(x) ((x) << ARM_TTE_BLOCK_CBSHIFT) | |
| 951 | #define ARM_TTE_BLOCK_CB_MASK (3<< ARM_TTE_BLOCK_CBSHIFT) | |
| 5ba3f43e | 952 | |
| cb323159 A |
953 | #define ARM_TTE_BLOCK_AP0SHIFT 10 |
| 954 | #define ARM_TTE_BLOCK_AP0 (1<<ARM_TTE_BLOCK_AP0SHIFT) | |
| 955 | #define ARM_TTE_BLOCK_AP0_MASK (1<<ARM_TTE_BLOCK_AP0SHIFT) | |
| 5ba3f43e | 956 | |
| cb323159 A |
957 | #define ARM_TTE_BLOCK_AP1SHIFT 11 |
| 958 | #define ARM_TTE_BLOCK_AP1 (1<<ARM_TTE_BLOCK_AP1SHIFT) | |
| 959 | #define ARM_TTE_BLOCK_AP1_MASK (1<<ARM_TTE_BLOCK_AP1SHIFT) | |
| 5ba3f43e | 960 | |
| cb323159 A |
961 | #define ARM_TTE_BLOCK_AP2SHIFT 15 |
| 962 | #define ARM_TTE_BLOCK_AP2 (1<<ARM_TTE_BLOCK_AP2SHIFT) | |
| 963 | #define ARM_TTE_BLOCK_AP2_MASK (1<<ARM_TTE_BLOCK_AP2SHIFT) | |
| 5ba3f43e | 964 | |
| 0a7de745 | 965 | /* access protections */ |
| cb323159 A |
966 | #define ARM_TTE_BLOCK_AP(ap) \ |
| 967 | ((((ap)&0x1)<<ARM_TTE_BLOCK_AP1SHIFT) | \ | |
| 968 | ((((ap)>>1)&0x1)<<ARM_TTE_BLOCK_AP2SHIFT)) | |
| 5ba3f43e | 969 | |
| 0a7de745 | 970 | /* mask access protections */ |
| cb323159 A |
971 | #define ARM_TTE_BLOCK_APMASK \ |
| 972 | (ARM_TTE_BLOCK_AP1_MASK | ARM_TTE_BLOCK_AP2_MASK) | |
| 5ba3f43e | 973 | |
| cb323159 A |
974 | #define ARM_TTE_BLOCK_AF ARM_TTE_BLOCK_AP0 /* value for access */ |
| 975 | #define ARM_TTE_BLOCK_AFMASK ARM_TTE_BLOCK_AP0_MASK /* access mask */ | |
| 5ba3f43e | 976 | |
| cb323159 A |
977 | #define ARM_TTE_TABLE_MASK 0xFFFFFC00 /* mask for a L2 page table entry */ |
| 978 | #define ARM_TTE_TABLE_SHIFT 10 /* shift for L2 page table phys address */ | |
| 5ba3f43e | 979 | |
| cb323159 A |
980 | #define ARM_TTE_BLOCK_L1_MASK 0xFFF00000 /* mask to extract phys address from L1 section entry */ |
| 981 | #define ARM_TTE_BLOCK_L1_SHIFT 20 /* shift for 1MB section phys address */ | |
| 5ba3f43e | 982 | |
| cb323159 A |
983 | #define ARM_TTE_SUPER_L1_MASK 0xFF000000 /* mask to extract phys address from L1 super entry */ |
| 984 | #define ARM_TTE_SUPER_L1_SHIFT 24 /* shift for 16MB section phys address */ | |
| 5ba3f43e | 985 | |
| cb323159 A |
986 | #define ARM_TTE_BLOCK_SUPER 0x00040000 /* make section a 16MB section */ |
| 987 | #define ARM_TTE_BLOCK_SUPER_MASK 0x00F40000 /* make section a 16MB section */ | |
| 5ba3f43e | 988 | |
| cb323159 A |
989 | #define ARM_TTE_BLOCK_NXSHIFT 4 |
| 990 | #define ARM_TTE_BLOCK_NX 0x00000010 /* section is no execute */ | |
| 991 | #define ARM_TTE_BLOCK_NX_MASK 0x00000010 /* mask for extracting no execute bit */ | |
| 992 | #define ARM_TTE_BLOCK_PNX ARM_TTE_BLOCK_NX | |
| 5ba3f43e | 993 | |
| cb323159 A |
994 | #define ARM_TTE_BLOCK_TEX0SHIFT 12 |
| 995 | #define ARM_TTE_BLOCK_TEX0 (1<<ARM_TTE_BLOCK_TEX0SHIFT) | |
| 996 | #define ARM_TTE_BLOCK_TEX0_MASK (1<<ARM_TTE_BLOCK_TEX0SHIFT) | |
| 5ba3f43e | 997 | |
| cb323159 A |
998 | #define ARM_TTE_BLOCK_TEX1SHIFT 13 |
| 999 | #define ARM_TTE_BLOCK_TEX1 (1<<ARM_TTE_BLOCK_TEX1SHIFT) | |
| 1000 | #define ARM_TTE_BLOCK_TEX1_MASK (1<<ARM_TTE_BLOCK_TEX1SHIFT) | |
| 5ba3f43e | 1001 | |
| cb323159 A |
1002 | #define ARM_TTE_BLOCK_TEX2SHIFT 14 |
| 1003 | #define ARM_TTE_BLOCK_TEX2 (1<<ARM_TTE_BLOCK_TEX2SHIFT) | |
| 1004 | #define ARM_TTE_BLOCK_TEX2_MASK (1<<ARM_TTE_BLOCK_TEX2SHIFT) | |
| 5ba3f43e A |
1005 | |
| 1006 | ||
| 0a7de745 | 1007 | /* mask memory attributes index */ |
| cb323159 A |
1008 | #define ARM_TTE_BLOCK_ATTRINDX(i) \ |
| 1009 | ((((i)&0x3)<<ARM_TTE_BLOCK_CBSHIFT) | \ | |
| 1010 | ((((i)>>2)&0x1)<<ARM_TTE_BLOCK_TEX0SHIFT)) | |
| 5ba3f43e | 1011 | |
| 0a7de745 | 1012 | /* mask memory attributes index */ |
| cb323159 A |
1013 | #define ARM_TTE_BLOCK_ATTRINDXMASK \ |
| 1014 | (ARM_TTE_BLOCK_CB_MASK | ARM_TTE_BLOCK_TEX0_MASK) | |
| 5ba3f43e A |
1015 | |
| 1016 | ||
| 1017 | /* | |
| 1018 | * Level 2 Page table entries | |
| 1019 | * | |
| 1020 | * The following page table entry types are possible: | |
| 1021 | * | |
| cb323159 A |
1022 | * fault page entry |
| 1023 | * 31 2 0 | |
| 1024 | * +----------------------------------------+--+ | |
| 1025 | * | ignored |00| | |
| 1026 | * +----------------------------------------+--+ | |
| 5ba3f43e | 1027 | * |
| cb323159 A |
1028 | * large (64KB) page entry |
| 1029 | * 31 16 15 12 9 6 4 3 2 0 | |
| 1030 | * +----------------+--+---+-+-+-+---+--+-+-+--+ | |
| 1031 | * | base phys addr |XN|TEX|G|S|A|000|AP|C|B|01| | |
| 1032 | * +----------------+--+---+-+-+-+---+--+-+-+--+ | |
| 5ba3f43e | 1033 | * |
| cb323159 A |
1034 | * small (4KB) page entry |
| 1035 | * 31 12 9 6 4 3 2 1 0 | |
| 1036 | * +-----------------------+-+-+-+---+--+-+-+-+--+ | |
| 1037 | * | base phys addr |G|S|A|TEX|AP|C|B|1|XN| | |
| 1038 | * +-----------------------+-+-+-+---+--+-+-+-+--+ | |
| 5ba3f43e A |
1039 | * |
| 1040 | * also where: | |
| cb323159 A |
1041 | * 'XN' is the eXecute Never bit |
| 1042 | * 'G' is the notGlobal (process-specific) bit | |
| 1043 | * 'S' is the shared bit | |
| 1044 | * 'A' in the access permission extension (ATX) bit | |
| 1045 | * 'TEX' remap register control bits | |
| 1046 | * 'AP' is the access protection | |
| 1047 | * 'dom' is the domain for the translation | |
| 1048 | * 'C' is the cache attribute | |
| 1049 | * 'B' is the write buffer attribute | |
| 5ba3f43e A |
1050 | */ |
| 1051 | ||
| 5ba3f43e | 1052 | /* markers for (invalid) PTE for a page sent to compressor */ |
| cb323159 A |
1053 | #define ARM_PTE_COMPRESSED ARM_PTE_TEX1 /* compressed... */ |
| 1054 | #define ARM_PTE_COMPRESSED_ALT ARM_PTE_TEX2 /* ... and was "alt_acct" */ | |
| 0a7de745 | 1055 | #define ARM_PTE_COMPRESSED_MASK (ARM_PTE_COMPRESSED | ARM_PTE_COMPRESSED_ALT) |
| cb323159 A |
1056 | #define ARM_PTE_IS_COMPRESSED(x, p) \ |
| 1057 | ((((x) & 0x3) == 0) && /* PTE is not valid... */ \ | |
| 1058 | ((x) & ARM_PTE_COMPRESSED) && /* ...has "compressed" marker" */ \ | |
| 1059 | ((!((x) & ~ARM_PTE_COMPRESSED_MASK)) || /* ...no other bits */ \ | |
| 1060 | (panic("compressed PTE %p 0x%x has extra bits 0x%x: corrupted?", \ | |
| 1061 | (p), (x), (x) & ~ARM_PTE_COMPRESSED_MASK), FALSE))) | |
| 1062 | ||
| 1063 | #define PTE_SHIFT 2 /* shift width of a pte (sizeof(pte) == (1 << PTE_SHIFT)) */ | |
| 1064 | #define PTE_PGENTRIES (1024 >> PTE_SHIFT) /* number of ptes per page */ | |
| 5ba3f43e | 1065 | |
| cb323159 | 1066 | #define ARM_PTE_EMPTY 0x00000000 /* unasigned - invalid entry */ |
| 5ba3f43e | 1067 | |
| cb323159 A |
1068 | #define ARM_PTE_TYPE_FAULT 0x00000000 /* fault entry type */ |
| 1069 | #define ARM_PTE_TYPE_VALID 0x00000002 /* valid L2 entry */ | |
| 1070 | #define ARM_PTE_TYPE 0x00000002 /* small page entry type */ | |
| 1071 | #define ARM_PTE_TYPE_MASK 0x00000002 /* mask to get pte type */ | |
| 5ba3f43e | 1072 | |
| cb323159 A |
1073 | #define ARM_PTE_NG_MASK 0x00000800 /* mask to determine notGlobal bit */ |
| 1074 | #define ARM_PTE_NG 0x00000800 /* value for a per-process mapping */ | |
| 5ba3f43e | 1075 | |
| cb323159 A |
1076 | #define ARM_PTE_SHSHIFT 10 |
| 1077 | #define ARM_PTE_SHMASK 0x00000400 /* shared (SMP) mapping mask */ | |
| 1078 | #define ARM_PTE_SH 0x00000400 /* shared (SMP) mapping */ | |
| 5ba3f43e | 1079 | |
| cb323159 A |
1080 | #define ARM_PTE_CBSHIFT 2 |
| 1081 | #define ARM_PTE_CB(x) ((x)<<ARM_PTE_CBSHIFT) | |
| 1082 | #define ARM_PTE_CB_MASK (0x3<<ARM_PTE_CBSHIFT) | |
| 5ba3f43e | 1083 | |
| cb323159 A |
1084 | #define ARM_PTE_AP0SHIFT 4 |
| 1085 | #define ARM_PTE_AP0 (1<<ARM_PTE_AP0SHIFT) | |
| 1086 | #define ARM_PTE_AP0_MASK (1<<ARM_PTE_AP0SHIFT) | |
| 5ba3f43e | 1087 | |
| cb323159 A |
1088 | #define ARM_PTE_AP1SHIFT 5 |
| 1089 | #define ARM_PTE_AP1 (1<<ARM_PTE_AP1SHIFT) | |
| 1090 | #define ARM_PTE_AP1_MASK (1<<ARM_PTE_AP1SHIFT) | |
| 1091 | ||
| 1092 | #define ARM_PTE_AP2SHIFT 9 | |
| 1093 | #define ARM_PTE_AP2 (1<<ARM_PTE_AP2SHIFT) | |
| 1094 | #define ARM_PTE_AP2_MASK (1<<ARM_PTE_AP2SHIFT) | |
| 5ba3f43e | 1095 | |
| 0a7de745 | 1096 | /* access protections */ |
| cb323159 A |
1097 | #define ARM_PTE_AP(ap) \ |
| 1098 | ((((ap)&0x1)<<ARM_PTE_AP1SHIFT) | \ | |
| 1099 | ((((ap)>>1)&0x1)<<ARM_PTE_AP2SHIFT)) | |
| 5ba3f43e | 1100 | |
| 0a7de745 | 1101 | /* mask access protections */ |
| cb323159 A |
1102 | #define ARM_PTE_APMASK \ |
| 1103 | (ARM_PTE_AP1_MASK | ARM_PTE_AP2_MASK) | |
| 5ba3f43e | 1104 | |
| cb323159 A |
1105 | #define ARM_PTE_AF ARM_PTE_AP0 /* value for access */ |
| 1106 | #define ARM_PTE_AFMASK ARM_PTE_AP0_MASK /* access mask */ | |
| 5ba3f43e | 1107 | |
| cb323159 A |
1108 | #define ARM_PTE_PAGE_MASK 0xFFFFF000 /* mask for a small page */ |
| 1109 | #define ARM_PTE_PAGE_SHIFT 12 /* page shift for 4KB page */ | |
| 5ba3f43e | 1110 | |
| cb323159 A |
1111 | #define ARM_PTE_NXSHIFT 0 |
| 1112 | #define ARM_PTE_NX 0x00000001 /* small page no execute */ | |
| 1113 | #define ARM_PTE_NX_MASK (1<<ARM_PTE_NXSHIFT) | |
| 5ba3f43e | 1114 | |
| cb323159 A |
1115 | #define ARM_PTE_PNXSHIFT 0 |
| 1116 | #define ARM_PTE_PNX 0x00000000 /* no privilege execute. not impl */ | |
| 1117 | #define ARM_PTE_PNX_MASK (0<<ARM_PTE_NXSHIFT) | |
| 5ba3f43e | 1118 | |
| cb323159 A |
1119 | #define ARM_PTE_TEX0SHIFT 6 |
| 1120 | #define ARM_PTE_TEX0 (1<<ARM_PTE_TEX0SHIFT) | |
| 1121 | #define ARM_PTE_TEX0_MASK (1<<ARM_PTE_TEX0SHIFT) | |
| 5ba3f43e | 1122 | |
| cb323159 A |
1123 | #define ARM_PTE_TEX1SHIFT 7 |
| 1124 | #define ARM_PTE_TEX1 (1<<ARM_PTE_TEX1SHIFT) | |
| 1125 | #define ARM_PTE_TEX1_MASK (1<<ARM_PTE_TEX1SHIFT) | |
| 5ba3f43e | 1126 | |
| cb323159 A |
1127 | #define ARM_PTE_WRITEABLESHIFT ARM_PTE_TEX1SHIFT |
| 1128 | #define ARM_PTE_WRITEABLE ARM_PTE_TEX1 | |
| 1129 | #define ARM_PTE_WRITEABLE_MASK ARM_PTE_TEX1_MASK | |
| 5ba3f43e | 1130 | |
| cb323159 A |
1131 | #define ARM_PTE_TEX2SHIFT 8 |
| 1132 | #define ARM_PTE_TEX2 (1<<ARM_PTE_TEX2SHIFT) | |
| 1133 | #define ARM_PTE_TEX2_MASK (1<<ARM_PTE_TEX2SHIFT) | |
| 5ba3f43e | 1134 | |
| cb323159 A |
1135 | #define ARM_PTE_WIREDSHIFT ARM_PTE_TEX2SHIFT |
| 1136 | #define ARM_PTE_WIRED ARM_PTE_TEX2 | |
| 1137 | #define ARM_PTE_WIRED_MASK ARM_PTE_TEX2_MASK | |
| 5ba3f43e | 1138 | |
| 0a7de745 | 1139 | /* mask memory attributes index */ |
| cb323159 A |
1140 | #define ARM_PTE_ATTRINDX(indx) \ |
| 1141 | ((((indx)&0x3)<<ARM_PTE_CBSHIFT) | \ | |
| 1142 | ((((indx)>>2)&0x1)<<ARM_PTE_TEX0SHIFT)) | |
| 5ba3f43e | 1143 | |
| 0a7de745 | 1144 | /* mask memory attributes index */ |
| cb323159 A |
1145 | #define ARM_PTE_ATTRINDXMASK \ |
| 1146 | (ARM_PTE_CB_MASK | ARM_PTE_TEX0_MASK) | |
| 1147 | ||
| 1148 | #define ARM_SMALL_PAGE_SIZE (4096) /* 4KB */ | |
| 1149 | #define ARM_LARGE_PAGE_SIZE (64*1024) /* 64KB */ | |
| 1150 | #define ARM_SECTION_SIZE (1024*1024) /* 1MB */ | |
| 1151 | #define ARM_SUPERSECTION_SIZE (16*1024*1024) /* 16MB */ | |
| 1152 | ||
| 1153 | #define TLBI_ADDR_SHIFT (12) | |
| 1154 | #define TLBI_ADDR_SIZE (20) | |
| 1155 | #define TLBI_ADDR_MASK (((1ULL << TLBI_ADDR_SIZE) - 1)) | |
| 1156 | #define TLBI_ASID_SHIFT (0) | |
| 1157 | #define TLBI_ASID_SIZE (8) | |
| 1158 | #define TLBI_ASID_MASK (((1ULL << TLBI_ASID_SIZE) - 1)) | |
| 5ba3f43e A |
1159 | #endif |
| 1160 | ||
| 1161 | /* | |
| 1162 | * Format of the Debug Status and Control Register (DBGDSCR) | |
| 1163 | */ | |
| cb323159 A |
1164 | #define ARM_DBGDSCR_RXFULL (1 << 30) |
| 1165 | #define ARM_DBGDSCR_TXFULL (1 << 29) | |
| 1166 | #define ARM_DBGDSCR_RXFULL_1 (1 << 27) | |
| 1167 | #define ARM_DBGDSCR_TXFULL_1 (1 << 26) | |
| 1168 | #define ARM_DBGDSCR_PIPEADV (1 << 25) | |
| 1169 | #define ARM_DBGDSCR_INSTRCOMPL_1 (1 << 24) | |
| 1170 | #define ARM_DBGDSCR_EXTDCCMODE_MASK (3 << 20) | |
| 1171 | #define ARM_DBGDSCR_EXTDCCMODE_NONBLOCKING (0 << 20) | |
| 1172 | #define ARM_DBGDSCR_EXTDCCMODE_STALL (1 << 20) | |
| 1173 | #define ARM_DBGDSCR_EXTDCCMODE_FAST (1 << 20) | |
| 1174 | #define ARM_DBGDSCR_ADADISCARD (1 << 19) | |
| 1175 | #define ARM_DBGDSCR_NS (1 << 18) | |
| 1176 | #define ARM_DBGDSCR_SPNIDDIS (1 << 17) | |
| 1177 | #define ARM_DBGDSCR_SPIDDIS (1 << 16) | |
| 1178 | #define ARM_DBGDSCR_MDBGEN (1 << 15) | |
| 1179 | #define ARM_DBGDSCR_HDBGEN (1 << 14) | |
| 1180 | #define ARM_DBGDSCR_ITREN (1 << 13) | |
| 1181 | #define ARM_DBGDSCR_UDCCDIS (1 << 12) | |
| 1182 | #define ARM_DBGDSCR_INTDIS (1 << 11) | |
| 1183 | #define ARM_DBGDSCR_DBGACK (1 << 10) | |
| 1184 | #define ARM_DBGDSCR_DBGNOPWRDWN (1 << 9) | |
| 1185 | #define ARM_DBGDSCR_UND_1 (1 << 8) | |
| 1186 | #define ARM_DBGDSCR_ADABORT_1 (1 << 7) | |
| 1187 | #define ARM_DBGDSCR_SDABORT_1 (1 << 6) | |
| 1188 | #define ARM_DBGDSCR_MOE_MASK (15 << 2) | |
| 1189 | #define ARM_DBGDSCR_MOE_HALT_REQUEST (0 << 2) | |
| 1190 | #define ARM_DBGDSCR_MOE_BREAKPOINT (1 << 2) | |
| 1191 | #define ARM_DBGDSCR_MOE_ASYNC_WATCHPOINT (2 << 2) | |
| 1192 | #define ARM_DBGDSCR_MOE_BKPT_INSTRUCTION (3 << 2) | |
| 1193 | #define ARM_DBGDSCR_MOE_EXT_DEBUG_REQ (4 << 2) | |
| 1194 | #define ARM_DBGDSCR_MOE_VECTOR_CATCH (5 << 2) | |
| 1195 | #define ARM_DBGDSCR_MOE_DSIDE_ABORT (6 << 2) | |
| 1196 | #define ARM_DBGDSCR_MOE_ISIDE_ABORT (7 << 2) | |
| 1197 | #define ARM_DBGDSCR_MOE_OS_UNLOCK_CATCH (8 << 2) | |
| 1198 | #define ARM_DBGDSCR_MOE_SYNC_WATCHPOINT (10 << 2) | |
| 1199 | ||
| 1200 | #define ARM_DBGDSCR_RESTARTED (1 << 1) | |
| 1201 | #define ARM_DBGDSCR_HALTED (1 << 0) | |
| 5ba3f43e A |
1202 | |
| 1203 | /* | |
| 1204 | * Format of the Debug & Watchpoint Breakpoint Value and Control Registers | |
| 1205 | * Using ARMv7 names; ARMv6 and ARMv6.1 are bit-compatible | |
| 1206 | */ | |
| cb323159 A |
1207 | #define ARM_DBG_VR_ADDRESS_MASK 0xFFFFFFFC /* BVR & WVR */ |
| 1208 | #define ARM_DBGBVR_CONTEXTID_MASK 0xFFFFFFFF /* BVR only */ | |
| 5ba3f43e | 1209 | |
| cb323159 A |
1210 | #define ARM_DBG_CR_ADDRESS_MASK_MASK 0x1F000000 /* BCR & WCR */ |
| 1211 | #define ARM_DBGBCR_MATCH_MASK (1 << 22) /* BCR only */ | |
| 5ba3f43e A |
1212 | #define ARM_DBGBCR_MATCH_MATCH (0 << 22) |
| 1213 | #define ARM_DBGBCR_MATCH_MISMATCH (1 << 22) | |
| cb323159 | 1214 | #define ARM_DBGBCR_TYPE_MASK (1 << 21) /* BCR only */ |
| 5ba3f43e A |
1215 | #define ARM_DBGBCR_TYPE_IVA (0 << 21) |
| 1216 | #define ARM_DBGBCR_TYPE_CONTEXTID (1 << 21) | |
| cb323159 | 1217 | #define ARM_DBG_CR_LINKED_MASK (1 << 20) /* BCR & WCR */ |
| 5ba3f43e A |
1218 | #define ARM_DBG_CR_LINKED_LINKED (1 << 20) |
| 1219 | #define ARM_DBG_CR_LINKED_UNLINKED (0 << 20) | |
| cb323159 A |
1220 | #define ARM_DBG_CR_LINKED_BRP_MASK 0x000F0000 /* BCR & WCR */ |
| 1221 | #define ARM_DBG_CR_SECURITY_STATE_MASK (3 << 14) /* BCR & WCR */ | |
| 5ba3f43e A |
1222 | #define ARM_DBG_CR_SECURITY_STATE_BOTH (0 << 14) |
| 1223 | #define ARM_DBG_CR_SECURITY_STATE_NONSECURE (1 << 14) | |
| 1224 | #define ARM_DBG_CR_SECURITY_STATE_SECURE (2 << 14) | |
| cb323159 | 1225 | #define ARM_DBG_CR_HIGHER_MODE_MASK (1 << 13) /* BCR & WCR */ |
| a39ff7e2 A |
1226 | #define ARM_DBG_CR_HIGHER_MODE_ENABLE (1 << 13) |
| 1227 | #define ARM_DBG_CR_HIGHER_MODE_DISABLE (0 << 13) | |
| cb323159 A |
1228 | #define ARM_DBGWCR_BYTE_ADDRESS_SELECT_MASK 0x00001FE0 /* WCR only */ |
| 1229 | #define ARM_DBG_CR_BYTE_ADDRESS_SELECT_MASK 0x000001E0 /* BCR & WCR */ | |
| 1230 | #define ARM_DBGWCR_ACCESS_CONTROL_MASK (3 << 3) /* WCR only */ | |
| 5ba3f43e A |
1231 | #define ARM_DBCWCR_ACCESS_CONTROL_LOAD (1 << 3) |
| 1232 | #define ARM_DBCWCR_ACCESS_CONTROL_STORE (2 << 3) | |
| 1233 | #define ARM_DBCWCR_ACCESS_CONTROL_ANY (3 << 3) | |
| cb323159 A |
1234 | #define ARM_DBG_CR_MODE_CONTROL_MASK (3 << 1) /* BCR & WCR */ |
| 1235 | #define ARM_DBG_CR_MODE_CONTROL_U_S_S (0 << 1) /* BCR only */ | |
| 1236 | #define ARM_DBG_CR_MODE_CONTROL_PRIVILEGED (1 << 1) /* BCR & WCR */ | |
| 1237 | #define ARM_DBG_CR_MODE_CONTROL_USER (2 << 1) /* BCR & WCR */ | |
| 1238 | #define ARM_DBG_CR_MODE_CONTROL_ANY (3 << 1) /* BCR & WCR */ | |
| 1239 | #define ARM_DBG_CR_ENABLE_MASK (1 << 0) /* BCR & WCR */ | |
| 5ba3f43e A |
1240 | #define ARM_DBG_CR_ENABLE_ENABLE (1 << 0) |
| 1241 | #define ARM_DBG_CR_ENABLE_DISABLE (0 << 0) | |
| 1242 | ||
| 1243 | /* | |
| 1244 | * Format of the Device Power-down and Reset Status Register (DBGPRSR) | |
| 1245 | */ | |
| cb323159 A |
1246 | #define ARM_DBGPRSR_STICKY_RESET_STATUS (1 << 3) |
| 1247 | #define ARM_DBGPRSR_RESET_STATUS (1 << 2) | |
| 1248 | #define ARM_DBGPRSR_STICKY_POWERDOWN_STATUS (1 << 1) | |
| 1249 | #define ARM_DBGPRSR_POWERUP_STATUS (1 << 0) | |
| 5ba3f43e | 1250 | |
| 0a7de745 | 1251 | /* |
| 5ba3f43e A |
1252 | * Format of the OS Lock Access (DBGOSLAR) and Lock Access Registers (DBGLAR) |
| 1253 | */ | |
| cb323159 | 1254 | #define ARM_DBG_LOCK_ACCESS_KEY 0xC5ACCE55 |
| 5ba3f43e A |
1255 | |
| 1256 | /* ARMv7 Debug register map */ | |
| cb323159 A |
1257 | #define ARM_DEBUG_OFFSET_DBGDIDR (0x000) |
| 1258 | #define ARM_DEBUG_OFFSET_DBGWFAR (0x018) | |
| 1259 | #define ARM_DEBUG_OFFSET_DBGVCR (0x01C) | |
| 1260 | #define ARM_DEBUG_OFFSET_DBGECR (0x024) | |
| 1261 | #define ARM_DEBUG_OFFSET_DBGDSCCR (0x028) | |
| 1262 | #define ARM_DEBUG_OFFSET_DBGDSMCR (0x02C) | |
| 1263 | #define ARM_DEBUG_OFFSET_DBGDTRRX (0x080) | |
| 1264 | #define ARM_DEBUG_OFFSET_DBGITR (0x084) /* Write-only */ | |
| 1265 | #define ARM_DEBUG_OFFSET_DBGPCSR (0x084) /* Read-only */ | |
| 1266 | #define ARM_DEBUG_OFFSET_DBGDSCR (0x088) | |
| 1267 | #define ARM_DEBUG_OFFSET_DBGDTRTX (0x08C) | |
| 1268 | #define ARM_DEBUG_OFFSET_DBGDRCR (0x090) | |
| 1269 | #define ARM_DEBUG_OFFSET_DBGBVR (0x100) /* 0x100 - 0x13C */ | |
| 1270 | #define ARM_DEBUG_OFFSET_DBGBCR (0x140) /* 0x140 - 0x17C */ | |
| 1271 | #define ARM_DEBUG_OFFSET_DBGWVR (0x180) /* 0x180 - 0x1BC */ | |
| 1272 | #define ARM_DEBUG_OFFSET_DBGWCR (0x1C0) /* 0x1C0 - 0x1FC */ | |
| 1273 | #define ARM_DEBUG_OFFSET_DBGOSLAR (0x300) | |
| 1274 | #define ARM_DEBUG_OFFSET_DBGOSLSR (0x304) | |
| 1275 | #define ARM_DEBUG_OFFSET_DBGOSSRR (0x308) | |
| 1276 | #define ARM_DEBUG_OFFSET_DBGPRCR (0x310) | |
| 1277 | #define ARM_DEBUG_OFFSET_DBGPRSR (0x314) | |
| 1278 | #define ARM_DEBUG_OFFSET_DBGITCTRL (0xF00) | |
| 1279 | #define ARM_DEBUG_OFFSET_DBGCLAIMSET (0xFA0) | |
| 1280 | #define ARM_DEBUG_OFFSET_DBGCLAIMCLR (0xFA4) | |
| 1281 | #define ARM_DEBUG_OFFSET_DBGLAR (0xFB0) | |
| 1282 | #define ARM_DEBUG_OFFSET_DBGLSR (0xFB4) | |
| 1283 | #define ARM_DEBUG_OFFSET_DBGAUTHSTATUS (0xFB8) | |
| 1284 | #define ARM_DEBUG_OFFSET_DBGDEVID (0xFC8) | |
| 1285 | #define ARM_DEBUG_OFFSET_DBGDEVTYPE (0xFCC) | |
| 1286 | #define ARM_DEBUG_OFFSET_DBGPID0 (0xFD0) | |
| 1287 | #define ARM_DEBUG_OFFSET_DBGPID1 (0xFD4) | |
| 1288 | #define ARM_DEBUG_OFFSET_DBGPID2 (0xFD8) | |
| 1289 | #define ARM_DEBUG_OFFSET_DBGPID3 (0xFDA) | |
| 1290 | #define ARM_DEBUG_OFFSET_DBGPID4 (0xFDC) | |
| 1291 | #define ARM_DEBUG_OFFSET_DBGCID0 (0xFF0) | |
| 1292 | #define ARM_DEBUG_OFFSET_DBGCID1 (0xFF4) | |
| 1293 | #define ARM_DEBUG_OFFSET_DBGCID2 (0xFF8) | |
| 1294 | #define ARM_DEBUG_OFFSET_DBGCID3 (0xFFA) | |
| 1295 | #define ARM_DEBUG_OFFSET_DBGCID4 (0xFFC) | |
| 5ba3f43e A |
1296 | |
| 1297 | /* | |
| 1298 | * Media and VFP Feature Register 1 (MVFR1) | |
| 1299 | */ | |
| cb323159 | 1300 | #define MVFR_ASIMD_HPFP 0x00100000UL |
| 5ba3f43e | 1301 | |
| 0a7de745 A |
1302 | /* |
| 1303 | * Main ID Register (MIDR) | |
| 1304 | * | |
| 1305 | * 31 24 23 20 19 16 15 4 3 0 | |
| 1306 | * +-----+-----+------+------+-----+ | |
| 1307 | * | IMP | VAR | ARCH | PNUM | REV | | |
| 1308 | * +-----+-----+------+------+-----+ | |
| 1309 | * | |
| 1310 | * where: | |
| 1311 | * IMP: Implementor code | |
| 1312 | * VAR: Variant number | |
| 1313 | * ARCH: Architecture code | |
| 1314 | * PNUM: Primary part number | |
| 1315 | * REV: Minor revision number | |
| 1316 | */ | |
| 1317 | #define MIDR_REV_SHIFT 0 | |
| 1318 | #define MIDR_REV_MASK (0xf << MIDR_REV_SHIFT) | |
| 1319 | #define MIDR_PNUM_SHIFT 4 | |
| 1320 | #define MIDR_PNUM_MASK (0xfff << MIDR_PNUM_SHIFT) | |
| 1321 | #define MIDR_ARCH_SHIFT 16 | |
| 1322 | #define MIDR_ARCH_MASK (0xf << MIDR_ARCH_SHIFT) | |
| 1323 | #define MIDR_VAR_SHIFT 20 | |
| 1324 | #define MIDR_VAR_MASK (0xf << MIDR_VAR_SHIFT) | |
| 1325 | #define MIDR_IMP_SHIFT 24 | |
| 1326 | #define MIDR_IMP_MASK (0xff << MIDR_IMP_SHIFT) | |
| 1327 | ||
| cb323159 A |
1328 | #ifdef __arm__ |
| 1329 | ||
| 1330 | /* Macros meant to make __builtin_arm_* functions easier to use. */ | |
| 1331 | #define MRC_SCTLR 15,0,1,0,0 | |
| 1332 | #define MCR_SCTLR(x) 15,0,(x),1,0,0 | |
| 1333 | ||
| 1334 | #define MRC_ACTLR 15,0,1,0,1 | |
| 1335 | #define MCR_ACTLR(x) 15,0,(x),1,0,1 | |
| 1336 | ||
| 1337 | #endif /* __arm__ */ | |
| 1338 | ||
| 0a7de745 | 1339 | #endif /* _ARM_PROC_REG_H_ */ |